基于Verilog-AMS的高速DAC高层次模型研究
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摘要
本文主要研究基于Verilog-AMS语言的高速D/A转换器的高层次行为模型。论文选取分段式电流舵D/A转换器作为高速D/A转换器的典型结构,系统的将分段式电流舵D/A转换器划分为结构和功能相互独立的各个电路模块,分析各模块功能的行为特点,建立相应的理想行为模型,使用Verilog-AMS语言对行为模型进行描述,同时采用Candence Spectre软件对各行为模型进行仿真,并对仿真波形进行了分析;在此基础上对各理想的行为模型进行了误差分析,根据理想模型和实际的电路的对比,对原有模型进行了修正,修改了模型代码,再次使用Candence Spectre软件对修正后的模型进行仿真,将仿真波形与实际电路的特性进行了比较。结果表明,使用Verilog-AMS语言对模拟部分进行行为级建模能够在很大程度上减少仿真所需要的时间,加快设计进程,并且提高仿真精度。本文的研究工作表明了在D/A转换器的高层次设计中,使用Verilog-AMS语言建立的行为模型代替实际电路模块的可行性和有效性。
The high-level model research of high-speed D/A converters based on Verilog-AMS is studied in this paper. Segmented current-steering DAC is selected as the typical of high-speed DAC. The current-steering DAC is divided into modules which are sorted by structure and function. Behavioral models of these modules are set up with Verilog-AMS, and simulations of the models are done in Candence Spectre.Then analysis of model error is taken. When non-ideal factors are considered as parts of behavioral models, the models are rebuilt, and simulations of them are done once again in Candence Spectre. All the simulation waves are shown in the paper. They are analysed based on corresponding circuit. The simulation result shows that the behavioral model of Verilog-AMS will shorten the time of simulation and improve the precision of simulation. The result validates that replacing the concrete analog circuits with the behavioral model of Verilog-AMS is efficient and feasible.
The high-level model research of high-speed D/A converters based on Verilog-AMS is studied in this paper. Segmented current-steering DAC is selected as the typical of high-speed DAC. The current-steering DAC is divided into modules which are sorted by structure and function. Behavioral models of these modules are set up with Verilog-AMS, and simulations of the models are done in Candence Spectre.Then analysis of model error is taken. When non-ideal factors are considered as parts of behavioral models, the models are rebuilt, and simulations of them are done once again in Candence Spectre. All the simulation waves are shown in the paper. They are analysed based on corresponding circuit. The simulation result shows that the behavioral model of Verilog-AMS will shorten the time of simulation and improve the precision of simulation. The result validates that replacing the concrete analog circuits with the behavioral model of Verilog-AMS is efficient and feasible.
引文
[1] 陈震初.发展我国数据转换电路的几点建议.微电子学, 1998, 28(4):231~235.
[2] Sam Blackman.A low Power, 8-bit, 200MHz Digital-to-Analog Converter: [doctor degreepaper], University of California, California, Berkerly: 1999.
[3] 何艳红.8 位高速 D/A 转换器设计研究:[硕士学位论文],电子科技大学,成都:2004.
[4] Jose Bastos, Augusto M.Marques, Michel S.J.Steyaert, and Willy Sansen.A 12-bit intrinsic accuracy high-speed CMOS DAC.Solid-State Circuits, 1998, 33(12): 13-16.
[5] B.A.A.Antao and A.J.Brodersen, Behavioral Simulation for analog system design verification, IEEE Transactions on VLSI systems, September 1995, pp.1012-1021
[6] Ira Miller and Dan Fitz Patrick and Ramana Aisola, Analog Design with Verilog-AMS, 2100 E.Elliot Rd, Tempe, Arizona 85283.
[7] CADENCE, Verilog-AMS Reference Manual ,1997.
[8] The Designer’s Guide to Verilog-AMS, June 2004.
[9] 杨银堂,朱樟明,朱臻.高速 COMS 数据转换器.第一版.北京:科学出版社,2006:33-54.
[10] R.A.Saleh, B.A.A.Antao, and J.Sign, Multilevel and Mixed-Domain simulation of analog circuits and systems, IEEE Transactions on Computer-aided design of Ics and Systems. Vol.15, No.1, Jan.1996, pp.349-356.
[11] J.M.Fournier and P.Senn.A 100-MHz CMOS DAC for video-Graphic Systems.IEEE J.Solid-State Circuits,1989,vol. 24: 635~639.
[12] S.–Y.Chin and C.–Y.Wu.A 10-bit 125MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources.IEEE J. Solid-state Circuits,1994,vol.29:1374~1380.
[13] A.Abrial,J.Bouvier,J.-M.Fournier,P.Senn,and M. Veillard.A 27-MHz digital-to-analog video processor . IEEE J . Solid-State Circuits , 1998 ,vol.23:1358-1369.
[14] Mehrmanesh S, Vahidfa M B,A slanzade H A , et al.A 12Volt, high PSRR, CMOS bandgap voltage reference [A].IEEE International Symposium on Circuit and Systems[C].Bangkok, 2003: 3812384.
[15] Ka Nang Leung, Mok Philip K T.A sub212V 152ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device [J].IEEE J Solid-State Circuites, 2002; 37 (4) : 5262530.
[16] Buck Arne,McDonald Charles,Lew is Stephen, et al.A CMOS bandgap reference without resistors [J].IEEE J Solid-Stage Circuits, 2002; 37 (1) : 81283.
[17] Annema A J.Low power bandgap references featuring DTMOST s [J].IEEE J Solid-State Circuits, 1999; 34 (7) : 9492955.
[18] Banba Hironori, Shiga Hitoshi, Umezawa Akira, et al. A CMOS bandgap reference circuit with sub-1-V operation [J].IEEE J Solid-State Circuits, 1999; 34 (5) : 6702677.
[19] Nico llini Germano, Senderow icz Daniel.A CMOS bandgap reference for differential signal processing [J].IEEE J Solid-State Circuits, 1991; 26 (1) : 41250
[20] Oguey Henri J , A ebischer Daniel.CMOS current reference without resistance [J ].IEEE J Solid-State Circuits, 1997; 32 (7) : 1132-1135.
[21] Tao Shui, Schreier, R.Hudson, F.Mismatch shaping for a current-mode multibit delta-sigma DAC. Solid-State Circuits, IEEE Journal, 1999, 34(3): 331–338.
[22] 毕查德.拉扎维.模拟 CMOS 集成电路设计.陈贵灿,程军、张瑞智等译.第一版.西安:西安交通大学出版社,2003:319-320.
[23] 茹纪军.高速电流舵型 CMOS 数模转换器的研究与设计:[硕士学位论文],电子科技大学,成都: 2005.
[24] 江金光,何恰刚,吴杰.12 位 80MHz 采样率具有梯度误差补偿的 CMOS 电流舵 D/A 转换器实现.半导体学报.2003,24(12):1324-1329.
[25] 李亚妮.功率转换器及其 Verilog-AMS 行为模型研究:[硕士学位论文],西安电子科技大学,西安:2005.
[26] 朱正涌.半导体集成电路.北京:清华大学出版社,2001.
[27] David A.Johns,Ken Martin.模拟集成电路设计.曾朝阳.北京:机械工业出版社,2005,317-344.
[28] A.Marques, J.Bastos, A.VandenBosch, J.Vandenbussche, M.Steyaert,and W.Sansen.A 12b Accuracy 300 MSample/s Update Rate CMOS DAC. IEEE ISSCC,1998:216.
[29] A . Van den Bosch, et al . A 12 bit 200MHz Low Glitch CMOS D/A Converter.IEEE CICC, 1998:249-252.
[30] A.Van den Bosch, M.A.F.Borremans et al. A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter.IEEE JSSC, 2001 (36):315-324.
[31] Albiol.M., Gonzalez.J.L., Alarcon.E.Improved current source sizing for high-speed high-accuracy current-steering d/a converter.Circuit and systems, 2003.ISCAS' 03 2003,1:837.
[32] Kosunen.M., Vankka.J., Teikari.F., etc.DNL and INL yield models fora current-steering d/a converter . Circuit and systems, 1003 . ISCAS' 03 2003.1:969.
[33] Yonghua cong, Geiger.R.L.Formulation of INL and DNL field estimation in current-steering d/a converter . ISCAS 2002 IEEE international symposium on. 2002, 3:1959.
[34] Sam Blackman . A Low Power, 8-bit, 200MHz Digital-to-Analog Converter. Electronics Research Laboratory, University of California, Berkeley, 1999.11.
[35] Chi-Hung Lin and Klaas Bult.A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2.Solid-State Circuits, IEEE Journal of, Volume:33, Issue:12, Dec.1998 Pages: 1948 -1958.
[36] A.Marques, J.Bastos, M.Steysert, W.Sansen.A Current Steering Architecture for 12-bit High-speed D/A Converter.Electronics, Circuits and Systems, 1998 IEEE International Conference on Sept.1998, Volume:1, 7-10, Pages:23-26.
[37] J.Jacob Wikner and Nianxiong Tan.Modeling of CMOS Digital-to-Analog Converters for Telecommunication.IEEE Trans.Circuits and Systems II. 1999, 46[5]:489-499.
[38] M.Gustavsson, J.J.Wikner, and N.Tan.CMOS Data Converters for Communications.Kluwer Academic Publishers, Boston, MA, USA, Jan.2000.
[39] R.J.van de Plassche.Integrated Analog to Digital and Digital to Analog Converters.Kluwer Academic Publishers, Boston, MA, USA, 1994.
[40] D.Groeneveld, et al.A self-calibration technique for monolithic high-resolution D/A converters[J].IEEE Journal of Solid-state Circuits, 1989, 24(12): 1517 - 1522.
[2] Sam Blackman.A low Power, 8-bit, 200MHz Digital-to-Analog Converter: [doctor degreepaper], University of California, California, Berkerly: 1999.
[3] 何艳红.8 位高速 D/A 转换器设计研究:[硕士学位论文],电子科技大学,成都:2004.
[4] Jose Bastos, Augusto M.Marques, Michel S.J.Steyaert, and Willy Sansen.A 12-bit intrinsic accuracy high-speed CMOS DAC.Solid-State Circuits, 1998, 33(12): 13-16.
[5] B.A.A.Antao and A.J.Brodersen, Behavioral Simulation for analog system design verification, IEEE Transactions on VLSI systems, September 1995, pp.1012-1021
[6] Ira Miller and Dan Fitz Patrick and Ramana Aisola, Analog Design with Verilog-AMS, 2100 E.Elliot Rd, Tempe, Arizona 85283.
[7] CADENCE, Verilog-AMS Reference Manual ,1997.
[8] The Designer’s Guide to Verilog-AMS, June 2004.
[9] 杨银堂,朱樟明,朱臻.高速 COMS 数据转换器.第一版.北京:科学出版社,2006:33-54.
[10] R.A.Saleh, B.A.A.Antao, and J.Sign, Multilevel and Mixed-Domain simulation of analog circuits and systems, IEEE Transactions on Computer-aided design of Ics and Systems. Vol.15, No.1, Jan.1996, pp.349-356.
[11] J.M.Fournier and P.Senn.A 100-MHz CMOS DAC for video-Graphic Systems.IEEE J.Solid-State Circuits,1989,vol. 24: 635~639.
[12] S.–Y.Chin and C.–Y.Wu.A 10-bit 125MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources.IEEE J. Solid-state Circuits,1994,vol.29:1374~1380.
[13] A.Abrial,J.Bouvier,J.-M.Fournier,P.Senn,and M. Veillard.A 27-MHz digital-to-analog video processor . IEEE J . Solid-State Circuits , 1998 ,vol.23:1358-1369.
[14] Mehrmanesh S, Vahidfa M B,A slanzade H A , et al.A 12Volt, high PSRR, CMOS bandgap voltage reference [A].IEEE International Symposium on Circuit and Systems[C].Bangkok, 2003: 3812384.
[15] Ka Nang Leung, Mok Philip K T.A sub212V 152ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device [J].IEEE J Solid-State Circuites, 2002; 37 (4) : 5262530.
[16] Buck Arne,McDonald Charles,Lew is Stephen, et al.A CMOS bandgap reference without resistors [J].IEEE J Solid-Stage Circuits, 2002; 37 (1) : 81283.
[17] Annema A J.Low power bandgap references featuring DTMOST s [J].IEEE J Solid-State Circuits, 1999; 34 (7) : 9492955.
[18] Banba Hironori, Shiga Hitoshi, Umezawa Akira, et al. A CMOS bandgap reference circuit with sub-1-V operation [J].IEEE J Solid-State Circuits, 1999; 34 (5) : 6702677.
[19] Nico llini Germano, Senderow icz Daniel.A CMOS bandgap reference for differential signal processing [J].IEEE J Solid-State Circuits, 1991; 26 (1) : 41250
[20] Oguey Henri J , A ebischer Daniel.CMOS current reference without resistance [J ].IEEE J Solid-State Circuits, 1997; 32 (7) : 1132-1135.
[21] Tao Shui, Schreier, R.Hudson, F.Mismatch shaping for a current-mode multibit delta-sigma DAC. Solid-State Circuits, IEEE Journal, 1999, 34(3): 331–338.
[22] 毕查德.拉扎维.模拟 CMOS 集成电路设计.陈贵灿,程军、张瑞智等译.第一版.西安:西安交通大学出版社,2003:319-320.
[23] 茹纪军.高速电流舵型 CMOS 数模转换器的研究与设计:[硕士学位论文],电子科技大学,成都: 2005.
[24] 江金光,何恰刚,吴杰.12 位 80MHz 采样率具有梯度误差补偿的 CMOS 电流舵 D/A 转换器实现.半导体学报.2003,24(12):1324-1329.
[25] 李亚妮.功率转换器及其 Verilog-AMS 行为模型研究:[硕士学位论文],西安电子科技大学,西安:2005.
[26] 朱正涌.半导体集成电路.北京:清华大学出版社,2001.
[27] David A.Johns,Ken Martin.模拟集成电路设计.曾朝阳.北京:机械工业出版社,2005,317-344.
[28] A.Marques, J.Bastos, A.VandenBosch, J.Vandenbussche, M.Steyaert,and W.Sansen.A 12b Accuracy 300 MSample/s Update Rate CMOS DAC. IEEE ISSCC,1998:216.
[29] A . Van den Bosch, et al . A 12 bit 200MHz Low Glitch CMOS D/A Converter.IEEE CICC, 1998:249-252.
[30] A.Van den Bosch, M.A.F.Borremans et al. A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter.IEEE JSSC, 2001 (36):315-324.
[31] Albiol.M., Gonzalez.J.L., Alarcon.E.Improved current source sizing for high-speed high-accuracy current-steering d/a converter.Circuit and systems, 2003.ISCAS' 03 2003,1:837.
[32] Kosunen.M., Vankka.J., Teikari.F., etc.DNL and INL yield models fora current-steering d/a converter . Circuit and systems, 1003 . ISCAS' 03 2003.1:969.
[33] Yonghua cong, Geiger.R.L.Formulation of INL and DNL field estimation in current-steering d/a converter . ISCAS 2002 IEEE international symposium on. 2002, 3:1959.
[34] Sam Blackman . A Low Power, 8-bit, 200MHz Digital-to-Analog Converter. Electronics Research Laboratory, University of California, Berkeley, 1999.11.
[35] Chi-Hung Lin and Klaas Bult.A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2.Solid-State Circuits, IEEE Journal of, Volume:33, Issue:12, Dec.1998 Pages: 1948 -1958.
[36] A.Marques, J.Bastos, M.Steysert, W.Sansen.A Current Steering Architecture for 12-bit High-speed D/A Converter.Electronics, Circuits and Systems, 1998 IEEE International Conference on Sept.1998, Volume:1, 7-10, Pages:23-26.
[37] J.Jacob Wikner and Nianxiong Tan.Modeling of CMOS Digital-to-Analog Converters for Telecommunication.IEEE Trans.Circuits and Systems II. 1999, 46[5]:489-499.
[38] M.Gustavsson, J.J.Wikner, and N.Tan.CMOS Data Converters for Communications.Kluwer Academic Publishers, Boston, MA, USA, Jan.2000.
[39] R.J.van de Plassche.Integrated Analog to Digital and Digital to Analog Converters.Kluwer Academic Publishers, Boston, MA, USA, 1994.
[40] D.Groeneveld, et al.A self-calibration technique for monolithic high-resolution D/A converters[J].IEEE Journal of Solid-state Circuits, 1989, 24(12): 1517 - 1522.