数字辅助流水线ADC关键单元设计
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摘要
随着电路系统数字化程度不断提高,模数转换器作为模拟信号与数字信号的接口电路,其作用也越来越重要。在诸多类型的模数转换器中,流水线模数转换器以其高速度和高精度而得到广泛应用。传统流水线模数转换器以模拟电路为主,其功耗、速度和精度之间存在严格的制约关系。而数字辅助流水线模数转换器采用简单的模拟电路代替复杂的数字电路,即在流水线的第一级采用简单的开环放大器,降低功耗,提高速度,在数字校正部分使用精确的校正算法校正开环放大器产生的非线性误差,改善精度,从而有效解决了传统流水线功耗、速度和精度之间严重的制约关系。
设计了12位40MS/s数字辅助流水线ADC的关键单元。首先分析系统整体结构,在考虑开环放大器非线性因素的基础上,建立系统的Verilog-A模型,验证校正方法的正确性。使用Cadence中的Spectre仿真软件,对没有数字校正的系统和带有数字校正的系统进行静态参数仿真,其INL从(-18LSB, 0.4LSB)降低到(-0.4LSB, 0.2LSB),DNL从(-0.5LSB, 0.4LSB)降低到(-0.2LSB, 0.2LSB)。并对带有数字校正的系统进行动态参数仿真,得到其SFDR达到86dB,SNDR达到72dB。另外,使用SMIC 0.35μm混合信号CMOS工艺,设计流水线第一级电路,按照建模的方法,在子ADC的最后一位加入伪随机信号,仿真结果表明在电路上实现了后台数字校正算法所要求的双余量曲线。
As an interface circuit of analog signal and digital signal, analog to digital converters get more and more important with the digitalize of the system. Pipeline ADC is applied broadly as its fast speed and high precision. However, a majority of the conventional pipeline ADCs are analog circuits, which have the restriction of power, speed and precision dramatically. To solve the problem and push up the advantages of digital circuits, simple analog circuits and complex digital arithmetic are used to transform the difficulty of ananlog circuit design to the complexity of the digital arithmetic. An open-loop amplifier is used in the first stage of the pipeline ADC to reduce the power and increase the speed. At the same time, accurate arithmetic is used in digital correction to correct the nonlinearity induced by the open-loop amplifier, which improves the precision. The method can relax the relationship between power, speed and precision effectively.
A 12-bit 40MS/s digitally assisted pipeline ADC is designed. First, Verilog-A is used to model the system to verify the digital correction with the nonlinearity of open-loop amplifier. Spectre in Cadence is used to simulate the system. Comparing the results of the system without and with digital correction, the INL falls from (-18LSB, 0.4LSB) to (-0.4LSB, 0.2LSB) and the DNL falls from (-0.5LSB, 0.4LSB) to (-0.2LSB, 0.2LSB). Simulating the system with digital correction dynamically, the SFDR is 86dB and the SNDR is 72dB. Moreover, SMIC 0.35μm mix signal CMOS technology is used to design the circuit of the first stage. In terms of the modle built forward, RNG is added to the last bit of the thermometer codes. The simulation shows that the two-residue plot fulfilling the digital correction can be realized in the form of schematic.
设计了12位40MS/s数字辅助流水线ADC的关键单元。首先分析系统整体结构,在考虑开环放大器非线性因素的基础上,建立系统的Verilog-A模型,验证校正方法的正确性。使用Cadence中的Spectre仿真软件,对没有数字校正的系统和带有数字校正的系统进行静态参数仿真,其INL从(-18LSB, 0.4LSB)降低到(-0.4LSB, 0.2LSB),DNL从(-0.5LSB, 0.4LSB)降低到(-0.2LSB, 0.2LSB)。并对带有数字校正的系统进行动态参数仿真,得到其SFDR达到86dB,SNDR达到72dB。另外,使用SMIC 0.35μm混合信号CMOS工艺,设计流水线第一级电路,按照建模的方法,在子ADC的最后一位加入伪随机信号,仿真结果表明在电路上实现了后台数字校正算法所要求的双余量曲线。
As an interface circuit of analog signal and digital signal, analog to digital converters get more and more important with the digitalize of the system. Pipeline ADC is applied broadly as its fast speed and high precision. However, a majority of the conventional pipeline ADCs are analog circuits, which have the restriction of power, speed and precision dramatically. To solve the problem and push up the advantages of digital circuits, simple analog circuits and complex digital arithmetic are used to transform the difficulty of ananlog circuit design to the complexity of the digital arithmetic. An open-loop amplifier is used in the first stage of the pipeline ADC to reduce the power and increase the speed. At the same time, accurate arithmetic is used in digital correction to correct the nonlinearity induced by the open-loop amplifier, which improves the precision. The method can relax the relationship between power, speed and precision effectively.
A 12-bit 40MS/s digitally assisted pipeline ADC is designed. First, Verilog-A is used to model the system to verify the digital correction with the nonlinearity of open-loop amplifier. Spectre in Cadence is used to simulate the system. Comparing the results of the system without and with digital correction, the INL falls from (-18LSB, 0.4LSB) to (-0.4LSB, 0.2LSB) and the DNL falls from (-0.5LSB, 0.4LSB) to (-0.2LSB, 0.2LSB). Simulating the system with digital correction dynamically, the SFDR is 86dB and the SNDR is 72dB. Moreover, SMIC 0.35μm mix signal CMOS technology is used to design the circuit of the first stage. In terms of the modle built forward, RNG is added to the last bit of the thermometer codes. The simulation shows that the two-residue plot fulfilling the digital correction can be realized in the form of schematic.
引文
1 B. Murmann, P. Nikaeen, D. J. Connelly, R. W. Dutton. Impact of Scaling on Analog Performance and Associated Modeling Needs. IEEE Transactions on Electron Devices. 2006,53(9):2160~2167
2欧阳文伟. ADC和DAC工作原理比较和发展现状.湖北教育学院报. 2005,22(2):67~69
3 D. Dallet, J. M. D. Silva. ADC的动态特性.科学出版社, 2007:3~5
4 B. Murmann. Digitally Assisted Analog Circuits. Micro. IEEE. 2006,26(2):38~47
5 R. H. Walden. Analog-to-Digital Converter Survey and Analysis. Journal on Selected Areas in Communications. 1999,17(4):539~550
6 B. Song, M. Tompsett, K. Lakshmikumar. A 12-bit 1-Msample/s Capacitor Error-averaging Pipelined A/D Converter. IEEE Journal of Solid-State Circuits. 1998,23:1324~1333
7 D. Y. Chang, J. P. Li, U. K. Moon. Radix-based Digital Calibration Techniques for Multi-stage Recycling Pipelined ADCs. IEEE Transactions on Circuits and Systems. 2004,51(11):2133~2140
8 Y. S. Shu, B. S. Song. A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated with Signal-dependent Dithering. IEEE Journal of Solid-State Circuits. 2008,43(2):342~350
9 Z. M. Lee, C. Y. Wang, J. T. Wu. A CMOS 15-bit 125-MS/s Time-interleaved ADC with Digital Background Calibration. IEEE Journal of Solid-State Circuits. 2007,42(10):2149~2160
10 D. Kelly, W. Yang, I. Mehr, M.Sayuk. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input. IEEE Journal of Solid-State Circuits. 2001,36(12):1931~1936
11 Y.-M. Lin, B. Kim, P. R. Gray. A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-μm CMOS. IEEE Journal of Solid-State Circuits. 1991,26(4):628~636
12 Y. Chiu, C. W. Tsang, B. Nikolic, P. R. Gray. Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-digital Converters. IEEE Trans. Circuits Syst. I, Reg. Papers. 2004,51:38~46
13 S. C. Grace, P. J. Hurst, S. H. Lewis. A 12b 80 MS/s Pipelined ADC with Bootstrapped Digital Calibration. Dig. Tech. Papers. Int. Solid-State Circuits Conf., 2004. San Francisco, CA, 2004:460~461
14 J. Sohbhi, Z. K. Kanani, A. Tahmasebi, M. Yousefi. A Simple Background Interstage Gain Calibration Technique for Pipeline ADCs. Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, 6th International Conference, 2009:508~511
15李淼,陈后鹏,戎蒙恬.一种数字与自校正流水线模数转换器改进结构.上海交通大学学报. 2004,38(5):738~746
16罗静芳,杨赟秀,吴霜毅,刘源,刘国庆.用于流水线模数转换冗余校正的溢出判断技术.微电子学. 2006,36(2):129~135
17贾华宇,陈贵灿,程军等.流水线模数转换器的一种数字校准技术.西安交通大学学报. 2008,42(8):991~995
18 R. Plassche. CMOS Integrated Analog-to-digital and Digital-to-analog Converters. Kluwer Academic Publishers, 2003:107~260
19荣雅君,余琼.数字电子技术.机械工业出版社, 1995:24~28
20阎鸿森,王新凤,田惠生.信号与现行系统.第2版.西安交通大学出版社, 2000:13~15
21 P. Sunghyun. Design Techniques for High Performance CMOS Flash Analog-to-Digital Converters. Degree of Doctoral in the University of Michigan United States. 2006:2~4
22李建.低功耗低电压CMOS流水线模数转换器的结构研究与实现.复旦大学博士学位论文. 2008:16~17
23 E. Culurciello, A. G. Andreou. An 8-bit 800uW 1.23-MS/s Successive Approximation ADC. SOI CMOS IEEE Transaction on Circuits and Systems-Ⅱ:Express Briefs. 2006,53(9):858~861
24丁晓燕. 16-bit 100Ksps Sigma-Delta模数转换器中数字滤波器的设计.西安电子科技大学硕士学位论文. 2009:5~11
25李晶.应用于Sigma-Delta ADC中可变抽取率数字滤波器的研究与设计.华中科技大学硕士学位论文. 2008:1~4
26杨银堂,朱樟明,朱臻.高速CMOS数据转换器.科学出版社, 2006:33~54
27韩泽耀,叶润涛.模拟/混合信号硬件描述语言VHDL-AMS综述.微电子学. 2001,31(2):83~84
28李亚妮.功率转换器及其Verilog-AMS行为模型研究.西安电子科技大学硕士学位论文. 2005:35~38
29 I. Miller, T. Casagnes. Verilog-A and Verilog-AMS Provides A New Dimension in Modeling and Simulation. 2000 Third IEEE International Caracas Conference,2000:1~6
30 M. Gustvsson, J. J. Wikner, N. N. Tan. CMOS Data Converters for Communications. Kluwer Academic, 2000:229~241
31 S. H. Lewis, P. R. Gray. A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter. IEEE Journal of Solid-State Circuits. 1987,22(6):954~961
32徐刚.流水线ADC的后台数字校正算法研究.电子科技大学硕士学位论文. 2008:55~57
33 L. A. Singer, T. L. Brooks. A 14-Bit 10MHz Calibration-Free CMOS Pipelined A/D Converter. Symposium on VLSI Circuits Digest of Technical Papers. 1996:94~95
34 P. J. Quinn, V. Roermund, H. M. Arthur. Design an Optimization of Multi-bit Front-end Stage and Scaled Back-end Stages of Pipelined ADCs. Circuits and Systems. 2005,3:1964~1967
35 G. Birkhoff, S. M. Lane. A Survey of Modern Algebra. 5th Edition. A. K Peters, 2007:101~103
36 B. Murmann, B. E. Boser. Digitally Assisted Pipeline ADCs: Theroy and Implementation. Kluwer Academic, 2004:79~90
37谢莉.高速全并行模数转换器的研究与设计.湖南大学硕士学位论文. 2009:17~18
38 A. G. W. Venes, B. Nauta, R. J. van de Plasssche. Low Power Folding A/D Converters In Analog Circuit Design. Kluwer Academic Publishers. 1996:105~124
39高雪莲.一种基于SAR ADC的低功耗动态比较器研究.北京交通大学硕士学位论文. 2007:36-40
40 H. Alzaher, M. Ismail. A CMOS fully Balanced Differential Difference Amplifier and its Applications. IEEE Trans. on Circuits and Systems:Ⅱ, Analog and Digital Signal Processing. 2001,48(6):614~620
41 K. Poulton, R. Neff, A. Muto, W. Liu, A. Burstein, M. Heshami. A 4 GS/s 8b ADC in 0.35μm CMOS. IEEE International Solid-State Circuits Conference, Dig. Tech. Papers. 2002:166~167
42 K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Permillo, C. Tan, A. Montijo. A 20GS/s 8b ADC with a 1MB Memory in 0.18μm CMOS. IEEE International Solid-State Circuits Conference, Dig. Tech. Papers. 2003:318~319
43 B. Murmann, B. E. Boser. A 12-bit 75-MS/s Pipelined ADC Using Open-loop Residue Amplification. IEEE Journal of Solid-State Circuits. 2003,38(12):2040~2050
44张鸿,陈贵灿,程军,贾华宇.流水线模数转换器中高速低功耗开环余量放大器的设计.西安交通大学学报. 2008,42(6):751~755
45罗敏. 12位100MSPS流水线ADC中的MDAC模块研究.电子科技大学硕士学位论文. 2008:53~55
46 D. W. Cline, P. R. Gray. A Power Optimized 13-b 5Msamples/s Pipelined Analog-to-Digital Converter in 1.2μm CMOS. IEEE Journal of Solid-State Circuits. 1996,31(3):294~303
47黄显洋.高速高精度流水线模数转换器设计研究.天津大学硕士学位论文. 2006:10~12
2欧阳文伟. ADC和DAC工作原理比较和发展现状.湖北教育学院报. 2005,22(2):67~69
3 D. Dallet, J. M. D. Silva. ADC的动态特性.科学出版社, 2007:3~5
4 B. Murmann. Digitally Assisted Analog Circuits. Micro. IEEE. 2006,26(2):38~47
5 R. H. Walden. Analog-to-Digital Converter Survey and Analysis. Journal on Selected Areas in Communications. 1999,17(4):539~550
6 B. Song, M. Tompsett, K. Lakshmikumar. A 12-bit 1-Msample/s Capacitor Error-averaging Pipelined A/D Converter. IEEE Journal of Solid-State Circuits. 1998,23:1324~1333
7 D. Y. Chang, J. P. Li, U. K. Moon. Radix-based Digital Calibration Techniques for Multi-stage Recycling Pipelined ADCs. IEEE Transactions on Circuits and Systems. 2004,51(11):2133~2140
8 Y. S. Shu, B. S. Song. A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated with Signal-dependent Dithering. IEEE Journal of Solid-State Circuits. 2008,43(2):342~350
9 Z. M. Lee, C. Y. Wang, J. T. Wu. A CMOS 15-bit 125-MS/s Time-interleaved ADC with Digital Background Calibration. IEEE Journal of Solid-State Circuits. 2007,42(10):2149~2160
10 D. Kelly, W. Yang, I. Mehr, M.Sayuk. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input. IEEE Journal of Solid-State Circuits. 2001,36(12):1931~1936
11 Y.-M. Lin, B. Kim, P. R. Gray. A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-μm CMOS. IEEE Journal of Solid-State Circuits. 1991,26(4):628~636
12 Y. Chiu, C. W. Tsang, B. Nikolic, P. R. Gray. Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-digital Converters. IEEE Trans. Circuits Syst. I, Reg. Papers. 2004,51:38~46
13 S. C. Grace, P. J. Hurst, S. H. Lewis. A 12b 80 MS/s Pipelined ADC with Bootstrapped Digital Calibration. Dig. Tech. Papers. Int. Solid-State Circuits Conf., 2004. San Francisco, CA, 2004:460~461
14 J. Sohbhi, Z. K. Kanani, A. Tahmasebi, M. Yousefi. A Simple Background Interstage Gain Calibration Technique for Pipeline ADCs. Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, 6th International Conference, 2009:508~511
15李淼,陈后鹏,戎蒙恬.一种数字与自校正流水线模数转换器改进结构.上海交通大学学报. 2004,38(5):738~746
16罗静芳,杨赟秀,吴霜毅,刘源,刘国庆.用于流水线模数转换冗余校正的溢出判断技术.微电子学. 2006,36(2):129~135
17贾华宇,陈贵灿,程军等.流水线模数转换器的一种数字校准技术.西安交通大学学报. 2008,42(8):991~995
18 R. Plassche. CMOS Integrated Analog-to-digital and Digital-to-analog Converters. Kluwer Academic Publishers, 2003:107~260
19荣雅君,余琼.数字电子技术.机械工业出版社, 1995:24~28
20阎鸿森,王新凤,田惠生.信号与现行系统.第2版.西安交通大学出版社, 2000:13~15
21 P. Sunghyun. Design Techniques for High Performance CMOS Flash Analog-to-Digital Converters. Degree of Doctoral in the University of Michigan United States. 2006:2~4
22李建.低功耗低电压CMOS流水线模数转换器的结构研究与实现.复旦大学博士学位论文. 2008:16~17
23 E. Culurciello, A. G. Andreou. An 8-bit 800uW 1.23-MS/s Successive Approximation ADC. SOI CMOS IEEE Transaction on Circuits and Systems-Ⅱ:Express Briefs. 2006,53(9):858~861
24丁晓燕. 16-bit 100Ksps Sigma-Delta模数转换器中数字滤波器的设计.西安电子科技大学硕士学位论文. 2009:5~11
25李晶.应用于Sigma-Delta ADC中可变抽取率数字滤波器的研究与设计.华中科技大学硕士学位论文. 2008:1~4
26杨银堂,朱樟明,朱臻.高速CMOS数据转换器.科学出版社, 2006:33~54
27韩泽耀,叶润涛.模拟/混合信号硬件描述语言VHDL-AMS综述.微电子学. 2001,31(2):83~84
28李亚妮.功率转换器及其Verilog-AMS行为模型研究.西安电子科技大学硕士学位论文. 2005:35~38
29 I. Miller, T. Casagnes. Verilog-A and Verilog-AMS Provides A New Dimension in Modeling and Simulation. 2000 Third IEEE International Caracas Conference,2000:1~6
30 M. Gustvsson, J. J. Wikner, N. N. Tan. CMOS Data Converters for Communications. Kluwer Academic, 2000:229~241
31 S. H. Lewis, P. R. Gray. A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter. IEEE Journal of Solid-State Circuits. 1987,22(6):954~961
32徐刚.流水线ADC的后台数字校正算法研究.电子科技大学硕士学位论文. 2008:55~57
33 L. A. Singer, T. L. Brooks. A 14-Bit 10MHz Calibration-Free CMOS Pipelined A/D Converter. Symposium on VLSI Circuits Digest of Technical Papers. 1996:94~95
34 P. J. Quinn, V. Roermund, H. M. Arthur. Design an Optimization of Multi-bit Front-end Stage and Scaled Back-end Stages of Pipelined ADCs. Circuits and Systems. 2005,3:1964~1967
35 G. Birkhoff, S. M. Lane. A Survey of Modern Algebra. 5th Edition. A. K Peters, 2007:101~103
36 B. Murmann, B. E. Boser. Digitally Assisted Pipeline ADCs: Theroy and Implementation. Kluwer Academic, 2004:79~90
37谢莉.高速全并行模数转换器的研究与设计.湖南大学硕士学位论文. 2009:17~18
38 A. G. W. Venes, B. Nauta, R. J. van de Plasssche. Low Power Folding A/D Converters In Analog Circuit Design. Kluwer Academic Publishers. 1996:105~124
39高雪莲.一种基于SAR ADC的低功耗动态比较器研究.北京交通大学硕士学位论文. 2007:36-40
40 H. Alzaher, M. Ismail. A CMOS fully Balanced Differential Difference Amplifier and its Applications. IEEE Trans. on Circuits and Systems:Ⅱ, Analog and Digital Signal Processing. 2001,48(6):614~620
41 K. Poulton, R. Neff, A. Muto, W. Liu, A. Burstein, M. Heshami. A 4 GS/s 8b ADC in 0.35μm CMOS. IEEE International Solid-State Circuits Conference, Dig. Tech. Papers. 2002:166~167
42 K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Permillo, C. Tan, A. Montijo. A 20GS/s 8b ADC with a 1MB Memory in 0.18μm CMOS. IEEE International Solid-State Circuits Conference, Dig. Tech. Papers. 2003:318~319
43 B. Murmann, B. E. Boser. A 12-bit 75-MS/s Pipelined ADC Using Open-loop Residue Amplification. IEEE Journal of Solid-State Circuits. 2003,38(12):2040~2050
44张鸿,陈贵灿,程军,贾华宇.流水线模数转换器中高速低功耗开环余量放大器的设计.西安交通大学学报. 2008,42(6):751~755
45罗敏. 12位100MSPS流水线ADC中的MDAC模块研究.电子科技大学硕士学位论文. 2008:53~55
46 D. W. Cline, P. R. Gray. A Power Optimized 13-b 5Msamples/s Pipelined Analog-to-Digital Converter in 1.2μm CMOS. IEEE Journal of Solid-State Circuits. 1996,31(3):294~303
47黄显洋.高速高精度流水线模数转换器设计研究.天津大学硕士学位论文. 2006:10~12