一种用于MCU的低功耗电源系统设计
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摘要
电源管理是电子系统不可或缺的一部分,随着工艺尺寸的不断缩小,片上系统的迅速发展,它也在朝着高集成化的方向发展。将电源管理电路与需要供电的模块集成在同一块芯片上不仅可以减小芯片面积和引脚数,降低系统成本,还可以降低模块间的串扰和寄生损耗,提高系统性能。
本文对不同电源电路的优缺点进行了比较,并提出了适合于MCU应用的电源系统方案。本文设计的电源系统由两部分构成,分别为待机模式电源电路和正常工作模式电源电路。前者是一个带有输出缓冲级的超低功耗准电压基准源,主要用于保证待机模式下芯片中部分存储器和低频振荡器的正常工作；后者是一个低压差线性稳压器,主要用于保证正常工作模式下芯片中MCU、各种存储器、高频振荡器及I/0口的正常工作。芯片在正常工作模式时,低压差线性稳压器被唤起,为芯片提供内部电源电压；芯片在待机模式时,低压差线性稳压器停止工作,由准电压基准源电路为芯片提供内部电源电压；这样可以达到降低芯片平均功耗的目的。
基于HEJIAN 0.25μm CMOS工艺对电路进行设计与仿真,待机模式电源电路的静态电流为240nA,最大输出电流为100μA,输出电压为2.1V,精度为±0.15V,最大温度系数为110ppm/℃,电路的线性调整率和负载调整率分别为13mV/V和2.2mV/μA,低频时电源抑制比为-44dB。正常工作模式电源电路的静态电流为135μA,最大输出电流为20mA,输出电压为2.4V,精度为±0.1V,最大温度系数为36ppm/℃,电路的线性调整率和负载调整率分别为8.3mV/V和-0.24mV/mA,低频时电源抑制比为-56dB,1MHz时电源抑制比为-34dB。
Power management is an essential part of the electronic system and is moving in the direction of high integration with the continuously shrinking of the feature size and the rapid development of system-on-chip (SoC). Integrating the power management circuitry and the blocks needing regulated supply voltage on a single chip can not only reduce the chip area and pins and lower the cost of system, but also reduce the crosstalk between them and improve the performance of the system.
In this thesis, the advantages and drawbacks of different power circuits are compared and the scheme of power system suitable for MCU application is proposed. Power system designed here consists of two parts, namely, standby mode power circuitry and active mode power circuitry respectively. The former is an ultra-low power quasi-voltage-reference with an output buffer stage, mainly used to guarantee part of memories and the low-frequency oscillator of the chip to work normally in standby mode; the latter is a low dropout regulator (LDO), primarily used to ensure MCU, kinds of memories, high-frequency oscillator and I/O ports to work normally in active mode. When the chip is in active mode, LDO is aroused to provide the internal supply voltage for the chip; when the chip is in standby mode, LDO stops working and the quasi-voltage-reference provides the internal supply voltage for the chip; this can lead to lower average power consumption of the chip.
Based on HEJIAN 0.25μm CMOS technology, the two circuits have been designed and simulated. The quiescent current, the maximum output current, output voltage, accuracy and the maximum temperature coefficient of the power circuitry used for the standby mode is 240nA, 100μA,2.1V,±0.15V and 110ppm/℃respectively. Its line regulation and load regulation are 13mV/V and 2.2mV/μA, and its power supply rejection ration (PSRR) is -44dB at low frequency. The quiescent current, the maximum output current, output voltage, accuracy and the maximum temperature coefficient of the power circuitry used for the active mode is 135μA, 20mA,2.4V,±0.1V and 36ppm/℃respectively. Its line regulation and load regulation are 8.3mV/V and -0.24mV/mA, and its PSRR is -56dB at low frequency and -34dB at 1MHz.
本文对不同电源电路的优缺点进行了比较,并提出了适合于MCU应用的电源系统方案。本文设计的电源系统由两部分构成,分别为待机模式电源电路和正常工作模式电源电路。前者是一个带有输出缓冲级的超低功耗准电压基准源,主要用于保证待机模式下芯片中部分存储器和低频振荡器的正常工作；后者是一个低压差线性稳压器,主要用于保证正常工作模式下芯片中MCU、各种存储器、高频振荡器及I/0口的正常工作。芯片在正常工作模式时,低压差线性稳压器被唤起,为芯片提供内部电源电压；芯片在待机模式时,低压差线性稳压器停止工作,由准电压基准源电路为芯片提供内部电源电压；这样可以达到降低芯片平均功耗的目的。
基于HEJIAN 0.25μm CMOS工艺对电路进行设计与仿真,待机模式电源电路的静态电流为240nA,最大输出电流为100μA,输出电压为2.1V,精度为±0.15V,最大温度系数为110ppm/℃,电路的线性调整率和负载调整率分别为13mV/V和2.2mV/μA,低频时电源抑制比为-44dB。正常工作模式电源电路的静态电流为135μA,最大输出电流为20mA,输出电压为2.4V,精度为±0.1V,最大温度系数为36ppm/℃,电路的线性调整率和负载调整率分别为8.3mV/V和-0.24mV/mA,低频时电源抑制比为-56dB,1MHz时电源抑制比为-34dB。
Power management is an essential part of the electronic system and is moving in the direction of high integration with the continuously shrinking of the feature size and the rapid development of system-on-chip (SoC). Integrating the power management circuitry and the blocks needing regulated supply voltage on a single chip can not only reduce the chip area and pins and lower the cost of system, but also reduce the crosstalk between them and improve the performance of the system.
In this thesis, the advantages and drawbacks of different power circuits are compared and the scheme of power system suitable for MCU application is proposed. Power system designed here consists of two parts, namely, standby mode power circuitry and active mode power circuitry respectively. The former is an ultra-low power quasi-voltage-reference with an output buffer stage, mainly used to guarantee part of memories and the low-frequency oscillator of the chip to work normally in standby mode; the latter is a low dropout regulator (LDO), primarily used to ensure MCU, kinds of memories, high-frequency oscillator and I/O ports to work normally in active mode. When the chip is in active mode, LDO is aroused to provide the internal supply voltage for the chip; when the chip is in standby mode, LDO stops working and the quasi-voltage-reference provides the internal supply voltage for the chip; this can lead to lower average power consumption of the chip.
Based on HEJIAN 0.25μm CMOS technology, the two circuits have been designed and simulated. The quiescent current, the maximum output current, output voltage, accuracy and the maximum temperature coefficient of the power circuitry used for the standby mode is 240nA, 100μA,2.1V,±0.15V and 110ppm/℃respectively. Its line regulation and load regulation are 13mV/V and 2.2mV/μA, and its power supply rejection ration (PSRR) is -44dB at low frequency. The quiescent current, the maximum output current, output voltage, accuracy and the maximum temperature coefficient of the power circuitry used for the active mode is 135μA, 20mA,2.4V,±0.1V and 36ppm/℃respectively. Its line regulation and load regulation are 8.3mV/V and -0.24mV/mA, and its PSRR is -56dB at low frequency and -34dB at 1MHz.
引文
[1]Moore G. E. Cramming more components onto integrated circuits[J]. Electronics,1965,38(8):114.
[2]Intel生成工艺规划：32nm半年后过半[EB/OL].:哈维硬件网,2010-12-27.
[3]Willy M. C. Sansen. Analog Design Essentials[M]. Netherlands: Springer,2006.
[4]何小庆.金融危机下的MCU发展趋势[EB/OL].:http://wenku.baidu.com/ view/97a686d376eeaeaadlf3305e.html,2009-3-28.
[5]柴远波,张兴明.现代SoC设计技术[M].北京：电子工业出版社,2009：1-22.
[6]何允灵,秦娟,王佳,倪明,柴小丽.SoC处理器的电源管理系统设计[J].计算机工程,2008,34(16)：262-264.
[7]Yu-Huei, Ke-Horng Chen. A 65nm Sub-1V Multi-Stage Low-Dropout(LDO) Regulator Design for SoC Systems[R]. IEEE International Midwest Symposium on Circuits and Systems,2010:584-587.
[8]Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, and Chih-Kong Ken Yang. Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies[J]. IEEE Transaction on VLSI Systems,2007, 15(9):1017-1027.
[9]Dennis D. Buss. Technology in the Internet Age[C]. ISSCC Digest of Technical Papers,2002:18-21.
[10]Nathan Andrews. The Global Market for Power Supply and Power Management Integrated Circuits[C]. Applied Power Electronics Conference and Exposition,2002:126-131.
[11]关注MCU发展的新动向[EB/OL].: http://www.cepark.com/Article/DSP/84251.html,2009-01-08.
[12]Kae Wong and David Evans. A 150mA Low Noise, High PSRR Low-Dropout Linear Regulator in 0.13μm Technology for RF SoC Applications[C]. IEEE Proceedings of 32nd European Solid-State Circuits Conference, 2006:532-535.
[13]Chaitanya K. Chava, Jose Silva-Martinez. A Frequency Compensation for LDO Voltage Regulators[J]. IEEE Transactions on Circuits and Systems,2004,51(6):1041-1050.
[14]Abraham I. Pressman. Switching Power Supply Design (Second Edition)[M].王志强等译.北京：电子工业出版社,2005：1-24.
[15]Markus Hammes, Christian Kranz, Dietolf Seippel, Jens Kissing, Andeas Leyk. Evolution on SoC Integration:GSM Baseband-Radio in 0.13μm CMOS Extended by Fully Integrated Power Management Unit[J]. IEEE Journal of Solid-State Circuits,2008,43(1):236-244.
[16]Gabriel Alfonso Rincno-Mora. Current Efficient, Low Voltage, Low Drop-out Regulators[D]. Atlanta Botanical:Georgia Institute of Technology,1996.
[17]Widlar R. J. New developments in IC voltage regulators [J]. IEEE Journal of Solid-State Circuits,1971,6(1):2-7.
[18]Filanovsky I.M., Allam A. Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits[J]. IEEE Transactions on Circuits and Systems,2001, 48(7):876-884.
[19]Cheng Y, Hu C. MOSFET Modeling & BSIM3 User's Guide[M]. Kluwer Academic Publishers,1999:124-125.
[20]余国义.低压低功耗CMOS基准参考源的设计[D].武汉：华中科技大学,2006.
[21]刘恩科,朱秉升,罗晋生等.半导体物理学[M].北京：国防工业出版社,2007：178-226.
[22]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya. A 300nW, 15ppm/℃,20ppm/V CMOS Voltage Reference Circuit Consisting of Sub-threshold MOSFETs[J]. IEEE Journal of Solid-State Circuits,2009, 44(7):2047-2053.
[23]de Carvalho Ferreira L. H., Cleber Pimenta T. A CMOS Voltage Reference Based on Threshold Voltage for Ultra Low-Voltage and Ultra Low-Power[C]. IEEE The 17th International Conference on Microelectronics,2005:10-12.
[24]Giustolisi G., Palumbo G.,Criscione M.,Cutri F. A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs[J]. IEEE Journal of Solid-State Circuits,2003,38(1):151-154.
[25]Po-Hsuan Huang, Hongchin Lin, Yen-Tai Lin. A Simple Subthreshold CMOS Voltage Reference Circuit With Channel-Length Modulation Compensation[J]. IEEE Transactions on Circuits and Systems,2006, 53(9):882-885.
[26]Tom Kugelstadt. Fundamental Theory of PMOS Low-Dropout Voltage Regulators[R]. Dallas:Texas Instruments Incorporated,1999.
[27]毕查德·拉扎维.模拟CMOS集成电路设计[M].陈贵灿、程军、张瑞智等译.西安：西安交通大学出版社,2002.
[28]Bang S. Lee. Technical Review of Low Dropout Voltage Regulator Operation and Performance[R]. Dallas:Texas Instruments Incorporated,1999.
[29]Xiaohua Fan, Chinmaya Mishra, Edgar Sanchez-Sinencio. Single Miller Capacitor Frequency Compensation Technique for Low-Power Multistage Amplifiers[J]. IEEE Journal of Solid-State Circuits,2005,40(3): 584-592.
[30]R. G. H. Eschauzier, L. P. T. Kerklaan, J. H. Huijsing. A 100-MHz 100-dB Operational Amplifier With Multipath Nested Miller Compensation Structure[J]. IEEE Journal of Solid-State Circuits,1992,27(12): 1709-1717.
[31]Ka Nang Leung,Philip K.T. Mok. A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation[J]. IEEE Journal of Solid-State Circuits,2003,38(10):1691-1701.
[32]Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sanchez-Sinencio. High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique[J]. IEEE Journal of Solid-State Circuits,2010,45(3):565-576.
[33]Ka Nang Leung, Philip K. T. Mok. A Sub-1-V 15-ppm/℃ CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Devi-ce[J]. IEEE Journal of Solid-State Circuits,2002,37(4):526-530.
[34]H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui. A CMOS Bandgap Reference Circuit with Sub-1-V Operation[J]. IEEE Journal of Solid-State Circuits,1999,34(5):670-674.
[35]Keith Sanborn, Dongsheng Ma, Vadim Ivanov. A Sub-1-V Low-Noise Bandgap Voltage Reference[J]. IEEE Journal of Solid-State Circuits,2007, 42(11):2466-2481.
[36]Annema A.-J. Low-Power Bandgap References Featuring DTMOST's[J]. IEEE Journal of Solid-State Circuits,1999,34(7):949-955.
[37]M. Gunawan et al. A Curvature-Corrected Low-Voltage Bandgap Reference[J]. IEEE Journal of Solid-State Circuits,1993,28(6): 667-670.
[38]G. A. Rincon-Mora. Voltage Reference-From Diodes to Precision High-Order Bandgap Circuits[M]. New York:Wiley,2002.
[39]Khong-Meng Tham, Krishnaswamy Nagaraj. A Low Supply Voltage High PSRR Voltage Reference in CMOS Process[J]. IEEE Journal of Solid-State Circuits,1995,30(5):586-590.
[40]Giuseppe De Vita, Giuseppe Iannaccone. An Ultra-Low-Power, Temperature Compensated Voltage Reference Generator[C]. IEEE Custom Integrated Circuits Conference,2005:751-754.
[41]Peter R. Kinget. Device Mismatch and Tradeoffs in the Design of Analog Circuits[J]. IEEE Journal of Solid-State Circuits,1998,33(1): 36-44.
[42]Tsz Yin Man, Philip K. T. Mok, Mansun Chan. Design of Area-Efficient, Low-Quiescent-Current LDOs for Chip-Level Power Management[C]. International Symposium on Integrated Circuits,2007:61-64.
[43]Gabriel A. Rincon-Mora, Phillip E. Allen. A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator[J]. IEEE Journal of Solid-State Circuits,1998,33(1):36-44.
[44]Mohammad Al-Shyoukh, Hoi Lee, Raul Perez. A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation[J]. IEEE Journal of Solid-State Circuits,2007,42(8): 1732-1741.
[45]Sai Kit Lau, Philip K. T. Mok, Ka Nang Leung. A Low-Dropout Regulator for SoCWith Q-Reduction[J]. IEEE Journal of Solid-State Circuits, 2007,42(3):658-664.
[46]Pui Ying, Ka Nang Leung. An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection[J]. IEEE Journal of Solid-State Circuits,2010,45(2):458-466.
[47]Jianping Guo, Ka Nang Leung. A Sub-1μ A Improved-Transient CMOS Low-Dropout Regulator without Minimal ESR Requirement[C]. IEEE Region 10 Conference,2009:1-6.
[2]Intel生成工艺规划：32nm半年后过半[EB/OL].:哈维硬件网,2010-12-27.
[3]Willy M. C. Sansen. Analog Design Essentials[M]. Netherlands: Springer,2006.
[4]何小庆.金融危机下的MCU发展趋势[EB/OL].:http://wenku.baidu.com/ view/97a686d376eeaeaadlf3305e.html,2009-3-28.
[5]柴远波,张兴明.现代SoC设计技术[M].北京：电子工业出版社,2009：1-22.
[6]何允灵,秦娟,王佳,倪明,柴小丽.SoC处理器的电源管理系统设计[J].计算机工程,2008,34(16)：262-264.
[7]Yu-Huei, Ke-Horng Chen. A 65nm Sub-1V Multi-Stage Low-Dropout(LDO) Regulator Design for SoC Systems[R]. IEEE International Midwest Symposium on Circuits and Systems,2010:584-587.
[8]Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, and Chih-Kong Ken Yang. Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies[J]. IEEE Transaction on VLSI Systems,2007, 15(9):1017-1027.
[9]Dennis D. Buss. Technology in the Internet Age[C]. ISSCC Digest of Technical Papers,2002:18-21.
[10]Nathan Andrews. The Global Market for Power Supply and Power Management Integrated Circuits[C]. Applied Power Electronics Conference and Exposition,2002:126-131.
[11]关注MCU发展的新动向[EB/OL].: http://www.cepark.com/Article/DSP/84251.html,2009-01-08.
[12]Kae Wong and David Evans. A 150mA Low Noise, High PSRR Low-Dropout Linear Regulator in 0.13μm Technology for RF SoC Applications[C]. IEEE Proceedings of 32nd European Solid-State Circuits Conference, 2006:532-535.
[13]Chaitanya K. Chava, Jose Silva-Martinez. A Frequency Compensation for LDO Voltage Regulators[J]. IEEE Transactions on Circuits and Systems,2004,51(6):1041-1050.
[14]Abraham I. Pressman. Switching Power Supply Design (Second Edition)[M].王志强等译.北京：电子工业出版社,2005：1-24.
[15]Markus Hammes, Christian Kranz, Dietolf Seippel, Jens Kissing, Andeas Leyk. Evolution on SoC Integration:GSM Baseband-Radio in 0.13μm CMOS Extended by Fully Integrated Power Management Unit[J]. IEEE Journal of Solid-State Circuits,2008,43(1):236-244.
[16]Gabriel Alfonso Rincno-Mora. Current Efficient, Low Voltage, Low Drop-out Regulators[D]. Atlanta Botanical:Georgia Institute of Technology,1996.
[17]Widlar R. J. New developments in IC voltage regulators [J]. IEEE Journal of Solid-State Circuits,1971,6(1):2-7.
[18]Filanovsky I.M., Allam A. Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits[J]. IEEE Transactions on Circuits and Systems,2001, 48(7):876-884.
[19]Cheng Y, Hu C. MOSFET Modeling & BSIM3 User's Guide[M]. Kluwer Academic Publishers,1999:124-125.
[20]余国义.低压低功耗CMOS基准参考源的设计[D].武汉：华中科技大学,2006.
[21]刘恩科,朱秉升,罗晋生等.半导体物理学[M].北京：国防工业出版社,2007：178-226.
[22]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya. A 300nW, 15ppm/℃,20ppm/V CMOS Voltage Reference Circuit Consisting of Sub-threshold MOSFETs[J]. IEEE Journal of Solid-State Circuits,2009, 44(7):2047-2053.
[23]de Carvalho Ferreira L. H., Cleber Pimenta T. A CMOS Voltage Reference Based on Threshold Voltage for Ultra Low-Voltage and Ultra Low-Power[C]. IEEE The 17th International Conference on Microelectronics,2005:10-12.
[24]Giustolisi G., Palumbo G.,Criscione M.,Cutri F. A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs[J]. IEEE Journal of Solid-State Circuits,2003,38(1):151-154.
[25]Po-Hsuan Huang, Hongchin Lin, Yen-Tai Lin. A Simple Subthreshold CMOS Voltage Reference Circuit With Channel-Length Modulation Compensation[J]. IEEE Transactions on Circuits and Systems,2006, 53(9):882-885.
[26]Tom Kugelstadt. Fundamental Theory of PMOS Low-Dropout Voltage Regulators[R]. Dallas:Texas Instruments Incorporated,1999.
[27]毕查德·拉扎维.模拟CMOS集成电路设计[M].陈贵灿、程军、张瑞智等译.西安：西安交通大学出版社,2002.
[28]Bang S. Lee. Technical Review of Low Dropout Voltage Regulator Operation and Performance[R]. Dallas:Texas Instruments Incorporated,1999.
[29]Xiaohua Fan, Chinmaya Mishra, Edgar Sanchez-Sinencio. Single Miller Capacitor Frequency Compensation Technique for Low-Power Multistage Amplifiers[J]. IEEE Journal of Solid-State Circuits,2005,40(3): 584-592.
[30]R. G. H. Eschauzier, L. P. T. Kerklaan, J. H. Huijsing. A 100-MHz 100-dB Operational Amplifier With Multipath Nested Miller Compensation Structure[J]. IEEE Journal of Solid-State Circuits,1992,27(12): 1709-1717.
[31]Ka Nang Leung,Philip K.T. Mok. A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation[J]. IEEE Journal of Solid-State Circuits,2003,38(10):1691-1701.
[32]Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sanchez-Sinencio. High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique[J]. IEEE Journal of Solid-State Circuits,2010,45(3):565-576.
[33]Ka Nang Leung, Philip K. T. Mok. A Sub-1-V 15-ppm/℃ CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Devi-ce[J]. IEEE Journal of Solid-State Circuits,2002,37(4):526-530.
[34]H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui. A CMOS Bandgap Reference Circuit with Sub-1-V Operation[J]. IEEE Journal of Solid-State Circuits,1999,34(5):670-674.
[35]Keith Sanborn, Dongsheng Ma, Vadim Ivanov. A Sub-1-V Low-Noise Bandgap Voltage Reference[J]. IEEE Journal of Solid-State Circuits,2007, 42(11):2466-2481.
[36]Annema A.-J. Low-Power Bandgap References Featuring DTMOST's[J]. IEEE Journal of Solid-State Circuits,1999,34(7):949-955.
[37]M. Gunawan et al. A Curvature-Corrected Low-Voltage Bandgap Reference[J]. IEEE Journal of Solid-State Circuits,1993,28(6): 667-670.
[38]G. A. Rincon-Mora. Voltage Reference-From Diodes to Precision High-Order Bandgap Circuits[M]. New York:Wiley,2002.
[39]Khong-Meng Tham, Krishnaswamy Nagaraj. A Low Supply Voltage High PSRR Voltage Reference in CMOS Process[J]. IEEE Journal of Solid-State Circuits,1995,30(5):586-590.
[40]Giuseppe De Vita, Giuseppe Iannaccone. An Ultra-Low-Power, Temperature Compensated Voltage Reference Generator[C]. IEEE Custom Integrated Circuits Conference,2005:751-754.
[41]Peter R. Kinget. Device Mismatch and Tradeoffs in the Design of Analog Circuits[J]. IEEE Journal of Solid-State Circuits,1998,33(1): 36-44.
[42]Tsz Yin Man, Philip K. T. Mok, Mansun Chan. Design of Area-Efficient, Low-Quiescent-Current LDOs for Chip-Level Power Management[C]. International Symposium on Integrated Circuits,2007:61-64.
[43]Gabriel A. Rincon-Mora, Phillip E. Allen. A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator[J]. IEEE Journal of Solid-State Circuits,1998,33(1):36-44.
[44]Mohammad Al-Shyoukh, Hoi Lee, Raul Perez. A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation[J]. IEEE Journal of Solid-State Circuits,2007,42(8): 1732-1741.
[45]Sai Kit Lau, Philip K. T. Mok, Ka Nang Leung. A Low-Dropout Regulator for SoCWith Q-Reduction[J]. IEEE Journal of Solid-State Circuits, 2007,42(3):658-664.
[46]Pui Ying, Ka Nang Leung. An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection[J]. IEEE Journal of Solid-State Circuits,2010,45(2):458-466.
[47]Jianping Guo, Ka Nang Leung. A Sub-1μ A Improved-Transient CMOS Low-Dropout Regulator without Minimal ESR Requirement[C]. IEEE Region 10 Conference,2009:1-6.