可编程快速锁定电荷泵型锁相环的设计与实现
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摘要
随着集成电路的发展,锁相环技术经历了由最初的模拟锁相环到数模混合的锁相环,再到后来的全数字锁相环的历程,发展十分迅速。尽管如此,作为数模混合锁相环典型代表的电荷泵锁相环,仍以其在理论上具有无限频率牵引范围的优点在超大规模集成电路中得到广泛的应用。本文在深入分析电荷泵锁相环基本理论以及捕捉与锁定理论的基础上,设计了一款可编程快速锁定电荷泵型锁相环,该锁相环电路稳定工作时的频率输出范围在20MHz到200MHz之间。
在本文所涉及的锁相环设计过程中,针对数模混合电路的特点,综合考虑了稳定性、锁定速度、功耗等方面的因素,设计的锁相环电路满足锁定速度快、抗噪声力强的要求。设计的可编程电荷泵,提高了锁相环路的频率锁定速度,同时采用将电荷泵开关设置在电流源MOS管源端的电荷泵结构,避免了因过冲电流引起锁相环路的非线性;设计的新型基准电压产生电路,大幅度提高了电路抗电源地噪声的能力;设计的可控环形压控振荡器,具有很好的线性度,性能稳定,并具有关断功能,能够在锁相环不工作时关闭压控振荡器,以降低功耗;为满足锁相环输出不同频率的需要,设计了一款可编程的分频器,实现对锁相环输出频率的可编程控制。
本文基于0.15μm CMOS工艺,设计实现了可编程快速锁定电荷泵型锁相环的电路和版图,并且分别在电路层和版图的层次进行了多个Corner条件下的验证工作,验证结果表明,该锁相环达到了设计指标。该锁相环已经流片。测试结果表明,该锁相环输出频率可以在20MHz到200MHz之间实现可编程控制。
With the development of the integrated circuit, phase-locked loop technology has experienced by the initial number of analog phase-locked loop, mixed-signal phase-locked loop and then all digital phase-locked loop, and developed rapidly. In spite of this, charge-pump phase-locked loop, as the typical representation of mixed-signal phase-locked loop, is still applied in very large scale integrated circuit extensively, since its irreplaceable advantages. In this paper, a programmable fast-locking charge-pump phase-locked loop is designed based on in-depth analyzing the basic theory of charge-pump phase-locked loop and the theory of capture and locking. It can work stability with the output frequency range from 20MHz to 200MHz.
In the light of the characteristic of mixed-signal circuits, phase-locked loop in this paper is comprehensively considered with the tradeoff between such requirements as stability, locking speed and power consumption in the process of design. The circuit designed can meet the needs of fast-locking and high noise resisting ability in the specification. A programmable charge-pump is designed to advance the frequency locking speed of phase-locked loop. In the meaning time, the structure of setting the switch on source side of the current mirror’s MOS transistor in charge-pump is selected to avoid the nonlinearity of phase-locked loop circuit caused by overshoot current. A new circuit to generate voltage reference is designed to greatly advance the ability of resisting noise of power and ground. A controllable ring voltage-controlled oscillator is designed with good linearity and steady performance. The voltage-controlled oscillator has the function to turn off the circuit of voltage-controlled oscillator to reduce the power consumption when phase-locked loop doesn’t work. To need the requirement of phase-locked loop outputting different frequency, a programmable frequency divider is designed to achieve the programmable control of output frequency of phase-locked loop.
In this paper, the overall circuit and the layout are implemented with 0.15μm CMOS technology,and the work of verification at the levels of circuit and layout have been done in many different Corner condition. The result of the verification proves that the phase-locked loop in the paper accords to the design requirement. The phase-locked loop has been taken out. The result of the test shows that the phase-locked loop achieve the .programmable control of the frequency from 20MHz to 200MHz.
在本文所涉及的锁相环设计过程中,针对数模混合电路的特点,综合考虑了稳定性、锁定速度、功耗等方面的因素,设计的锁相环电路满足锁定速度快、抗噪声力强的要求。设计的可编程电荷泵,提高了锁相环路的频率锁定速度,同时采用将电荷泵开关设置在电流源MOS管源端的电荷泵结构,避免了因过冲电流引起锁相环路的非线性;设计的新型基准电压产生电路,大幅度提高了电路抗电源地噪声的能力;设计的可控环形压控振荡器,具有很好的线性度,性能稳定,并具有关断功能,能够在锁相环不工作时关闭压控振荡器,以降低功耗;为满足锁相环输出不同频率的需要,设计了一款可编程的分频器,实现对锁相环输出频率的可编程控制。
本文基于0.15μm CMOS工艺,设计实现了可编程快速锁定电荷泵型锁相环的电路和版图,并且分别在电路层和版图的层次进行了多个Corner条件下的验证工作,验证结果表明,该锁相环达到了设计指标。该锁相环已经流片。测试结果表明,该锁相环输出频率可以在20MHz到200MHz之间实现可编程控制。
With the development of the integrated circuit, phase-locked loop technology has experienced by the initial number of analog phase-locked loop, mixed-signal phase-locked loop and then all digital phase-locked loop, and developed rapidly. In spite of this, charge-pump phase-locked loop, as the typical representation of mixed-signal phase-locked loop, is still applied in very large scale integrated circuit extensively, since its irreplaceable advantages. In this paper, a programmable fast-locking charge-pump phase-locked loop is designed based on in-depth analyzing the basic theory of charge-pump phase-locked loop and the theory of capture and locking. It can work stability with the output frequency range from 20MHz to 200MHz.
In the light of the characteristic of mixed-signal circuits, phase-locked loop in this paper is comprehensively considered with the tradeoff between such requirements as stability, locking speed and power consumption in the process of design. The circuit designed can meet the needs of fast-locking and high noise resisting ability in the specification. A programmable charge-pump is designed to advance the frequency locking speed of phase-locked loop. In the meaning time, the structure of setting the switch on source side of the current mirror’s MOS transistor in charge-pump is selected to avoid the nonlinearity of phase-locked loop circuit caused by overshoot current. A new circuit to generate voltage reference is designed to greatly advance the ability of resisting noise of power and ground. A controllable ring voltage-controlled oscillator is designed with good linearity and steady performance. The voltage-controlled oscillator has the function to turn off the circuit of voltage-controlled oscillator to reduce the power consumption when phase-locked loop doesn’t work. To need the requirement of phase-locked loop outputting different frequency, a programmable frequency divider is designed to achieve the programmable control of output frequency of phase-locked loop.
In this paper, the overall circuit and the layout are implemented with 0.15μm CMOS technology,and the work of verification at the levels of circuit and layout have been done in many different Corner condition. The result of the verification proves that the phase-locked loop in the paper accords to the design requirement. The phase-locked loop has been taken out. The result of the test shows that the phase-locked loop achieve the .programmable control of the frequency from 20MHz to 200MHz.
引文
[1] H.De Bekkescuze. La Reception Synchrone. L’onde electrique, 1932.5(11):225-240
[2] Vincent von Kaenel, Damel Aebischer, Christran Piguet and Evert Dykstra. A Bicmos PLL-Based Data Separator Circuit with High Stability and Accuracy. IEEE JSSC, 1991.2:117-121
[3]郑禹希.锁相环路原理与应用.人民邮电出版社, 1984
[4] Mark, Van Paemel. Analysis of a Charge-Pump PLL: A New Model. IEEE Trans.on Communications, 1994.7(42):2490-2498
[5] F.M Gardner.锁相环技术(第三版).人民邮电出版社, 2007
[6] Y.Koo. A fully integrated CMOS frequency synthesizer with charge-averaging charging charge pump and dual-path loop filter for PCS and Cellular CDMA wireless system. IEEE JSSC, 2002.5(37):536-542
[7]胡仕刚,熊元新,司龙,徐征.一种基于新型Precharge PFD的CMOS CPPLL设计.微电子学与计算机, 2005(22-9):54-57
[8]胡华春,石玉.数字锁相环路与应用.上海科学技术出版社, 1990
[9] Stanley Goldman. Phase-Locked Loop Engineering Handbook fo Integrated Circuits. Artech House, 2007:516-522
[10] B.Staszewski, P.T.Balsara. Phase-domain all-digital phase locked loop. IEEE Trans.Circuits Syst.Ⅱ,Exp.Briefs, 2004.12(40):2469-2483
[11]罗新民,张传生,薛少丽.现代通信原理.高等教育出版社, 2003.12
[12]黄载禄,殷蔚华,黄本雄.通信原理.科学出版社, 2007.2
[13]何希才.锁相环(PLL)电路设计与应用.科学出版设, 2006.1
[14] Gerry C. T. Leung, Howard C. Luong. A 1-V 5.2-GHz CMOS Synthesizer for WLAN Applications. IEEE JSSC, 2004.11(39):1873-1882
[15] Kossel, M. Morf, T. Weiss. LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. IEEE JSSC, 2009.2(44):436-449
[16] Lizhong Sun, Tad Kwasniewski. A 1.25 GHz 0.35um Monolithic CMOS PLL Clock Generator for Data Communications. IEEE CICC,1999:265-268
[17] Intel Core 2 Extreme Processor QX9000 Series, Intel Core 2 Quad Processor Q9000, Q9000S, Q8000, and Q8000S Series Datasheet. 2009.5
[18] http://cache.baidu.com/c?m=9d78d513d98211ae59eb962d1a16a6310d13c03d338d96533dc3923b8e791a041c30f4bb50734d5bc4c50b365db20b0abeed7424631e41c79ac98e48aeac955c589f2040711b84436da951f98a5125b662c60e&p=882a9705cd9212a059bcc93b53&user=baidu
[19]韩波.一种采用锁相环技术的800MHz CMOS时钟发生器设计.电子科技大学硕士学位论文, 2006
[20] D.K.Jeong. Design of PLL based clock generation circuits. IEEE JSSC, 1987.4(22):255-261
[21] Grawford J. Frequency Synthesizer Design Handbool. Artech House, 1994
[22] Best R.E. Phase-Locked Loops: Design, Simulation and Applications, 3rd ed. McGraw-Hill,1997:156-163
[23] F.M.Gardner. Properties of Frequency Difference Detectors. IEEE Transactions on Communications,1985.2(COM-33):131-138
[24]童诗白,华成英主编.模拟电子技术基础(第三版).高等教育出版社, 2001.1:337-344
[25] M.Toyama. A design of a compact 2GHz-PLL with a new adapative loop filter circuit. IEEE Symp.VLSI Circuits, 2003:185-188
[26]李树芳. MathCAD教程.北京大学出版社, 1994
[27]钱哲弘基于USB2.0的电荷泵锁相环时钟发生器的设计.复旦大学硕士学位论文, 2005.9
[28]远坂俊昭.锁相环(PLL)电路设计与应用.科学出版社, 2006.1
[29] W.Rhee. Design of high-performance CMOS charge pumps in phase-locked loops. IEEE Int.Symp.Circuits and systems, 1999(2):545-548
[30] Woogeun Rhee. Design of High-Performance CMOS Charge Pump in Phase-Locked Loops. IEEE Circuits and Systems, 1999(2):545-548
[31]黄建钢.锁相环频率合成器相位噪声分析.雷达与对抗, 1994(3):57-63
[32] Shu, K.L等编著. CMOS锁相环:分析和设计.科学出版社, 2007.1
[33]陶蕤,王志功,顾峥.低噪声集成压控振荡器噪声性能分析.电子工程师, 2000(1):45-47
[34] Behzad Razavi. A Study of Oscillator Jiter Due to Supply and Substrate Noise. IEEE Trans Circuits and Systems, 1999:56-62
[35] Behzad Razavi著,陈贵灿等译.模拟集成电路设计.西安交通大学出版社,2002
[2] Vincent von Kaenel, Damel Aebischer, Christran Piguet and Evert Dykstra. A Bicmos PLL-Based Data Separator Circuit with High Stability and Accuracy. IEEE JSSC, 1991.2:117-121
[3]郑禹希.锁相环路原理与应用.人民邮电出版社, 1984
[4] Mark, Van Paemel. Analysis of a Charge-Pump PLL: A New Model. IEEE Trans.on Communications, 1994.7(42):2490-2498
[5] F.M Gardner.锁相环技术(第三版).人民邮电出版社, 2007
[6] Y.Koo. A fully integrated CMOS frequency synthesizer with charge-averaging charging charge pump and dual-path loop filter for PCS and Cellular CDMA wireless system. IEEE JSSC, 2002.5(37):536-542
[7]胡仕刚,熊元新,司龙,徐征.一种基于新型Precharge PFD的CMOS CPPLL设计.微电子学与计算机, 2005(22-9):54-57
[8]胡华春,石玉.数字锁相环路与应用.上海科学技术出版社, 1990
[9] Stanley Goldman. Phase-Locked Loop Engineering Handbook fo Integrated Circuits. Artech House, 2007:516-522
[10] B.Staszewski, P.T.Balsara. Phase-domain all-digital phase locked loop. IEEE Trans.Circuits Syst.Ⅱ,Exp.Briefs, 2004.12(40):2469-2483
[11]罗新民,张传生,薛少丽.现代通信原理.高等教育出版社, 2003.12
[12]黄载禄,殷蔚华,黄本雄.通信原理.科学出版社, 2007.2
[13]何希才.锁相环(PLL)电路设计与应用.科学出版设, 2006.1
[14] Gerry C. T. Leung, Howard C. Luong. A 1-V 5.2-GHz CMOS Synthesizer for WLAN Applications. IEEE JSSC, 2004.11(39):1873-1882
[15] Kossel, M. Morf, T. Weiss. LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. IEEE JSSC, 2009.2(44):436-449
[16] Lizhong Sun, Tad Kwasniewski. A 1.25 GHz 0.35um Monolithic CMOS PLL Clock Generator for Data Communications. IEEE CICC,1999:265-268
[17] Intel Core 2 Extreme Processor QX9000 Series, Intel Core 2 Quad Processor Q9000, Q9000S, Q8000, and Q8000S Series Datasheet. 2009.5
[18] http://cache.baidu.com/c?m=9d78d513d98211ae59eb962d1a16a6310d13c03d338d96533dc3923b8e791a041c30f4bb50734d5bc4c50b365db20b0abeed7424631e41c79ac98e48aeac955c589f2040711b84436da951f98a5125b662c60e&p=882a9705cd9212a059bcc93b53&user=baidu
[19]韩波.一种采用锁相环技术的800MHz CMOS时钟发生器设计.电子科技大学硕士学位论文, 2006
[20] D.K.Jeong. Design of PLL based clock generation circuits. IEEE JSSC, 1987.4(22):255-261
[21] Grawford J. Frequency Synthesizer Design Handbool. Artech House, 1994
[22] Best R.E. Phase-Locked Loops: Design, Simulation and Applications, 3rd ed. McGraw-Hill,1997:156-163
[23] F.M.Gardner. Properties of Frequency Difference Detectors. IEEE Transactions on Communications,1985.2(COM-33):131-138
[24]童诗白,华成英主编.模拟电子技术基础(第三版).高等教育出版社, 2001.1:337-344
[25] M.Toyama. A design of a compact 2GHz-PLL with a new adapative loop filter circuit. IEEE Symp.VLSI Circuits, 2003:185-188
[26]李树芳. MathCAD教程.北京大学出版社, 1994
[27]钱哲弘基于USB2.0的电荷泵锁相环时钟发生器的设计.复旦大学硕士学位论文, 2005.9
[28]远坂俊昭.锁相环(PLL)电路设计与应用.科学出版社, 2006.1
[29] W.Rhee. Design of high-performance CMOS charge pumps in phase-locked loops. IEEE Int.Symp.Circuits and systems, 1999(2):545-548
[30] Woogeun Rhee. Design of High-Performance CMOS Charge Pump in Phase-Locked Loops. IEEE Circuits and Systems, 1999(2):545-548
[31]黄建钢.锁相环频率合成器相位噪声分析.雷达与对抗, 1994(3):57-63
[32] Shu, K.L等编著. CMOS锁相环:分析和设计.科学出版社, 2007.1
[33]陶蕤,王志功,顾峥.低噪声集成压控振荡器噪声性能分析.电子工程师, 2000(1):45-47
[34] Behzad Razavi. A Study of Oscillator Jiter Due to Supply and Substrate Noise. IEEE Trans Circuits and Systems, 1999:56-62
[35] Behzad Razavi著,陈贵灿等译.模拟集成电路设计.西安交通大学出版社,2002