超宽带无线通信系统射频前端电路研究与设计
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摘要
超宽带(Ultra-Wide Band,UWB)技术是当前无线通信技术领域发展极为迅速的一种新型无线通信技术。超宽带技术以高速率、高容量,低功耗和低成本等特性受到通信学术界和产业界的重视,并将获得日益广泛的应用。因此,研究并提高超宽带射频通信电路性能,对无线通信的发展具有重要的科学意义和现实意义。
本论文主要研究多载波正交频分复用(MultiBand OFDM,MB-OFDM)超宽带(3.1-10.6GHz)射频前端,包括低噪声放大器、混频器和频率合成器三大主要部件。本文主要的创新工作可概括如下：
(1)本文提出了一种工作在3.1-10.6GHz的超低噪声高线性的超宽带低噪声放大器电路。该低噪声放大器电路主要由两级构成：第一级为输入匹配级,采用共栅结构实现宽带输入匹配；第二级为放大级,采用改进型共源共栅结构组成,这种结构在获得良好增益的同时大大降低了对电源电压的要求。通过采用电感负载峰值技术和极间串联电感峰值技术,在整个频带内获得了良好的增益平坦度。提出的电路采用CHRT0.18μm RF CMOS工艺,在Cadence软件进行仿真,结果表明,在1.5V的电源电压下,该电路在整个带宽内实现了良好的输入输出匹配(S11<-9.5dB,S22<-8dB),增益11.3-15.3dB,最小噪声系数仅为2.75dB,三阶互调截点IIP3为19dB,功耗为17mW。
(2)本文提出了一种工作在3.1-10.6GHz频段的低电压低功耗的超宽带低噪声放大器电路。该低噪声放大器电路主要由两级共源放大器和输出缓冲器构成,采用LC滤波网络实现输入匹配,结合电流复用技术,在整个频带内获得了较低的功耗和较高的增益。提出的电路采用CHRT0.18μmCMOS工艺,在Cadence软件进行仿真,仿真结果表明,在1V的电源电压下,该电路在整个带宽内实现了良好的输入输出匹配(S11-10dB, S22<-10.5dB),增益为15.5-17.5dB,最小噪声系数为2.8dB,功耗仅为6mW。
(3)本文提出了一种工作在3.1-10.6GHz频段的超低功耗高线性度上混频器电路。在传统吉尔伯特(Gilbert)单元电路的基础上,通过在开关对共源节点插入T型LC网络吸收寄生电容,使得混频器的线性度性能有了大幅的改善；结合使用电流注入技术,使得混频器在低功耗条件下具有较高的增益和线性度。提出的电路采用CHRT0.18μm CMOS工艺,在Cadence软件仿真,仿真结果显示,在3.1-10.6GHz频带内,工作电压为1.2V,功耗仅为2.4mW,混频器的转换增益达到了10±1dB,IIP3为7.19dBm,噪声系数为7.1～7.8dB。
(4)本文提出了一种应用于3.1-10.6GHz频段的无电感超宽带频率合成器电路。该电路结构上的特点是：一是只包括一个锁相环和两个宽带单边带混频器,无需在末级单边带混频器增加滤波网络来改善输出信号的纯度,结构上的简化有助于电路功耗、面积和成本的降低。二是在锁相环中采用无电感正交环形振荡器和两路无电感双边带混频器实现单边带混频器,进一步降低了电路的复杂度、版图面积和总功耗。采用TMSC0.18μmRF CMOS工艺,使用ADS工具进行仿真,结果表明,该超宽带频率合成器在1.8V的电压下,产生从3432MHz到10296MHz的频率,载波频率之间的转换时间约为2.5ns,输出信号中的杂散信号功率不超过-30dBc。
Ultra Wide Band (UWB) technology, which has been developed rapidly in the field of wireless communication, is a new type of wireless communications technology. It attracts more and more attention from Communication Field for its high-speed, high capacity, low power consumption and cost, and will be used widely. Therefore, studying and improving Ultra-Wide Band radio communication circuits has important scientific and practical significance for the development of wireless communication.
This dissertation mainly focuses on the study of multi-carrier orthogonal frequency division multiplexing(Multi-Band OFDM, MB-OFDM) of Ultra Wideband(3.1-10.6GHz) RF front-end, including the three main components such as a low noise amplifier, a mixer and a frequency synthesizer. The main innovative work of this dissertation is as follow.
(1) This dissertation proposes a3.1-to10.6-GHz ultra low noise and high linear UWB LNA circuit. The LNA circuit is mainly composed of two components:the first stage is the input matching stage, employing a common-gate structure to realize broadband input matching; the second stage is the amplification stage, using an improved cascade structure which can get a good gain and at the same time reduce the supply voltage requirement. By the use of the LC peaking technology and interelectrode series LC peaking technology, the circuit has obtained good gain flatness in the whole frequency band. The circuit uses the Cadence software to simulate as well as employing the Chartered0.18u m RF CMOS process. Simulation results show that the proposed UWB LNA achieves a good input and output match (S1K<-9.5dB, S22<-8dB), power gain of11.3-15.3dB, minimum noise figure of2.75dB, a power consumption of17mW under a supply voltage of1.5V.
(2) This dissertation proposes a3.1-to10.6-GHz ultra low voltage and low power consumption UWB LNA circuit. The LNA circuit is mainly composed of two-stage common-source amplifier and an output buffer. It has realized the input matching by using the LC filter network and obtained lower power consumption and higher gain in the entire frequency band by employing the current reuse technology. The circuit uses the Cadence software to simulate as well as employing the Chartered0.18μm RF CMOS process. Simulation results show that the proposed UWB LNA achieves a good input and output match (S1K<-10dB, S22<-10.5dB), power gain of15.5-17.5dB, minimum noise figure of2.8dB, a power consumption of6mW under a supply voltage of IV.
(3) This dissertation proposes a3.1-to10.6-GHz ultra low power consumption and high linear UWB Mixer circuit. The Mixer circuit is based on the tradition of Gilbert unit and achieves good performance in supply voltage, power consumption, conversion gain and linearity by employing multiple-input-branch technique, folded topology and a CS output stage. The circuit also uses the Cadence software to simulate as well as employing the Chartered0.18u m RF CMOS process. Simulation results show that the proposed UWB Mixer has a conversion gain of10±dB with a power consumption of2.4mW under a supply voltage of1.2V, SSB noise-figure(NF) of7.1-7.8dB,and IIP3better than7.19dBm.
(4) This dissertation proposes a3.1-to10.6-GHz non-inductive UWB frequency synthesizer circuit. The circuit has two structural characteristics:the first is that it only includes a phase-locked loop and two broadband single-sideband mixers, and it is not necessary to add a filter network on the final stage of single-sideband mixer to improve the purity of the output signal. The simplified structure will contribute lower circuit consumption, less area and cost reduction. The second is that a non-inductive quadrature ring oscillator and two-pass non-inductive double-sideband mixer, which form one single-sideband mixer, are adopted in the phase-locked loop to further reduce the circuit complexity, layout area and power consumption. The circuit uses the ADS software to simulate as well as employing the TMSC0.18u m RF CMOS process. Simulation results show that the UWB frequency synthesizer can produce from3432MHz to10296MHz frequency, conversion time between the carrier frequencies is approximately2.5ns, the spurious signal power in the output does not exceed-30dBc.
本论文主要研究多载波正交频分复用(MultiBand OFDM,MB-OFDM)超宽带(3.1-10.6GHz)射频前端,包括低噪声放大器、混频器和频率合成器三大主要部件。本文主要的创新工作可概括如下：
(1)本文提出了一种工作在3.1-10.6GHz的超低噪声高线性的超宽带低噪声放大器电路。该低噪声放大器电路主要由两级构成：第一级为输入匹配级,采用共栅结构实现宽带输入匹配；第二级为放大级,采用改进型共源共栅结构组成,这种结构在获得良好增益的同时大大降低了对电源电压的要求。通过采用电感负载峰值技术和极间串联电感峰值技术,在整个频带内获得了良好的增益平坦度。提出的电路采用CHRT0.18μm RF CMOS工艺,在Cadence软件进行仿真,结果表明,在1.5V的电源电压下,该电路在整个带宽内实现了良好的输入输出匹配(S11<-9.5dB,S22<-8dB),增益11.3-15.3dB,最小噪声系数仅为2.75dB,三阶互调截点IIP3为19dB,功耗为17mW。
(2)本文提出了一种工作在3.1-10.6GHz频段的低电压低功耗的超宽带低噪声放大器电路。该低噪声放大器电路主要由两级共源放大器和输出缓冲器构成,采用LC滤波网络实现输入匹配,结合电流复用技术,在整个频带内获得了较低的功耗和较高的增益。提出的电路采用CHRT0.18μmCMOS工艺,在Cadence软件进行仿真,仿真结果表明,在1V的电源电压下,该电路在整个带宽内实现了良好的输入输出匹配(S11-10dB, S22<-10.5dB),增益为15.5-17.5dB,最小噪声系数为2.8dB,功耗仅为6mW。
(3)本文提出了一种工作在3.1-10.6GHz频段的超低功耗高线性度上混频器电路。在传统吉尔伯特(Gilbert)单元电路的基础上,通过在开关对共源节点插入T型LC网络吸收寄生电容,使得混频器的线性度性能有了大幅的改善；结合使用电流注入技术,使得混频器在低功耗条件下具有较高的增益和线性度。提出的电路采用CHRT0.18μm CMOS工艺,在Cadence软件仿真,仿真结果显示,在3.1-10.6GHz频带内,工作电压为1.2V,功耗仅为2.4mW,混频器的转换增益达到了10±1dB,IIP3为7.19dBm,噪声系数为7.1～7.8dB。
(4)本文提出了一种应用于3.1-10.6GHz频段的无电感超宽带频率合成器电路。该电路结构上的特点是：一是只包括一个锁相环和两个宽带单边带混频器,无需在末级单边带混频器增加滤波网络来改善输出信号的纯度,结构上的简化有助于电路功耗、面积和成本的降低。二是在锁相环中采用无电感正交环形振荡器和两路无电感双边带混频器实现单边带混频器,进一步降低了电路的复杂度、版图面积和总功耗。采用TMSC0.18μmRF CMOS工艺,使用ADS工具进行仿真,结果表明,该超宽带频率合成器在1.8V的电压下,产生从3432MHz到10296MHz的频率,载波频率之间的转换时间约为2.5ns,输出信号中的杂散信号功率不超过-30dBc。
Ultra Wide Band (UWB) technology, which has been developed rapidly in the field of wireless communication, is a new type of wireless communications technology. It attracts more and more attention from Communication Field for its high-speed, high capacity, low power consumption and cost, and will be used widely. Therefore, studying and improving Ultra-Wide Band radio communication circuits has important scientific and practical significance for the development of wireless communication.
This dissertation mainly focuses on the study of multi-carrier orthogonal frequency division multiplexing(Multi-Band OFDM, MB-OFDM) of Ultra Wideband(3.1-10.6GHz) RF front-end, including the three main components such as a low noise amplifier, a mixer and a frequency synthesizer. The main innovative work of this dissertation is as follow.
(1) This dissertation proposes a3.1-to10.6-GHz ultra low noise and high linear UWB LNA circuit. The LNA circuit is mainly composed of two components:the first stage is the input matching stage, employing a common-gate structure to realize broadband input matching; the second stage is the amplification stage, using an improved cascade structure which can get a good gain and at the same time reduce the supply voltage requirement. By the use of the LC peaking technology and interelectrode series LC peaking technology, the circuit has obtained good gain flatness in the whole frequency band. The circuit uses the Cadence software to simulate as well as employing the Chartered0.18u m RF CMOS process. Simulation results show that the proposed UWB LNA achieves a good input and output match (S1K<-9.5dB, S22<-8dB), power gain of11.3-15.3dB, minimum noise figure of2.75dB, a power consumption of17mW under a supply voltage of1.5V.
(2) This dissertation proposes a3.1-to10.6-GHz ultra low voltage and low power consumption UWB LNA circuit. The LNA circuit is mainly composed of two-stage common-source amplifier and an output buffer. It has realized the input matching by using the LC filter network and obtained lower power consumption and higher gain in the entire frequency band by employing the current reuse technology. The circuit uses the Cadence software to simulate as well as employing the Chartered0.18μm RF CMOS process. Simulation results show that the proposed UWB LNA achieves a good input and output match (S1K<-10dB, S22<-10.5dB), power gain of15.5-17.5dB, minimum noise figure of2.8dB, a power consumption of6mW under a supply voltage of IV.
(3) This dissertation proposes a3.1-to10.6-GHz ultra low power consumption and high linear UWB Mixer circuit. The Mixer circuit is based on the tradition of Gilbert unit and achieves good performance in supply voltage, power consumption, conversion gain and linearity by employing multiple-input-branch technique, folded topology and a CS output stage. The circuit also uses the Cadence software to simulate as well as employing the Chartered0.18u m RF CMOS process. Simulation results show that the proposed UWB Mixer has a conversion gain of10±dB with a power consumption of2.4mW under a supply voltage of1.2V, SSB noise-figure(NF) of7.1-7.8dB,and IIP3better than7.19dBm.
(4) This dissertation proposes a3.1-to10.6-GHz non-inductive UWB frequency synthesizer circuit. The circuit has two structural characteristics:the first is that it only includes a phase-locked loop and two broadband single-sideband mixers, and it is not necessary to add a filter network on the final stage of single-sideband mixer to improve the purity of the output signal. The simplified structure will contribute lower circuit consumption, less area and cost reduction. The second is that a non-inductive quadrature ring oscillator and two-pass non-inductive double-sideband mixer, which form one single-sideband mixer, are adopted in the phase-locked loop to further reduce the circuit complexity, layout area and power consumption. The circuit uses the ADS software to simulate as well as employing the TMSC0.18u m RF CMOS process. Simulation results show that the UWB frequency synthesizer can produce from3432MHz to10296MHz frequency, conversion time between the carrier frequencies is approximately2.5ns, the spurious signal power in the output does not exceed-30dBc.
引文
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