基于SOCS的光学光刻系统仿真算法的研究
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摘要
从0.18μm技术节点开始,半导体制造工艺中便广泛采用了“亚波长光刻”技术。在亚波长光刻下,由于光刻和掩模制造过程中的光的衍射及其他物理、化学现象,光刻后硅片表面成像将产生明显的畸变。版图图形转移过程中的失真,将会影响到产品的性能参数,降低集成电路的成品率。为了消除这些负面的影响,半导体业界提出并广泛采用分辨率增强技术(RET)作为应对。RET的采用能够在一定程度上解决亚波长光刻中的失真问题,而相关EDA算法工具的开发应用是解决问题的关键所在。
无论何种分辨率增强技术,都需要有快速、精确、有效的光刻系统模型和相应的算法的支持。掩模补偿技术是目前分辨增强技术的主要形式,利用光刻系统模型,可以预测实际光刻条件下掩模在硅片表面所成的图像,从而做出正确的掩模预补偿。
本文主要围绕光刻系统模型的结构和相关算法以及具体实现等问题展开。本文介绍了集成电路制造和光刻工艺的基本流程及相关理论。针对光刻模型的光学成像系统,本文介绍了基本的基于Hopkins公式的曝光系统模型以及Hopkins的近似算法,即所谓的基于特征函数的SOCS算法。实现了光刻仿真工具Litholab中用于建立掩模图形模型的CMask部分和用于光强计算的CInten部分,并提出了几种用于提高SOCS算法精度的优化方案。
Beginning from the 0.18μm technology node, the so-called Sub-Wavelength Lithography has been widely used in semiconductor processes. Because of the diffraction and scatter and other physical and chemical phenomena during optical lithography and mask writing under Sub-Wavelength Lithography, the printed shapes on silicon wafer will not be consistent with the mask patterns. The distortions in pattern transfer may influence the functionality and performance of IC products and lower the production yield. Revolution Enhancement Technologies ( RETs ) are developed and applied widely in order to solve the manufacturability problems and the sticking point of this issue is the progress of corresponding EDA tools and algorithms.RETs need the support of fast and accurate lithography process models and relevant theories and algorithms. Layout modifications are the main ways of RET and need a tool to simulate the image on the wafer under real lithography situations. The framework of the lithography model and algorithms are the major research objects of this thesis. Flows of IC design and manufacturability and photolithography are described. An optical model with Hopkins and an approximate algorithm, so-called SOCS algorithm, are presented as well. Two parts of the lithography simulation tool named Litholab are implemented, one is CMask which is to establish mask model and the other is CInten which implement the intensity calculation. And some optimization methods of the SOCS algorithm are introduced.
无论何种分辨率增强技术,都需要有快速、精确、有效的光刻系统模型和相应的算法的支持。掩模补偿技术是目前分辨增强技术的主要形式,利用光刻系统模型,可以预测实际光刻条件下掩模在硅片表面所成的图像,从而做出正确的掩模预补偿。
本文主要围绕光刻系统模型的结构和相关算法以及具体实现等问题展开。本文介绍了集成电路制造和光刻工艺的基本流程及相关理论。针对光刻模型的光学成像系统,本文介绍了基本的基于Hopkins公式的曝光系统模型以及Hopkins的近似算法,即所谓的基于特征函数的SOCS算法。实现了光刻仿真工具Litholab中用于建立掩模图形模型的CMask部分和用于光强计算的CInten部分,并提出了几种用于提高SOCS算法精度的优化方案。
Beginning from the 0.18μm technology node, the so-called Sub-Wavelength Lithography has been widely used in semiconductor processes. Because of the diffraction and scatter and other physical and chemical phenomena during optical lithography and mask writing under Sub-Wavelength Lithography, the printed shapes on silicon wafer will not be consistent with the mask patterns. The distortions in pattern transfer may influence the functionality and performance of IC products and lower the production yield. Revolution Enhancement Technologies ( RETs ) are developed and applied widely in order to solve the manufacturability problems and the sticking point of this issue is the progress of corresponding EDA tools and algorithms.RETs need the support of fast and accurate lithography process models and relevant theories and algorithms. Layout modifications are the main ways of RET and need a tool to simulate the image on the wafer under real lithography situations. The framework of the lithography model and algorithms are the major research objects of this thesis. Flows of IC design and manufacturability and photolithography are described. An optical model with Hopkins and an approximate algorithm, so-called SOCS algorithm, are presented as well. Two parts of the lithography simulation tool named Litholab are implemented, one is CMask which is to establish mask model and the other is CInten which implement the intensity calculation. And some optimization methods of the SOCS algorithm are introduced.
引文
[Adam00] K. Adam and a. Neureuther, Analysis of OPC features in binary masks at 193nm, SPIP Proc Optical Microlithography ⅩⅢ, 2000, 4000: 711-722
[Adam03] K. Adam and Y. Granik, A. Torres et al,"Improved Modeling Performance with an Adapted Vectorial Formulation of the Hopkins Imaging Equation, Proceeding of SPIE, 2003, 5040
[Chou96] S. Y. Chou, P. R. Krauss and P. J. Renstrom. Imprint Lithography with 25-nanometer resolution. Science, 1996, 272: 85
[Cobb96] N. Cobb, A. Zakhor and E. Miloslavsk, Mathematical and CAD Framework for Proximity Correction, Proceedings of the SPIE, 1996, 2726
[Cobb98] N. Cobb, Fast Optical and Process Proximity Correction Algorithms for Integrated Circuit Manufacturing, Berkeley: University of California at Berkeley, 1998
[Cobb03] N. Cobb and W. Maurer, Flows for model-based layout correction of mask proximity effects, Proceedings of SPIE, 2003, 5256(23): 956-964
[Flanner86] P. D. Flanner, Two-dimension optical imaging for photolithography simulation, Tech. Rep. Memorandum No. UCB/ERL M86/57, Electronics Reaserch Laboratory, University of California at Berkeley, 1986
[Garofalo95] J. Garofalo, J. DeMarco, J. Bailey, et al, Reduction of ASIC gate-level line-end shorting by mask compensation, Proceedings of SPIE, 1995, 2240
[Granik01] Y. Granik, Correction for etch proximity: new models and applications, SPIE, 2001, 4346: 98-112
[Hirotomo99] Hirotomo Inui, Toshiyuki Ohta, Accurate resist profile simulation for large area OPC. IEEE International Conference on Simulation of Semiconductor Processed and Devices, Kyoto, 1999: 111
[Hopkins51] H. H. Hopkins, The Concept of Partial Coherence in Optics, Proc. Royal Soc. London, 1951, A208: 263-277
[ITRS01] Semiconductor Industry Association, The international Technology Roadmap for Semiconductors, 2001 Edition
[ITRS03] Semiconductor Industry Association, The international Technology Roadmap for Semiconductors, 2003 Edition
[ITRS05] Semiconductor Industry Association, The international Technology Roadmap for Semiconductors, 2005 Edition
[Karklin00] L. Karklin and B. J. Lin, Resolution Enhancement Techniques and Mask Manufacturability for Sub-wavelength Lithography, Proceedings of SPIE, 2000, 4066: 40-46
[Kahng99] A. B. Kahng and Y. C. Pati, Sub-wavelength Optical Lithography: Challenges and Impact on Physical Design. Proceeding of the 1999 International Symposium on Physical Design, California, 1999: 112
[Dang97] K. Dang, Development and characterization of multilevel metal interconnection etch process, SPIE, 1997, 3213: 91-100
[Jones03] R. Jones and J. Byers, Theoretical Comer Rounding Analysis and Mask Writer Simulation, SPIE Proc Optical Microlithography ⅩⅥ, 2003, 5040: 1035-1043
[Kirchauer98] H. Kirchauer, Photolithography Simulation, Ph. D. Dissertation, Institute for Microelectronics, TU Vienna, 1998
[Levinson01] H. J. Levinson,"Principles of lithography", SPIE press, 2001
[Liebmann01] L. W. Liebmann, Resolution Enhancement Techniques in Optical Lithography: It's not just a Mask Problem, Photomask and Next-Generation Lithography Mask Technology Ⅷ, Proceeding of SPIE, 2001, 4409: 23-32
[Liu98] H. Y. Liu, L. Karklin, Y. T. Wang, et al., The Application of Alternating Phase-shifting Masks to 140nm Gate Patteming(Ⅱ): Mask Design and Manufacturing Tolerances, SPIE, 1998, 3334: 2-14
[NEWS03] http://www.reed-electronics.com/electronicnews/article/CA301016.html
[NEWS05a] http://www.3gcn.org/index.php?option=com_content&task=view&id=442&Itemid=2
[NEWS05b] http://www10.edacafe.com/nbe/articles/view_article.php?section=ICNews&artieleid=167405
[NEWS05c] http://www.sichinamag.com/Article/html/2005-10/20061121430518036e.htm
[O'Toole79] M. M. O' Toole and A. R. Neureuther, The Influence of Partial Coherence on Projection Printing, In Proc. SPIE Developments in Semiconductor Microlithography Ⅳ, 1979, 174: 22-27,
[Pati97] Y. C. Pati, A. A. Ghazanfarian and R. F. Pease. Exploiting Structure in Fast Aerial Image Computation for Integrated Circuit Patterns. IEEE Transactions on Semiconductor Manufacturing, 1997, 10(1): 62-74
[Pitchumani05] Vijay Pitchumani, Design for Manufacturability, embedded turoriai, ASPDAC2005
[Wong95] A. K. Wong and A. R. Neureuthr, Rigorous Three-Dimensional Time-Domain Finite-Difference Electromagnetic Simulation for Photolithographic Application, IEEE Transactions on Semiconductor Manufacturing, 1995, 8(4): 419-430
[陈晓辉 06] 陈晓辉,“超深亚微米下一种光刻仿真工具的系统框架研究及其实现”,浙江大学硕士学位论文,2006
[陈志锦 02] 陈志锦,史峥,王国雄,付萍,严晓浪,“一种快速光刻模拟中二维成像轮廓提取的新方法”,半导体学报,2002,Vol.23 No.7:766
[陈志锦 03] 陈志锦,“超深亚微米集成电路制造过程中光学邻近效应模拟的研究”,浙江大学硕士学位论文,2003
[杜惊雷 01] 杜惊雷,石瑞英,崔铮,郭永康,“掩模制作中的邻近效应”,微纳电子技术,2002,No.11
[史峥 05] 史峥,“亚波长光刻条件下集成电路可制造性设计与验证技术研究”,浙江大学博士学位论文,2005
[王阳元 01] 王阳元,康晋锋,“硅集成电路光刻技术的发展与挑战”,半导体学报 2002,Vol.23 No.3:225-237
[Adam03] K. Adam and Y. Granik, A. Torres et al,"Improved Modeling Performance with an Adapted Vectorial Formulation of the Hopkins Imaging Equation, Proceeding of SPIE, 2003, 5040
[Chou96] S. Y. Chou, P. R. Krauss and P. J. Renstrom. Imprint Lithography with 25-nanometer resolution. Science, 1996, 272: 85
[Cobb96] N. Cobb, A. Zakhor and E. Miloslavsk, Mathematical and CAD Framework for Proximity Correction, Proceedings of the SPIE, 1996, 2726
[Cobb98] N. Cobb, Fast Optical and Process Proximity Correction Algorithms for Integrated Circuit Manufacturing, Berkeley: University of California at Berkeley, 1998
[Cobb03] N. Cobb and W. Maurer, Flows for model-based layout correction of mask proximity effects, Proceedings of SPIE, 2003, 5256(23): 956-964
[Flanner86] P. D. Flanner, Two-dimension optical imaging for photolithography simulation, Tech. Rep. Memorandum No. UCB/ERL M86/57, Electronics Reaserch Laboratory, University of California at Berkeley, 1986
[Garofalo95] J. Garofalo, J. DeMarco, J. Bailey, et al, Reduction of ASIC gate-level line-end shorting by mask compensation, Proceedings of SPIE, 1995, 2240
[Granik01] Y. Granik, Correction for etch proximity: new models and applications, SPIE, 2001, 4346: 98-112
[Hirotomo99] Hirotomo Inui, Toshiyuki Ohta, Accurate resist profile simulation for large area OPC. IEEE International Conference on Simulation of Semiconductor Processed and Devices, Kyoto, 1999: 111
[Hopkins51] H. H. Hopkins, The Concept of Partial Coherence in Optics, Proc. Royal Soc. London, 1951, A208: 263-277
[ITRS01] Semiconductor Industry Association, The international Technology Roadmap for Semiconductors, 2001 Edition
[ITRS03] Semiconductor Industry Association, The international Technology Roadmap for Semiconductors, 2003 Edition
[ITRS05] Semiconductor Industry Association, The international Technology Roadmap for Semiconductors, 2005 Edition
[Karklin00] L. Karklin and B. J. Lin, Resolution Enhancement Techniques and Mask Manufacturability for Sub-wavelength Lithography, Proceedings of SPIE, 2000, 4066: 40-46
[Kahng99] A. B. Kahng and Y. C. Pati, Sub-wavelength Optical Lithography: Challenges and Impact on Physical Design. Proceeding of the 1999 International Symposium on Physical Design, California, 1999: 112
[Dang97] K. Dang, Development and characterization of multilevel metal interconnection etch process, SPIE, 1997, 3213: 91-100
[Jones03] R. Jones and J. Byers, Theoretical Comer Rounding Analysis and Mask Writer Simulation, SPIE Proc Optical Microlithography ⅩⅥ, 2003, 5040: 1035-1043
[Kirchauer98] H. Kirchauer, Photolithography Simulation, Ph. D. Dissertation, Institute for Microelectronics, TU Vienna, 1998
[Levinson01] H. J. Levinson,"Principles of lithography", SPIE press, 2001
[Liebmann01] L. W. Liebmann, Resolution Enhancement Techniques in Optical Lithography: It's not just a Mask Problem, Photomask and Next-Generation Lithography Mask Technology Ⅷ, Proceeding of SPIE, 2001, 4409: 23-32
[Liu98] H. Y. Liu, L. Karklin, Y. T. Wang, et al., The Application of Alternating Phase-shifting Masks to 140nm Gate Patteming(Ⅱ): Mask Design and Manufacturing Tolerances, SPIE, 1998, 3334: 2-14
[NEWS03] http://www.reed-electronics.com/electronicnews/article/CA301016.html
[NEWS05a] http://www.3gcn.org/index.php?option=com_content&task=view&id=442&Itemid=2
[NEWS05b] http://www10.edacafe.com/nbe/articles/view_article.php?section=ICNews&artieleid=167405
[NEWS05c] http://www.sichinamag.com/Article/html/2005-10/20061121430518036e.htm
[O'Toole79] M. M. O' Toole and A. R. Neureuther, The Influence of Partial Coherence on Projection Printing, In Proc. SPIE Developments in Semiconductor Microlithography Ⅳ, 1979, 174: 22-27,
[Pati97] Y. C. Pati, A. A. Ghazanfarian and R. F. Pease. Exploiting Structure in Fast Aerial Image Computation for Integrated Circuit Patterns. IEEE Transactions on Semiconductor Manufacturing, 1997, 10(1): 62-74
[Pitchumani05] Vijay Pitchumani, Design for Manufacturability, embedded turoriai, ASPDAC2005
[Wong95] A. K. Wong and A. R. Neureuthr, Rigorous Three-Dimensional Time-Domain Finite-Difference Electromagnetic Simulation for Photolithographic Application, IEEE Transactions on Semiconductor Manufacturing, 1995, 8(4): 419-430
[陈晓辉 06] 陈晓辉,“超深亚微米下一种光刻仿真工具的系统框架研究及其实现”,浙江大学硕士学位论文,2006
[陈志锦 02] 陈志锦,史峥,王国雄,付萍,严晓浪,“一种快速光刻模拟中二维成像轮廓提取的新方法”,半导体学报,2002,Vol.23 No.7:766
[陈志锦 03] 陈志锦,“超深亚微米集成电路制造过程中光学邻近效应模拟的研究”,浙江大学硕士学位论文,2003
[杜惊雷 01] 杜惊雷,石瑞英,崔铮,郭永康,“掩模制作中的邻近效应”,微纳电子技术,2002,No.11
[史峥 05] 史峥,“亚波长光刻条件下集成电路可制造性设计与验证技术研究”,浙江大学博士学位论文,2005
[王阳元 01] 王阳元,康晋锋,“硅集成电路光刻技术的发展与挑战”,半导体学报 2002,Vol.23 No.3:225-237