基于DSP的图像编码研究
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摘要
随着人们对数字电视，有线／无线可视电话，多媒体应用和视频在介质上存储的广泛关
注，过去十年来，视频压缩编码技术有了巨大的发展。目前最成功的技术是基于运动估值，
DCT的混合视频编码方案，并导致了ITU-T H．261／3，MPEG-1/2，MPEG-4等国际标准的出
现。这些技术的计算密集的特点对其实时实现提出了挑战。
专用的基于VLSI的实现是一种解决方案，既可以作为专用的编解码器，又可以作为其
中的核心模块。这种方法十分有效，因为设计可以针对专门的算法进行高度优化。其缺点在
于其中有大量的专用模块，当算法需要修改时，便无法适应新的算法，只能重新设计。
更加灵活的方案是利用可编程DSP。这种方法不仅缩短了开发时间而且具有高度的适
应性。而且随着VLSI技术的不断发展，DSP实现与VLSI实现的性能差别也将越来越小。
本文首先回顾了DSP处理器结构的演进，然后对视频编码DSP实现的方法进行了探讨。
从实时性要求，系统开销的角度分析了如何对算法，程序，以及并行性等进行改进才能满足
实时要求，减少系统开销。同时基于DSP系统有限的存储器资源，从改写程序代码的角度，
提出了减小存储器占用的策略。
本文最后以MPEG-4 Simple Profile编码在TI C6201上的实现为例说明了整个DSP程序
开发的流程，对其中采用的各种优化技术进行了一一介绍。
Due to the increasing interests in digital TV,wired/wireless video telephony,multimedia applications and storage of video on compact disks,there has been tremendous progress in video compression and coding for the last decade. The most successful techniques so far are the hybrid coding schemes,i.e.,those based on motion estimation(ME) and discrete cosine transformation(DCT).The hybrid coding gives rise to all international standards for moving images,i.e.,ITU-T H.261/3,MPEG-l/2 and MPEG-4. The intensive computation involved in these techniques poses challenges to real-time implementation.
Dedicated VLSI-based implementation can be made for such computationally intensive schemes,as either complete codecs or core modules. These approaches are efficient since the design can be highly optimized for particular algorithms. Disadvantages of the approach are the large number of dedicated modules and their limited adaptability for an algorithm to be modified. Adaptation to a new coding scheme can result in a redesign.
More flexible implementation is achieved by utilizing programmable DSP. Such an approach not only shorten the time to market but also offers adaptability by reprogramming. With the development of VLSI technique,the performance difference between DSP implementation and VLSI will become very small.
This paper is composed of the following parts:
Firstly,major video coding techniques and standards and the evolution of DSP architecture is analyzed.
Secondly,the methodology of video coding implementation on DSP is given. To meet the real-time requirements and lower the cost some major principles must be adopted during the process of choosing algorithm,writing code and utilizing parallelism.
Lastly,as an example of DSP implementation of video coding,the development flow of MPEG-4 video Simple Profile coding on TMS320C6201 DSP is presented. Major techniques are also given.
注，过去十年来，视频压缩编码技术有了巨大的发展。目前最成功的技术是基于运动估值，
DCT的混合视频编码方案，并导致了ITU-T H．261／3，MPEG-1/2，MPEG-4等国际标准的出
现。这些技术的计算密集的特点对其实时实现提出了挑战。
专用的基于VLSI的实现是一种解决方案，既可以作为专用的编解码器，又可以作为其
中的核心模块。这种方法十分有效，因为设计可以针对专门的算法进行高度优化。其缺点在
于其中有大量的专用模块，当算法需要修改时，便无法适应新的算法，只能重新设计。
更加灵活的方案是利用可编程DSP。这种方法不仅缩短了开发时间而且具有高度的适
应性。而且随着VLSI技术的不断发展，DSP实现与VLSI实现的性能差别也将越来越小。
本文首先回顾了DSP处理器结构的演进，然后对视频编码DSP实现的方法进行了探讨。
从实时性要求，系统开销的角度分析了如何对算法，程序，以及并行性等进行改进才能满足
实时要求，减少系统开销。同时基于DSP系统有限的存储器资源，从改写程序代码的角度，
提出了减小存储器占用的策略。
本文最后以MPEG-4 Simple Profile编码在TI C6201上的实现为例说明了整个DSP程序
开发的流程，对其中采用的各种优化技术进行了一一介绍。
Due to the increasing interests in digital TV,wired/wireless video telephony,multimedia applications and storage of video on compact disks,there has been tremendous progress in video compression and coding for the last decade. The most successful techniques so far are the hybrid coding schemes,i.e.,those based on motion estimation(ME) and discrete cosine transformation(DCT).The hybrid coding gives rise to all international standards for moving images,i.e.,ITU-T H.261/3,MPEG-l/2 and MPEG-4. The intensive computation involved in these techniques poses challenges to real-time implementation.
Dedicated VLSI-based implementation can be made for such computationally intensive schemes,as either complete codecs or core modules. These approaches are efficient since the design can be highly optimized for particular algorithms. Disadvantages of the approach are the large number of dedicated modules and their limited adaptability for an algorithm to be modified. Adaptation to a new coding scheme can result in a redesign.
More flexible implementation is achieved by utilizing programmable DSP. Such an approach not only shorten the time to market but also offers adaptability by reprogramming. With the development of VLSI technique,the performance difference between DSP implementation and VLSI will become very small.
This paper is composed of the following parts:
Firstly,major video coding techniques and standards and the evolution of DSP architecture is analyzed.
Secondly,the methodology of video coding implementation on DSP is given. To meet the real-time requirements and lower the cost some major principles must be adopted during the process of choosing algorithm,writing code and utilizing parallelism.
Lastly,as an example of DSP implementation of video coding,the development flow of MPEG-4 video Simple Profile coding on TMS320C6201 DSP is presented. Major techniques are also given.
引文
[1] 周一珂，“常见图像压缩标准介绍”，http：／／www．bocom．com．cn／luntan-003． htm，博康 系统工程
[2] “MPEG的新发展--MPEG-4、 MPEG-7”，http：／／www．edu12． com／SERVICES／support／ tech_resourcees／mpeg4_new．htm
[3] 姚庆栋，徐孟侠等，“图像编码基础”(修订版)，浙江大学出版社
[4] Lulin Chen; Zhihai He; Sethuraman, S.; Chang Wen Chen;"MPEG-4 encoder implementation on MAP-CA" Consumer Electronics, 2002． ICCE. 2002 Digest of Technical Papers. International Conference on , 2002 Page(s): 276-277
[5] 毛讯， “高速视频解码器设计研究”，浙江大学博士学位论文，2001
[6] 王蕙， “实时视频图像压缩处理SOC设计研究”，浙江大学硕士学位论文，2002
[7] William Stallings，“计算级组织与结构性能设计”清华大学出版社
[8] W. Lin, B. Tye, E. Ong, C. Xiong et al. "Systematic Analysis and Methodology of Real-time DSP Implementation for Hybrid Video Co ding "IEEE. 1999 Page(s):847-851
[9] Eddv De Greef, Francky Catthoor et al. "Program Transformation Strategies for Memory Size and Power Reduction of Pseudoregular Multimedia Subsystems "IEEE. 1998 Page(s):719-733
[10] N.Liveris,N.D.Zervas,et al. "A Code Transformation-Based Methodology for Improving I-cache Performance of DSP Applications "IEEE. Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition y .2002． Page(s)1530-1591
[11] Equator Technologies,Inc "MAP-CA DSP Datasheet "June 2001
[12] Texas Instruments, Inc "DSP Selection Guide "Oct.2002
[13] Texas Instruments,Inc "TMS320C5207 Datasheet "Mar. 1998
[14] Texas Instruments,Inc" TMS320DM642 Datasheet"Jul.2002
[15] Analog Devices,Inc, "ADSP-TS101s TigerSHARC DSP Micorcomputer Data Sheet "2002
[16] Analog Devices,Inc," ADSP-2106x SHARC DSP Micorcomputer Family"2000
[17] Analog Devices,Inc," ADSP-21535 Preliminary Technical Data"Jun.2002
[18] Philips Semiconductors, "TM-1300 Media Processor DATA BOOK"May 2000
[19] Philips Semiconductors, "PNX1300 Series Media Processors DATA BOOK"Feb.2002
[20] Jennifer Eyve,Jeff Bier, "The evolution of DSP Processors "IEEE Signal Processing Magazine Mar.2000 Page(s):44-51
[21] 崔之祜，江春等译“数字视频处理”电子工业出版社
[22] 马小虎，张明敏等编“多媒体数据压缩标准及实现”清华大学出版社
[23] Texas Instruments,Inc "TMS320C6x Evaluation Module "1998
[24] Texas Instruments,Inc "TMS320C62x/67x CPU and Instruction Set" 1998
[25] Texas Instruments,Inc "TMS320C62x/67x Programmer's Guide " 1998
[26] Texas Instruments,Inc "TMS320C6000 Optimizing C Compiler " 1998
[27] Texas Instruments,Inc "TMS320C6000 Peripherals" 1999
[28] 钟玉琢，王琪等“基于对象的多媒体数据压缩编码国际标准MPEG-4及其校验模 型”科学出版社
[29] H. Yamauchi, et al., "Architecture and Implementation of a Highly Parallel Single-Chip Video DSP" , vol. 2,no.2,pp207-220, Jun.1992
[30] M.Toyokura, et al., "A Video DSP with a Macroblock-Level-Pipeline and a SIMD Type Vector-Pipeline Architecture for MPEG-2 CODEC ", IEEE Journal of solid-State Circuits, vol.29 12, pp. 1474-1481, Dec. 1994
[31] Simar, R., Jr, "Codevelopment of the TMS320C6X VelociTI architecture and compiler", Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 3145-3148, vol.5, 1998
[32] 龚惠民， “视频解码系统设计”浙江大学硕士学位论文，2002
[33] Bryan,"Video Compression and VLSI"IEEE 1993 Custom Integrated Circuits Comference
[34] Ycong Kong Lai et al."A Novel Video Signal Processor with Programmable Data Arrangement and Efficient Memory Configuration "IEEE, 1996
[35] T.Akiyama,H.Aono et al. "MPEG-2 Video Codec using Image Compression DSP "IEEE 1994,Page(s): 150-151
[36] "VLIW Architectures for Media Processing" IEEE Signal Processing Magazine .Mar.1998 Page(s):16-19
[37] Sang Joon Nam,Young-Su Kwon, "DIVA:DUAL-ISSUE VLIW ARCHITECTURE WITH MEDIA INSTRUCTIONS FOR IMAGE PROCESSING "IEEE Transactions on Consumer Electronics.Vol.45． No. 1 .Feb. 1999 Page(s): 192-202
[38] 邱钢等“运用定点DSP实现MPEG-4标准中DCT系数快速量化的方法”电子技术应用 2002年第二期Page(s)：73-74
[39] 王栋，张兆杨等“基于TMS320C6000 DSP的视频解码器设计及其硬件实现方案”电 子技术应用2002年第二期Page(s)：78-80
[40] 焦晓等“基于DSP的实时MPEG-4编码的软件优化设计”电子技术应用2002年第六 期Page(s)：22-24
[41] 郑方译“IDSP体系结构在提高实时信号处理方面的作用”电子产品世界1998年11 月
[42] Masatoshi Matssuo,Hitoshi Fujimoto et al. "A Programmable Video Codec System for Low-Bit-Rate Communication" IEEE Transactions on Consumer Electronics Page(s):903-910 1997
[43] 曹锦薇“两种最新的运动矢量搜索算法”北京广播学院学报2000-2 Page(s)：33-38
[44] 杜诚，何芸等“新的低码率视频编码快速半像素搜索算法”清华大学学报2001年第 41卷第一期
[45] 王维东，姚庆栋“亚像素运动估值快速算法”信号处理2002年2月第18卷第一期
[46] 刘海峰，郭宝龙等“用于块匹配运动估值的正方形-菱形搜索算法”计算机学报2002 年7月第25卷第七期
[47] H.Lee,K.Nguyen-phi et al. "Software-Only Real-Time MPEG-2 Video Encoding on The C62x VLIW Processor"
[48] Yuen-Wen Lee, Faouzi Kossentini, Rabab Ward and Mark Smith, "Towards MPEG4: An ImprovedH.263-based video coder," in Signal Processing Image Communication, Oct. 1997．
[49] Thomas Sikora, "MPEG Digital Video-Coding Standards," IEEE Signal Processing Magazine, Sept 1997．
[2] “MPEG的新发展--MPEG-4、 MPEG-7”，http：／／www．edu12． com／SERVICES／support／ tech_resourcees／mpeg4_new．htm
[3] 姚庆栋，徐孟侠等，“图像编码基础”(修订版)，浙江大学出版社
[4] Lulin Chen; Zhihai He; Sethuraman, S.; Chang Wen Chen;"MPEG-4 encoder implementation on MAP-CA" Consumer Electronics, 2002． ICCE. 2002 Digest of Technical Papers. International Conference on , 2002 Page(s): 276-277
[5] 毛讯， “高速视频解码器设计研究”，浙江大学博士学位论文，2001
[6] 王蕙， “实时视频图像压缩处理SOC设计研究”，浙江大学硕士学位论文，2002
[7] William Stallings，“计算级组织与结构性能设计”清华大学出版社
[8] W. Lin, B. Tye, E. Ong, C. Xiong et al. "Systematic Analysis and Methodology of Real-time DSP Implementation for Hybrid Video Co ding "IEEE. 1999 Page(s):847-851
[9] Eddv De Greef, Francky Catthoor et al. "Program Transformation Strategies for Memory Size and Power Reduction of Pseudoregular Multimedia Subsystems "IEEE. 1998 Page(s):719-733
[10] N.Liveris,N.D.Zervas,et al. "A Code Transformation-Based Methodology for Improving I-cache Performance of DSP Applications "IEEE. Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition y .2002． Page(s)1530-1591
[11] Equator Technologies,Inc "MAP-CA DSP Datasheet "June 2001
[12] Texas Instruments, Inc "DSP Selection Guide "Oct.2002
[13] Texas Instruments,Inc "TMS320C5207 Datasheet "Mar. 1998
[14] Texas Instruments,Inc" TMS320DM642 Datasheet"Jul.2002
[15] Analog Devices,Inc, "ADSP-TS101s TigerSHARC DSP Micorcomputer Data Sheet "2002
[16] Analog Devices,Inc," ADSP-2106x SHARC DSP Micorcomputer Family"2000
[17] Analog Devices,Inc," ADSP-21535 Preliminary Technical Data"Jun.2002
[18] Philips Semiconductors, "TM-1300 Media Processor DATA BOOK"May 2000
[19] Philips Semiconductors, "PNX1300 Series Media Processors DATA BOOK"Feb.2002
[20] Jennifer Eyve,Jeff Bier, "The evolution of DSP Processors "IEEE Signal Processing Magazine Mar.2000 Page(s):44-51
[21] 崔之祜，江春等译“数字视频处理”电子工业出版社
[22] 马小虎，张明敏等编“多媒体数据压缩标准及实现”清华大学出版社
[23] Texas Instruments,Inc "TMS320C6x Evaluation Module "1998
[24] Texas Instruments,Inc "TMS320C62x/67x CPU and Instruction Set" 1998
[25] Texas Instruments,Inc "TMS320C62x/67x Programmer's Guide " 1998
[26] Texas Instruments,Inc "TMS320C6000 Optimizing C Compiler " 1998
[27] Texas Instruments,Inc "TMS320C6000 Peripherals" 1999
[28] 钟玉琢，王琪等“基于对象的多媒体数据压缩编码国际标准MPEG-4及其校验模 型”科学出版社
[29] H. Yamauchi, et al., "Architecture and Implementation of a Highly Parallel Single-Chip Video DSP" , vol. 2,no.2,pp207-220, Jun.1992
[30] M.Toyokura, et al., "A Video DSP with a Macroblock-Level-Pipeline and a SIMD Type Vector-Pipeline Architecture for MPEG-2 CODEC ", IEEE Journal of solid-State Circuits, vol.29 12, pp. 1474-1481, Dec. 1994
[31] Simar, R., Jr, "Codevelopment of the TMS320C6X VelociTI architecture and compiler", Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 3145-3148, vol.5, 1998
[32] 龚惠民， “视频解码系统设计”浙江大学硕士学位论文，2002
[33] Bryan,"Video Compression and VLSI"IEEE 1993 Custom Integrated Circuits Comference
[34] Ycong Kong Lai et al."A Novel Video Signal Processor with Programmable Data Arrangement and Efficient Memory Configuration "IEEE, 1996
[35] T.Akiyama,H.Aono et al. "MPEG-2 Video Codec using Image Compression DSP "IEEE 1994,Page(s): 150-151
[36] "VLIW Architectures for Media Processing" IEEE Signal Processing Magazine .Mar.1998 Page(s):16-19
[37] Sang Joon Nam,Young-Su Kwon, "DIVA:DUAL-ISSUE VLIW ARCHITECTURE WITH MEDIA INSTRUCTIONS FOR IMAGE PROCESSING "IEEE Transactions on Consumer Electronics.Vol.45． No. 1 .Feb. 1999 Page(s): 192-202
[38] 邱钢等“运用定点DSP实现MPEG-4标准中DCT系数快速量化的方法”电子技术应用 2002年第二期Page(s)：73-74
[39] 王栋，张兆杨等“基于TMS320C6000 DSP的视频解码器设计及其硬件实现方案”电 子技术应用2002年第二期Page(s)：78-80
[40] 焦晓等“基于DSP的实时MPEG-4编码的软件优化设计”电子技术应用2002年第六 期Page(s)：22-24
[41] 郑方译“IDSP体系结构在提高实时信号处理方面的作用”电子产品世界1998年11 月
[42] Masatoshi Matssuo,Hitoshi Fujimoto et al. "A Programmable Video Codec System for Low-Bit-Rate Communication" IEEE Transactions on Consumer Electronics Page(s):903-910 1997
[43] 曹锦薇“两种最新的运动矢量搜索算法”北京广播学院学报2000-2 Page(s)：33-38
[44] 杜诚，何芸等“新的低码率视频编码快速半像素搜索算法”清华大学学报2001年第 41卷第一期
[45] 王维东，姚庆栋“亚像素运动估值快速算法”信号处理2002年2月第18卷第一期
[46] 刘海峰，郭宝龙等“用于块匹配运动估值的正方形-菱形搜索算法”计算机学报2002 年7月第25卷第七期
[47] H.Lee,K.Nguyen-phi et al. "Software-Only Real-Time MPEG-2 Video Encoding on The C62x VLIW Processor"
[48] Yuen-Wen Lee, Faouzi Kossentini, Rabab Ward and Mark Smith, "Towards MPEG4: An ImprovedH.263-based video coder," in Signal Processing Image Communication, Oct. 1997．
[49] Thomas Sikora, "MPEG Digital Video-Coding Standards," IEEE Signal Processing Magazine, Sept 1997．