基于8051IP核SoC平台的研究与设计
|
摘要
片上系统(System on Chip，SoC)技术是21世纪集成电路发展的重要方向。本论文来源于导师的教育厅重点科研项目“基于嵌入式SoC智能信息家电集成电路的研究与设计”，主要开展了关于SoC软核的研究与设计，设计了一个基于8051 IP核的SoC系统平台。该系统平台应用8051 IP软核为微控制器，选择易于与MCU连接的Wishbone总线作为系统总线。通过外部RAM的访问时序以模拟Wishbone总线的时序，实现了Wishbone总线与8051的桥接。外扩了一个通用的I／O口(P4端口)，设计了家用电器常用的三个IP软核SPI、I~2C和PWM控制器，增强了8051 IP控制器的功能，成功搭建了家用电器的控制器SoC开发平台。在此基础上，实现了一个无线数据采集系统。
本平台应用QuartusⅡEDA集成开发工具进行设计，用MENTOR公司的ModelsimSE 6.2b仿真软件，对各个软核进行了较完整的测试仿真。使用Synplify Pro 8.1进行综合，得到了符合要求的电路和门级网表。以Altera的CycloneⅡ组成的DE2实验板为验证平台，采用I~2C总线接口的存储器AT24C64芯片和SPI总线接口的无线模块PTR8000，搭建了无线数据采集测试系统。经测试，各个模块运行正常，各项指标满足系统的需要，达到了设计要求。设计的无线数据采集系统工作正常。
该系统采用自顶向下("Top-Down")的设计方法和自底向上("Botom-Up")的测试方法，采用硬件描述语言进行了RTL级的描述，完成了SPI、I~2C、PWM软核的前端设计。
The technology of SoC (System on a Chip) has been a important direction of IC design in21st century. The paper come from mentor's education department project "Research andDesign IC of the intelligent Information Appliance based on embedded SoC", and mainlystudy and design the SoC soft cores, and design a SoC platform based on 8051 IP. Theplatform verifies the 8051 IP and selects the Wishbone as the interconnection bus between IPcores and MCU. By accessing to the external RAM, it has realized the bridged interfacebetween 8051 and Wishbone by simulation its timing. Meanwhile, expand a external generalI/O port (P4). Design the common interfaces in household electric appliance, SPI, I~2C, PWM,and enhance the performance of 8051 IP. A SoC platform is created successfully, and awireless data acquisition system is built based on this platform.
The platform is developed based on the QuartusⅡIntegrating Development Environment,adopt Modelsim 6.2b of MENTOR to simulate the soft cores. The electronic circuit andnetlists requested is obtained by the synthesis tool, Synplify pro 8.1. On the Altera's CycloneⅡDE2 development board, it expanded AT24C64 chip and PTR8000, and build a testplatform. Through verification, the cores work well and meet the command of system. Thewireless data acquisition system works well, too.
The design of system adopts the means of Top-to-Down in front-end design andDown-to-Top in test, and RTL-level code is designed in HDL. The front-end design of I~2C,SPI and PWM soft cores has been completed.
本平台应用QuartusⅡEDA集成开发工具进行设计，用MENTOR公司的ModelsimSE 6.2b仿真软件，对各个软核进行了较完整的测试仿真。使用Synplify Pro 8.1进行综合，得到了符合要求的电路和门级网表。以Altera的CycloneⅡ组成的DE2实验板为验证平台，采用I~2C总线接口的存储器AT24C64芯片和SPI总线接口的无线模块PTR8000，搭建了无线数据采集测试系统。经测试，各个模块运行正常，各项指标满足系统的需要，达到了设计要求。设计的无线数据采集系统工作正常。
该系统采用自顶向下("Top-Down")的设计方法和自底向上("Botom-Up")的测试方法，采用硬件描述语言进行了RTL级的描述，完成了SPI、I~2C、PWM软核的前端设计。
The technology of SoC (System on a Chip) has been a important direction of IC design in21st century. The paper come from mentor's education department project "Research andDesign IC of the intelligent Information Appliance based on embedded SoC", and mainlystudy and design the SoC soft cores, and design a SoC platform based on 8051 IP. Theplatform verifies the 8051 IP and selects the Wishbone as the interconnection bus between IPcores and MCU. By accessing to the external RAM, it has realized the bridged interfacebetween 8051 and Wishbone by simulation its timing. Meanwhile, expand a external generalI/O port (P4). Design the common interfaces in household electric appliance, SPI, I~2C, PWM,and enhance the performance of 8051 IP. A SoC platform is created successfully, and awireless data acquisition system is built based on this platform.
The platform is developed based on the QuartusⅡIntegrating Development Environment,adopt Modelsim 6.2b of MENTOR to simulate the soft cores. The electronic circuit andnetlists requested is obtained by the synthesis tool, Synplify pro 8.1. On the Altera's CycloneⅡDE2 development board, it expanded AT24C64 chip and PTR8000, and build a testplatform. Through verification, the cores work well and meet the command of system. Thewireless data acquisition system works well, too.
The design of system adopts the means of Top-to-Down in front-end design andDown-to-Top in test, and RTL-level code is designed in HDL. The front-end design of I~2C,SPI and PWM soft cores has been completed.
引文
[1] (美)JAN M. RABAEY, ANANTHA CHANDRAKASAN, BORIVOJE NIKOLIC著，周润德译，数字集成电路—电路、系统与设计(第二版)[M]北京：电子工业出版社，2004．10：1-10
[2] (美)JOHN P. UYEMUR著，周润德译，超大规模集成电路与系统导论[M] 北京：电子工业出版社，2004．1：3-8
[3] 李瑞 张春元 罗莉等，三种常用SoC片上总线的分析与比较[J]，单片机与嵌入式系统应用，2004．2：1
[4] MICHAEL D．CILETTI著，张雅绮 李锵译，VERILOG HDL高级数字设计[M]，北京：电子工业出版社，2005：124-226
[5] 夏宇闻著，VERILOG数字系统设计教程[M]，北京：北京航空航天大学出版社，2004：1-9
[6] 任艳颖等著，IC设计基础[M]，西安：西安电子出版社，2003：60-73
[7] R K Gupta, Y Zorian. Introducing core-base system design[J]. IEEE Design & Test of Computers, 1997, 14(4): 15-25
[8] Virtual Socket Interface Architecture Document[EB/OL]. http://www.vsi.org
[9] 沈戈等译，片上系统(第3版)[M]，北京：电子工业出版社 2004．5：124-144
[10] 章立生，SoC芯片设计方法及标准化[J]．计算机研究与发展，2002，(1)：1-6
[11] 黄晓林，蒋伟荣，SoC与IP复用及其发展策略[J]，现代电子技术，2003，(16)：1-4
[12] A B Kahng et al. Watermarking techniques for intellectual property protection[C]. In: Proc of the 35th Design Automation Conf. San Francisco, California, 1998: 776-781
[13] ASIC Council Homepage[EB/OL]. http://www.si2.org/asic
[14] Virtual Socket Interface Alliance Homepage[EB/OL]. http://www.vsi.org
[15] L Semeria, A Ghosh. Methodology for hardware/software co-verification C/C++[C]. In: Proc of the Asia South2PacificDesign Automation Conf. Yokohama, Japan, 2000: 405-408
[16] C Lennard. Enabling VC exchange through system-level VC standards[C]. In: Proc of Forum on Design Language. Lyon, France, 1999: 641-650
[17] Christopher K Lennard et al. Standard for system level design: Practical, reality or solution in search of a question?[C]. In: Proc of the Design, Automation and Test in Europe Conf. Paris, France, 2000: 576-583
[18] K Kucukcakar. Analysis of merging core-based design life cycle[C]. In: ICCAD'98. San Jose, California, 1998
[19] VSI Alliance. VSIA Architecture Document, Version 1.0. [EB/OL].1997, http://www.vsi.org/resources/techdocs/vsi-or.pdf
[20] Jay Abraham, Sanjay Curiwala. Flexible model for delay and power[EB/OL]. 1999. http: // www.si2.org/ola/paper/olapaper5.pdf
[21] G Arnout. SystemC standard[C]. In: Proc of the Asia South-Pacific Design Automation Conf. Yokohama, Japan, 2000: 573-577
[22] J Raw son et al. Interface base design[C]. In: Proc of the 34th Design Automation Conf. Anaheim, California, 1997:178-183
[23] P Flake, S Davidmann. Superlog, a unified design language for system-on-chip[C]. In: Proc of the Asia South-Pacific Design Automation Conf. Yokohama, Japan, 2000: 583 -586
[24] L Lavagno, E Sentovich. ECL:A specification environment for system-level design [C].In: Proc of the 36th Design Automation Conf. New Orleans, LA, 1999:511-516
[25] C Liao, S Tjiang, R Gupta. An efficient implementation of reactivity for modeling hardware in the scenic design environment [C]. In: Proc of the 34th Design Automation Conf. Anaheim, California, 1997,70-75
[26] System Level Design Language Homepage[EB/OL]. http: //www.inmet.com/SLDL/
[27] W Wolf. Hardware/software co-design of embedded systems. Proceedings of the IEEE[C], 1994, 82(7): 967-989
[28] Yanbing Li et al. Hardware/software co-design of embedded reconfigurable architectures [C]. In: Proc of Design Automation Conf. Los Angeles, 2000: 507-512
[29] R K Gupta, G De Micheli. A co-synthesis approach to embedded system design automation[J]. Design Automation for Embedded Systems, 1996,1(1-2): 69-120
[30] Carry Ussery. Configurable processing platforms: Redefining SoC[C]. In: CoolChip2000. Tokyo, 2000
[31] Russell Priebe, Cary Ussery. A configurable platform for advanced system-on-a-chip applications[C]. In: ICSPAT2000. Dallas, TX, USA, 2000
[32] Marc Tremblay, Jeffrey Chan, Shailender Chaudhry et al. The MAJC architecture: A synthesis of parallelism and scalability. [C]IEEE Micro, 2000, 20(6): 12-25
[33] Carry Ussery. Configurable platform, the ASIC revolution[C].In: DesignCon2000. Santa Clara, CA , USA , 2000
[34] An overview of the ZSP architecture [A]. LSI Logic Corp. 2000:3-7
[35] Oregano, mc8051 overview [EB/OL]. http://oregano.at/ip/mc8051/ mc8051_overview.pdf, 2005
[36] ARM, AMBA Specification Overview[S], 2001
[37] IBM, The CoreCormect Bus Architecture[S], 1999
[38] SILICORE, WISHBONE, Revision B.3 Specification[S], 2002.9: 30-69
[39] 鄢永明等，基于8051软核的SOPC系统设计与实现[J]，电子技术应用，2005，(12)：72-75
[40] Motorola, SPI Bus pecification [EB/OL].http: www.freescale.com/files/microcontrollers /doc/ref_manual/S12SP/V2.pdf, 2002: 9-33
[41] Philips , The I~2C-bus specification(V2.1) [EB/OL]. http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf, 2000: 6-26
[42] Altera, Cyclone Ⅱ[EB/OL], http://www.altera.com.cn/products/deviees/cyelone2/overview/cy2-overview.html
[43] Altera, Cyclone Ⅱ configuration[-EB/OL].http://www.altera.com.cn/products/devices/config/cfg-index.html
[44] Modelsim, introduction to modelsim [EB/OL].http://www.model.com/products/products_se.asp
[45] Synplicity, product [EB/OL], http://www.synplicity.com/products/synplifypro/
[46] Altera, Quartus Ⅱ function[EB/OL], http://www.altera.com.cn/products/software/products/quartus2/whats_new/qts-whatsnew.jsp
[47] Terasic, DE2 board Document Version 1.2[EB/OL], http://www.terasic.com.tw oct.02, 2005: 1-49
[48] 迅通科技，PTR8000 datasheet [EB/OL], http://www.freqchina.com/PTR8000.htm
[2] (美)JOHN P. UYEMUR著，周润德译，超大规模集成电路与系统导论[M] 北京：电子工业出版社，2004．1：3-8
[3] 李瑞 张春元 罗莉等，三种常用SoC片上总线的分析与比较[J]，单片机与嵌入式系统应用，2004．2：1
[4] MICHAEL D．CILETTI著，张雅绮 李锵译，VERILOG HDL高级数字设计[M]，北京：电子工业出版社，2005：124-226
[5] 夏宇闻著，VERILOG数字系统设计教程[M]，北京：北京航空航天大学出版社，2004：1-9
[6] 任艳颖等著，IC设计基础[M]，西安：西安电子出版社，2003：60-73
[7] R K Gupta, Y Zorian. Introducing core-base system design[J]. IEEE Design & Test of Computers, 1997, 14(4): 15-25
[8] Virtual Socket Interface Architecture Document[EB/OL]. http://www.vsi.org
[9] 沈戈等译，片上系统(第3版)[M]，北京：电子工业出版社 2004．5：124-144
[10] 章立生，SoC芯片设计方法及标准化[J]．计算机研究与发展，2002，(1)：1-6
[11] 黄晓林，蒋伟荣，SoC与IP复用及其发展策略[J]，现代电子技术，2003，(16)：1-4
[12] A B Kahng et al. Watermarking techniques for intellectual property protection[C]. In: Proc of the 35th Design Automation Conf. San Francisco, California, 1998: 776-781
[13] ASIC Council Homepage[EB/OL]. http://www.si2.org/asic
[14] Virtual Socket Interface Alliance Homepage[EB/OL]. http://www.vsi.org
[15] L Semeria, A Ghosh. Methodology for hardware/software co-verification C/C++[C]. In: Proc of the Asia South2PacificDesign Automation Conf. Yokohama, Japan, 2000: 405-408
[16] C Lennard. Enabling VC exchange through system-level VC standards[C]. In: Proc of Forum on Design Language. Lyon, France, 1999: 641-650
[17] Christopher K Lennard et al. Standard for system level design: Practical, reality or solution in search of a question?[C]. In: Proc of the Design, Automation and Test in Europe Conf. Paris, France, 2000: 576-583
[18] K Kucukcakar. Analysis of merging core-based design life cycle[C]. In: ICCAD'98. San Jose, California, 1998
[19] VSI Alliance. VSIA Architecture Document, Version 1.0. [EB/OL].1997, http://www.vsi.org/resources/techdocs/vsi-or.pdf
[20] Jay Abraham, Sanjay Curiwala. Flexible model for delay and power[EB/OL]. 1999. http: // www.si2.org/ola/paper/olapaper5.pdf
[21] G Arnout. SystemC standard[C]. In: Proc of the Asia South-Pacific Design Automation Conf. Yokohama, Japan, 2000: 573-577
[22] J Raw son et al. Interface base design[C]. In: Proc of the 34th Design Automation Conf. Anaheim, California, 1997:178-183
[23] P Flake, S Davidmann. Superlog, a unified design language for system-on-chip[C]. In: Proc of the Asia South-Pacific Design Automation Conf. Yokohama, Japan, 2000: 583 -586
[24] L Lavagno, E Sentovich. ECL:A specification environment for system-level design [C].In: Proc of the 36th Design Automation Conf. New Orleans, LA, 1999:511-516
[25] C Liao, S Tjiang, R Gupta. An efficient implementation of reactivity for modeling hardware in the scenic design environment [C]. In: Proc of the 34th Design Automation Conf. Anaheim, California, 1997,70-75
[26] System Level Design Language Homepage[EB/OL]. http: //www.inmet.com/SLDL/
[27] W Wolf. Hardware/software co-design of embedded systems. Proceedings of the IEEE[C], 1994, 82(7): 967-989
[28] Yanbing Li et al. Hardware/software co-design of embedded reconfigurable architectures [C]. In: Proc of Design Automation Conf. Los Angeles, 2000: 507-512
[29] R K Gupta, G De Micheli. A co-synthesis approach to embedded system design automation[J]. Design Automation for Embedded Systems, 1996,1(1-2): 69-120
[30] Carry Ussery. Configurable processing platforms: Redefining SoC[C]. In: CoolChip2000. Tokyo, 2000
[31] Russell Priebe, Cary Ussery. A configurable platform for advanced system-on-a-chip applications[C]. In: ICSPAT2000. Dallas, TX, USA, 2000
[32] Marc Tremblay, Jeffrey Chan, Shailender Chaudhry et al. The MAJC architecture: A synthesis of parallelism and scalability. [C]IEEE Micro, 2000, 20(6): 12-25
[33] Carry Ussery. Configurable platform, the ASIC revolution[C].In: DesignCon2000. Santa Clara, CA , USA , 2000
[34] An overview of the ZSP architecture [A]. LSI Logic Corp. 2000:3-7
[35] Oregano, mc8051 overview [EB/OL]. http://oregano.at/ip/mc8051/ mc8051_overview.pdf, 2005
[36] ARM, AMBA Specification Overview[S], 2001
[37] IBM, The CoreCormect Bus Architecture[S], 1999
[38] SILICORE, WISHBONE, Revision B.3 Specification[S], 2002.9: 30-69
[39] 鄢永明等，基于8051软核的SOPC系统设计与实现[J]，电子技术应用，2005，(12)：72-75
[40] Motorola, SPI Bus pecification [EB/OL].http: www.freescale.com/files/microcontrollers /doc/ref_manual/S12SP/V2.pdf, 2002: 9-33
[41] Philips , The I~2C-bus specification(V2.1) [EB/OL]. http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf, 2000: 6-26
[42] Altera, Cyclone Ⅱ[EB/OL], http://www.altera.com.cn/products/deviees/cyelone2/overview/cy2-overview.html
[43] Altera, Cyclone Ⅱ configuration[-EB/OL].http://www.altera.com.cn/products/devices/config/cfg-index.html
[44] Modelsim, introduction to modelsim [EB/OL].http://www.model.com/products/products_se.asp
[45] Synplicity, product [EB/OL], http://www.synplicity.com/products/synplifypro/
[46] Altera, Quartus Ⅱ function[EB/OL], http://www.altera.com.cn/products/software/products/quartus2/whats_new/qts-whatsnew.jsp
[47] Terasic, DE2 board Document Version 1.2[EB/OL], http://www.terasic.com.tw oct.02, 2005: 1-49
[48] 迅通科技，PTR8000 datasheet [EB/OL], http://www.freqchina.com/PTR8000.htm