基于AMR标准的语音编码VLSI设计
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摘要
随着现代无线多媒体通信的发展,以及当前通信系统有限的带宽资源,发展高质量和低码率的的语音编码器成为很迫切的课题。AMR(自适应多速率)语音编码器由于其低码率和高质量,使之在通信和多媒体领域得到广泛应用,同时由于集成电路设计方法学和工具软件的不断发展,低成本、低功耗、高性能的AMR语音编码器已经完全可以实现。
     对AMR编码器的原理作了深入的研究,并对算法的C实现做了详细的模拟和分析。根据模拟得到的数据,针对AMR语音编码标准的算法特点,提出了一种“DSP软核+ASIC加速器”的体系结构。在设计好体系结构后,对编码器算法进行具体的硬件建模。首先,优化DSP软核,基于该DSP软核对AMR编码算法进行了改进;接着将AMR编码器用全汇编实现和优化,对汇编代码进行测试并给出了结果数据;然后根据汇编测试数据,详细地分析和设计了ASIC加速器;最后对整个设计进行了详细地验证和分析。采用了FPGA原型验证,在功能方面保证了设计的功能正确性。同时对设计中的ASIC加速器中的模块采用了复用设计,使得本设计方案对G.72x系列语音编码算法具有通用性和可移植性。
     设计在HJTC0.18μm工艺库上实现,工作电压为1.8V,最高工作频率达110MHz。当工作在20MHz频率的时候,就可以满足语音编码实时性20ms的延时要求,此时设计功耗仅有20mW,设计面积只有15万门(包括片上存储器),最后设计进行了MPW投片。
With the development of wireless communication systems and the limit of communication systems bandwidth resource, research and design of speech coder with high quality and low bits rate imminently. AMR(adaptive mult rate)speech coder using widely in communication and mult-media field for high quality and low bits rate. With rapid and successful development in integrated circurits design method and software, design a AMR speech coder IP practically.
     In this paper, research AMR speech coder principle deeply, then simulate and analyze the c code in detail. Then, with the data of simulation, presents a structure of“DSP soft core + ASIC accelerator”based on AMR speech coding algorithm. After that , hardware model should be implemented in detail. According the new structure, optimize the DSP core and improved AMR speech coding algorithm. After that, write assembler code and optimize the assembler code. Once the assembler design is finished, test and simulate the code, the record the data of testing and simulation. ASIC accelerator could be design using these result data. This design was implemented on FPGA device, and the experimental results indicate that the structure is feasible. Meanwhile , as the design in this structure can also be applied in many other speech coding algorithms like G.72X serial speech coder.
     This design implementes on the HJTC0.18μm process, voltage is 1.8V. After synthesis, the design can work utmost at 110 MHz. While working at 20 MHz, the design can meet the 20ms limit of timing, and only have 20mW power and 150 K gates chip area.(include on chip memory).The design will be taped out in last.
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