铁电场效应晶体管的保持性能与负电容效应研究
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摘要
近些年来，由铁电场效应晶体管构成存储单元的铁电存储器，由于具有结构简单、非破坏性读出、不易挥发、功耗低、可多次反复读写、可高速大密度存取、良好的抗辐射性能以及与集成电路工艺兼容等优点，而被公认为下一代最具潜力的存储器之一，得到了人们的广泛关注。但是，由于铁电场效应晶体管的保持性能比较差，目前仍然没有实用化；其次，一旦铁电场效应晶体管用作铁电存储器得到实用化，铁电存储器芯片又如何克服由于集成度不断提高而带来的功耗与稳定性问题。基于此，本论文先从铁电材料及其存储器的研究进展进行综述，包括铁电体及铁电薄膜材料的分类与物理特性、铁电存储器的发展历史、研究现状以及目前存在的主要问题，然后在此基础上我们通过理论建模与数值分析相结合的方法，重点研究了铁电薄膜电容的保持性能与铁电场效应晶体管的负电容效应。具体内容和结论如下：
1、考虑金属电极-铁电界面层效应，我们对金属-铁电-绝缘层-半导体(MFIS)结构电容的退极化场进行了理论推导，结合娄氏的极化保持性能模型，对影响MFIS结构电容保持性能的一些物理参数进行了探讨。结果表明：选择薄膜厚度相对厚一点、介电常数比较高的铁电材料有利于提高MFIS结构电容的极化保持时间，良好的电极-铁电界面质量也有利于提高MFIS结构电容的保持性能。同时，适当地提高硅衬底掺杂浓度可以通过减小退极化场来改善MFIS结构电容的保持性能。该研究结果对提高MFIS结构电容和场效应晶体管的保持性能具有重要的指导意义。
2、基于Landau–Ginzburg–Devonshire理论、泊松方程、以及电流连续性方程，我们考虑铁电薄膜负电容效应，针对双栅铁电场效应晶体管的表面势和漏电流特性进行了研究。研究结果表明：选择合适的铁电薄膜厚度，在室温下可实现半导体硅表面势放大进而可以获得小的亚阈值摆幅(S=34<60mV/dec)。与传统的正电容铁电场效应晶体管相比，若保持开态电流在600μA/μm，它可以减小260mV的驱动电压。这对低电压、低功耗MOS场效应晶体管的设计具有非常重要的指导意义。
3、在上一章的基础上，我们针对双栅铁电场效应晶体管发展了一个界面层模型，考虑金属电极与铁电层的界面效应，对负电容双栅铁电场效应晶体管的表面势和亚阈值特性进行了研究。研究结果表明：处于负电容状态下的铁电场效应晶体管，其硅表面势放大效应与亚阈值摆幅明显地受金属电极-铁电界面层影响，随着金属电极-铁电界面层厚度变厚，硅表面势放大效应变弱，亚阈值摆幅变大(亚阈值斜率变小)。该研究结果对低功耗新型铁电场效应晶体管的设计具有很好的指导意义。
4、由于铁电薄膜负电容明显地依赖于温度(T)，基于此，在280K~360K的温度范围，我们对负电容铁电场效应晶体管的电学性能从理论上进行了研究。研究结果表明：对于一定厚度铁电薄膜的场效应晶体管，硅表面势的放大效应可以通过温度来调节；存在一个最佳的温度使得铁电薄膜负电容效应最强，硅表面势放大效应最明显。超过这个最佳温度，晶体管的转移特性和输出特性随温度的升高(或者降低)逐渐变差，原因是当温度达到最佳值时，铁电薄膜负电容效应最明显，温度若再升高(或者降低)，铁电薄膜负电容效应逐渐减弱直至消失。该研究成果抓住了环境温度这一关键因素，对低功耗场效应晶体管在特定环境温度下的设计与应用具有重要的指导意义。
5、考虑铁电薄膜的负电容效应，我们针对环栅新型铁电场效应晶体管提出了一个理论模型，并运用该模型对其电学性能包括电容-电压(C-V)、电流-电压(I-V)进行了研究。研究结果表明：负电容环栅铁电场效应晶体管表现出比传统正电容环栅场效应晶体管优越的一些电学性能，比如栅电极能更好地控制沟道静电势、小的亚阈值摆幅(<60mV/dec)、以及大的输出电流等。该成果能很好地指导高速转换、低功耗环栅铁电场效应晶体管的设计。
In recent years, ferroelectric gate field-effect transistor (FeFET), as one type offerroelectric random access memory (FeRAM), is currently regarded as one of the mostpotential next generation memory with clear advantages such as its simple structure,nondestructive read-out operation, non-volatility, low power dissipation, high endurance, highspeed writing, high density, irradiation hardness, and compatible with the process ofintegrated circuit (IC). However, FeFETs have not been put into practical application as aresult of its relatively short retention time. Additionally, how to reduce the powerconsumption and improve the stability of the system on chip will prove to be a problem forpeople when the FeFETs are commonly used. In order to solve these two problems, firstly, inthis thesis, the advences of the ferroelectric materials and ferroelectric memory are reviewedin the introduction, including the classification and physical characteristics of the ferroelectricthin films, and the development history, current status and existing problems of theferroelectric memory. Then, on the basis of introduction, the retention propery of ferroelectricthin film capacitor and the negative capacitance effect of FeFET are mainly investigated bycombining the theoretical modeling and numerical analysis. The main contents andconclusions are as follows:
1. Depolarization field in metal-ferroelectric-insulator-semiconductor (MFIS) capacitorswith a ferroelectric-electrode interface layer was derived theoretically in this work. Thepolarization relaxation characteristics were investigated in details based on Lou’s polarizationretention model. It is found that the retention time of MFIS capacitor can be improvedeffectively by using relatively high dielectric constant ferroelectric thin film and relativelythick ferroelectric thin film. Additionally, a good ferroelectric-electrode interface layer andrelatively high doping concentration of semiconductor silicon can help to improve theretention time of MFIS capacitor. The results may provide some insights into the design andthe retention property improvement of MFIS-FET as nonvolatile memory.
2. Based on the Landau-Ginzburg-Devonshire theory, the Poisson’s equation, and thecurrent continuity equation, the surface potential and drain current of double-gatemetal-ferroelectric-insulator-semiconductor (MFIS) feld-effect transistor were investigatedby using the ferroelectric negative capacitance (NC). The derived results demonstrated thatthe up-converted semiconductor surface potential and low subthreshold swing S=34(<60mV/dec) can be realized with appropriate thicknesses of ferroelectric thin flm and insulatorlayer at room temperature. What’s more, a reduction of gate voltage about260mV can bereached if the ON-state current is fxed to600μA/μm. It is expected that the derived results can offer useful guidelines for the application of low power dissipation in ongoing scaling ofFETs.
3. Based on chapter3, an interface layer model was proposed for the double-gateferroelectric feld-effect transistor (FeFET). The surface potential and subthresholdcharacteristics in negative capacitance (NC) double-gate ferroelectric field-effect transistorwere investigated by considering the metal-ferroelectric interface layer. The derived resultsindicates that the negative capacitance regime which allows for amplified surface potentialand steeper subthreshold characteristics were significantly affected by the interface layer. Thisimposes a severe limit to the step-up conversion capability and steeper subthreshold (<60mV/dec) obtainable in the device. These results may provide some insight into the design andperformance improvement for the low power dissipation FeFETs.
4. Based on the temperature dependence ferroelectric negative capacitance, the electricalproperties of negative capacitance (NC) ferroelectric feld-effect transistors (FeFETs) weretheoretically investigated in the temperature range from280to360K. The derived resultsindicate that for a fxed thickness of ferroelectric thin flm the amplifcation of surfacepotential can be tuned by temperature. The transfer and output characteristics degrade withincreasing temperature due to the gradual loss of ferroelectric NC effect. It is expected thatthe derived results may provide some insight into the design and performance improvementfor the low power dissipation applications of FeFETs.
5. The electrical properties of surrounding-gate (SG) metal-ferroelectric-semiconductor(MFS) FETs were theoretically investigated by considering the ferroelectric negativecapacitance (NC) effect. The derived results demonstrated that the NC-SG-MFS-FET displayssuperior electrical properties compared with that of the traditional SG-MIS-FET, in terms ofbetter electrostatic control of the gate electrode over the channel, smaller subthreshold swing(S <60mV/dec), and bigger value of ION. It is expected that this investigation may providesome insight into the design and performance improvement for the fast switching and lowpower dissipation applications of ferroelectric FETs.
1、考虑金属电极-铁电界面层效应，我们对金属-铁电-绝缘层-半导体(MFIS)结构电容的退极化场进行了理论推导，结合娄氏的极化保持性能模型，对影响MFIS结构电容保持性能的一些物理参数进行了探讨。结果表明：选择薄膜厚度相对厚一点、介电常数比较高的铁电材料有利于提高MFIS结构电容的极化保持时间，良好的电极-铁电界面质量也有利于提高MFIS结构电容的保持性能。同时，适当地提高硅衬底掺杂浓度可以通过减小退极化场来改善MFIS结构电容的保持性能。该研究结果对提高MFIS结构电容和场效应晶体管的保持性能具有重要的指导意义。
2、基于Landau–Ginzburg–Devonshire理论、泊松方程、以及电流连续性方程，我们考虑铁电薄膜负电容效应，针对双栅铁电场效应晶体管的表面势和漏电流特性进行了研究。研究结果表明：选择合适的铁电薄膜厚度，在室温下可实现半导体硅表面势放大进而可以获得小的亚阈值摆幅(S=34<60mV/dec)。与传统的正电容铁电场效应晶体管相比，若保持开态电流在600μA/μm，它可以减小260mV的驱动电压。这对低电压、低功耗MOS场效应晶体管的设计具有非常重要的指导意义。
3、在上一章的基础上，我们针对双栅铁电场效应晶体管发展了一个界面层模型，考虑金属电极与铁电层的界面效应，对负电容双栅铁电场效应晶体管的表面势和亚阈值特性进行了研究。研究结果表明：处于负电容状态下的铁电场效应晶体管，其硅表面势放大效应与亚阈值摆幅明显地受金属电极-铁电界面层影响，随着金属电极-铁电界面层厚度变厚，硅表面势放大效应变弱，亚阈值摆幅变大(亚阈值斜率变小)。该研究结果对低功耗新型铁电场效应晶体管的设计具有很好的指导意义。
4、由于铁电薄膜负电容明显地依赖于温度(T)，基于此，在280K~360K的温度范围，我们对负电容铁电场效应晶体管的电学性能从理论上进行了研究。研究结果表明：对于一定厚度铁电薄膜的场效应晶体管，硅表面势的放大效应可以通过温度来调节；存在一个最佳的温度使得铁电薄膜负电容效应最强，硅表面势放大效应最明显。超过这个最佳温度，晶体管的转移特性和输出特性随温度的升高(或者降低)逐渐变差，原因是当温度达到最佳值时，铁电薄膜负电容效应最明显，温度若再升高(或者降低)，铁电薄膜负电容效应逐渐减弱直至消失。该研究成果抓住了环境温度这一关键因素，对低功耗场效应晶体管在特定环境温度下的设计与应用具有重要的指导意义。
5、考虑铁电薄膜的负电容效应，我们针对环栅新型铁电场效应晶体管提出了一个理论模型，并运用该模型对其电学性能包括电容-电压(C-V)、电流-电压(I-V)进行了研究。研究结果表明：负电容环栅铁电场效应晶体管表现出比传统正电容环栅场效应晶体管优越的一些电学性能，比如栅电极能更好地控制沟道静电势、小的亚阈值摆幅(<60mV/dec)、以及大的输出电流等。该成果能很好地指导高速转换、低功耗环栅铁电场效应晶体管的设计。
In recent years, ferroelectric gate field-effect transistor (FeFET), as one type offerroelectric random access memory (FeRAM), is currently regarded as one of the mostpotential next generation memory with clear advantages such as its simple structure,nondestructive read-out operation, non-volatility, low power dissipation, high endurance, highspeed writing, high density, irradiation hardness, and compatible with the process ofintegrated circuit (IC). However, FeFETs have not been put into practical application as aresult of its relatively short retention time. Additionally, how to reduce the powerconsumption and improve the stability of the system on chip will prove to be a problem forpeople when the FeFETs are commonly used. In order to solve these two problems, firstly, inthis thesis, the advences of the ferroelectric materials and ferroelectric memory are reviewedin the introduction, including the classification and physical characteristics of the ferroelectricthin films, and the development history, current status and existing problems of theferroelectric memory. Then, on the basis of introduction, the retention propery of ferroelectricthin film capacitor and the negative capacitance effect of FeFET are mainly investigated bycombining the theoretical modeling and numerical analysis. The main contents andconclusions are as follows:
1. Depolarization field in metal-ferroelectric-insulator-semiconductor (MFIS) capacitorswith a ferroelectric-electrode interface layer was derived theoretically in this work. Thepolarization relaxation characteristics were investigated in details based on Lou’s polarizationretention model. It is found that the retention time of MFIS capacitor can be improvedeffectively by using relatively high dielectric constant ferroelectric thin film and relativelythick ferroelectric thin film. Additionally, a good ferroelectric-electrode interface layer andrelatively high doping concentration of semiconductor silicon can help to improve theretention time of MFIS capacitor. The results may provide some insights into the design andthe retention property improvement of MFIS-FET as nonvolatile memory.
2. Based on the Landau-Ginzburg-Devonshire theory, the Poisson’s equation, and thecurrent continuity equation, the surface potential and drain current of double-gatemetal-ferroelectric-insulator-semiconductor (MFIS) feld-effect transistor were investigatedby using the ferroelectric negative capacitance (NC). The derived results demonstrated thatthe up-converted semiconductor surface potential and low subthreshold swing S=34(<60mV/dec) can be realized with appropriate thicknesses of ferroelectric thin flm and insulatorlayer at room temperature. What’s more, a reduction of gate voltage about260mV can bereached if the ON-state current is fxed to600μA/μm. It is expected that the derived results can offer useful guidelines for the application of low power dissipation in ongoing scaling ofFETs.
3. Based on chapter3, an interface layer model was proposed for the double-gateferroelectric feld-effect transistor (FeFET). The surface potential and subthresholdcharacteristics in negative capacitance (NC) double-gate ferroelectric field-effect transistorwere investigated by considering the metal-ferroelectric interface layer. The derived resultsindicates that the negative capacitance regime which allows for amplified surface potentialand steeper subthreshold characteristics were significantly affected by the interface layer. Thisimposes a severe limit to the step-up conversion capability and steeper subthreshold (<60mV/dec) obtainable in the device. These results may provide some insight into the design andperformance improvement for the low power dissipation FeFETs.
4. Based on the temperature dependence ferroelectric negative capacitance, the electricalproperties of negative capacitance (NC) ferroelectric feld-effect transistors (FeFETs) weretheoretically investigated in the temperature range from280to360K. The derived resultsindicate that for a fxed thickness of ferroelectric thin flm the amplifcation of surfacepotential can be tuned by temperature. The transfer and output characteristics degrade withincreasing temperature due to the gradual loss of ferroelectric NC effect. It is expected thatthe derived results may provide some insight into the design and performance improvementfor the low power dissipation applications of FeFETs.
5. The electrical properties of surrounding-gate (SG) metal-ferroelectric-semiconductor(MFS) FETs were theoretically investigated by considering the ferroelectric negativecapacitance (NC) effect. The derived results demonstrated that the NC-SG-MFS-FET displayssuperior electrical properties compared with that of the traditional SG-MIS-FET, in terms ofbetter electrostatic control of the gate electrode over the channel, smaller subthreshold swing(S <60mV/dec), and bigger value of ION. It is expected that this investigation may providesome insight into the design and performance improvement for the fast switching and lowpower dissipation applications of ferroelectric FETs.
引文
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