高速串行数据发送器的研究
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摘要
随着社会不断的发展,人们对通信的要求越来越高,信息交换的数量之大和速度之快达到了前所未有的程度。串行通信也越来越多应用在现代数据通信系统中,特别是在下一代的数据通信中串行通信将成为数据通信的主要模式。在前人研究的基础上,本文在以下几个方面对高速数据发送器进行了研究与实践。
第一个方面是系统研究。主要做了以下几个方面的工作:首先,对发送系统进行信号规则分析,比较了差分和单端信号,二进制和多电平编码的优缺点。其次是信道分析,作为数据发送主要的传输信道:印刷电路板和同轴电缆建立信道模型,为信道预均衡提供了理论基础;接下来是对于系统主要性能的评估,对于数据发送器最主要的性能是极限数据率与误码率,这两个性能主要是由片上信号带宽以及信号完整性决定的。最后是根据以上的分析,在信号编码、系统时钟、信道驱动器上对发送器系统进行了分类比较。
第二方面,本文设计了三个高速串行发送器,第一个是1.5Gbps全速时钟发送器,它适用于高速硬盘接口,采用二进制编码、全速时钟、混合型线驱动器结构实现,并且在电路实现过程中对并串转换电路进行了优化设计。第二个电路是1.25Gbps以太网发送器的设计,它采用半速时钟结构,改进了树状结构并串转换电路,优化了整个发送器的功耗。第三个电路是3.125Gbps以太网发送器的设计,发送器采用了多相时钟结构,为了改善抖动特性,设计了占空比调整电路来改善发送系统的时钟特性,采用预均衡线驱动器补偿了信道高频衰减,并且对于发送器的总体功耗进行了优化设计。
本文的最后一章对论文进行了总结,并且展望了以后的工作。
The requirement for large-volume and high-speed communication is increasing day by day. The serial link has been more and more used in modern communication system. And it will be dominant methodology of next generation data communication. On the basis of recent research, this thesis concentrates on bellowed several aspects to do some research of high-speed transmitter.Firstly, it is system research. There are several topics have been mentioned in this thesis. Firstly, signal conversion as an important aspect in data communication has been discussed here. It includes comparisons of differential and single-ended, binary and multilevel. Secondly, signal channel analysis concentrates on the dominant channel materials of data communication, which are PCB and coaxial cable. In this thesis, the channel model and pre-emphasis theory has been built up. Thirdly, as the main performance of transmitter, the maximum data rate and Bit Error Rate (BER) have been analyzed. Base on above several topics, the thesis categorizes transmitter system in signal conversion, system clock method, signaling method.The thesis also describes two designs of high-speed transmitters. The first design is a 1.5Gbps full speed clock transmitter in the application of Serial ATA. It concludes high speed clock generator, improved parallel-to-serial circuit, combined linedriver. The second design is a 1.25Gbps transmitter in the application of Ethernet. It adopts half-rate-clock architecture and improve tree type parallel-to-serial circuit and optimization system power consumption. The third design is a 3.125Gbps multi-clock-phase transmitter in the application of Ethernet. It adopts multi-phase clock generator, a duty-cycle stable circuit to minimize deterministic jitter and pre-emphasis linedriver to compensate attenuation of channel.At the end of thesis, a summary is put forward are mentioned.
第一个方面是系统研究。主要做了以下几个方面的工作:首先,对发送系统进行信号规则分析,比较了差分和单端信号,二进制和多电平编码的优缺点。其次是信道分析,作为数据发送主要的传输信道:印刷电路板和同轴电缆建立信道模型,为信道预均衡提供了理论基础;接下来是对于系统主要性能的评估,对于数据发送器最主要的性能是极限数据率与误码率,这两个性能主要是由片上信号带宽以及信号完整性决定的。最后是根据以上的分析,在信号编码、系统时钟、信道驱动器上对发送器系统进行了分类比较。
第二方面,本文设计了三个高速串行发送器,第一个是1.5Gbps全速时钟发送器,它适用于高速硬盘接口,采用二进制编码、全速时钟、混合型线驱动器结构实现,并且在电路实现过程中对并串转换电路进行了优化设计。第二个电路是1.25Gbps以太网发送器的设计,它采用半速时钟结构,改进了树状结构并串转换电路,优化了整个发送器的功耗。第三个电路是3.125Gbps以太网发送器的设计,发送器采用了多相时钟结构,为了改善抖动特性,设计了占空比调整电路来改善发送系统的时钟特性,采用预均衡线驱动器补偿了信道高频衰减,并且对于发送器的总体功耗进行了优化设计。
本文的最后一章对论文进行了总结,并且展望了以后的工作。
The requirement for large-volume and high-speed communication is increasing day by day. The serial link has been more and more used in modern communication system. And it will be dominant methodology of next generation data communication. On the basis of recent research, this thesis concentrates on bellowed several aspects to do some research of high-speed transmitter.Firstly, it is system research. There are several topics have been mentioned in this thesis. Firstly, signal conversion as an important aspect in data communication has been discussed here. It includes comparisons of differential and single-ended, binary and multilevel. Secondly, signal channel analysis concentrates on the dominant channel materials of data communication, which are PCB and coaxial cable. In this thesis, the channel model and pre-emphasis theory has been built up. Thirdly, as the main performance of transmitter, the maximum data rate and Bit Error Rate (BER) have been analyzed. Base on above several topics, the thesis categorizes transmitter system in signal conversion, system clock method, signaling method.The thesis also describes two designs of high-speed transmitters. The first design is a 1.5Gbps full speed clock transmitter in the application of Serial ATA. It concludes high speed clock generator, improved parallel-to-serial circuit, combined linedriver. The second design is a 1.25Gbps transmitter in the application of Ethernet. It adopts half-rate-clock architecture and improve tree type parallel-to-serial circuit and optimization system power consumption. The third design is a 3.125Gbps multi-clock-phase transmitter in the application of Ethernet. It adopts multi-phase clock generator, a duty-cycle stable circuit to minimize deterministic jitter and pre-emphasis linedriver to compensate attenuation of channel.At the end of thesis, a summary is put forward are mentioned.
引文
[1] M. Galles, et al., "Spider: a high-speed network interconnect," IEEE Micro Jan. Feb. 1997. vol. 17. no. 1, p34-39
[2] J. Kuskin, et al., "The Stanford FLASH Multiprocessor," Proceedings of the 21st International Symposium on Computer Architecture, Chicago, IL, Apr. 1994, pp. 302-13
[3] R. Mooney, et al., "A 900 Mb/s bidirectional signaling scheme," IEEE Journal ofSolid-State Circuits, Dec. 1995, vol. 30, no.12, p. 1538-43
[4] 叶菁华,陈一辉,郭淦,“一种适用于高速数据通信的发送器”,半导体学报 No.5 2003
[5] R. C. Foss, et al., "Memory- fast interfaced for DRAMs," IEEE Spectrum, Oct. 1992, vol. 29, no. 10, pp. 54-7
[6] N. Kushiyama, et al., "A 500-megabyte/s data-rate 4.5 M DRAM," IEEE Journal of Solid-State Circuits, Apr. 1993. vol. 28, no. 4, p. 490-8
[7] A. Le Fevre, R. Flett, "A 100Mb/s Multi-LAN Crosspoint Chip-Set for Cable Management," IEEE Journal of Solid-State Circuits, Jul. 1997, vol. 32, no. 7, pp. 1115-1121
[8] 朱江,陈钰,洪志良“0.18um CMOS工艺784Mb/s的数据发送器的设计”系统工程与电子技术,Vol.23,No.3 2001.
[9] 张展鹏,郭亚炜,汪若鹏“100Base-Tx以太网物理收发器的设计”微电子学 No.6 2002
[10] 陈钰,洪志良,“用于2.5 Gbps千兆以太网发接器的时钟倍频器的设计”,已被《固体电子学研究与进展》录用
[11] 叶菁华,郭淦,陈一辉,“0.18um CMOS工艺3.125Gb/s发送器的设计”半导体学报 No.7 2004
[12] Yueng. E. Y "Design of High-Performance and Low-Cost Parallel Links" Ph. D Dissertation Jan 2002.
[13] Yang. C. K. K "Design of High-Speed Serial Links in CMOS" Ph. D Dissertation Dec. 1998
[14] R. Farjad-Rad, C. Yang, M. A. Horowitz, and T. H. Lee, "A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter," IEEE Journal of Solid-State Circuits, vol. 34, pp. 580-585, May 1999.
[15] http://www.velio.com
[16] 陈学峰,“四通道3.125-Gb/s CMOS发接器的系统研究与集成”,硕士学位论文,2003。
[17] Maxim Integrated Products, "Jitter in digital communication systems- part 1," Application Note HFAN-4.0.3, Sep. 2001.
[18] http://www.serialata.org/
[19] 陈一辉,“高速低噪声锁相时钟发生器的设计”,硕士学位论文,2003。
[20] Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki,"2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology", IEEE Journal of Solid-State Circuits, vol. 31, pp. 2024-2029, December 1996.
[21] John F. Ewen, Albert X. Widmer, Mehmet Soyuer," Single-chip 1062Mbaud CMOS transceiver for serial data communication", IEEE International Solid-State Circuits Conference, vol. ⅩⅩⅩⅧ, pp. 32-33, February 1995.
[22] Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, " A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture", IEEE Journal of Solid-State Circuits, vol. 33, pp. 2139-2147, December 1998.
[23] Dao-Long Chen, Michael O. Baker;" A 1.25Gb/s, 460mW CMOS transceiver for serial data communication", IEEE International Solid-State Circuits Conference, vol. ⅩL, pp. 242-243, February 1997.
[24] 苏彦峰,叶菁华,洪志良“一种用于千兆以太网发接器的高速串并转换电路的设计”,微电子学 Vol.33 No.3 PP247～250 2003
[25] 数字集成电路设计
[26] R. Farjad-Rad et al., "An Equalization Scheme for 10Gb/s 4-PAM Signalling over Long Cables" IEEE Mixed Signal Conference, Digest of technical papers, Cancun, Mexico, July 1997.
[27] 黄林,郭淦,叶菁华,“一种采用半速结构的CMOS串行数据收发器的设计”,半导体学报 Vol.26 No.1 Jan,.2005
[28] 郭淦,叶菁华,黄林,“一种采用半速率时钟的1.25Gbit/s串行数据接收器的设计”,通信学报 Vol.25 No.5 May.2004
[29] 李曙光,“高速锁相环电路的设计及其在1.25/2.5 Gbps高速以太网串并转电路中的应用,”复旦大学硕士学位论文,2001年。
[30] Alan Fiedler, Ross Mactaggart, James Welch, Shoba Krishnan; A 1.0625Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis, IEEE International Solid-State Circuits Conference, vol. ⅩL, pp. 238-239, February
[31] Ramin Farjad-Rad, Chih-Kong Yang, Mark A. Horowitz, Thomas H. Lee; A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial, link transmitter, IEEE Journal of Solid-State Circuits, vol. 34, pp. 580-585, May 1999.
[32] David J. Foley, Michael P. Flynn; A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS, IEEE Journal of Solid-State Circuits, vol. 37, pp. 310-316, March 2002.
[33] Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi; A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1611-1618, November 2000.
[34] Dao-Long Chen, Michael O. Baker; A 1.25Gb/s, 460mW CMOS transceiver for serial data communication, IEEE International Solid-State Circuits Conference, vol. ⅩL, pp. 242-243, February 1997.
[35] Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi; A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture, IEEE Journal of Solid-State Circuits, vol. 33, pp. 2139-2147, December 1998.
[36] Dao-Long Chen, Robert Waldron; A single-chip 266Mb/s CMOS
[2] J. Kuskin, et al., "The Stanford FLASH Multiprocessor," Proceedings of the 21st International Symposium on Computer Architecture, Chicago, IL, Apr. 1994, pp. 302-13
[3] R. Mooney, et al., "A 900 Mb/s bidirectional signaling scheme," IEEE Journal ofSolid-State Circuits, Dec. 1995, vol. 30, no.12, p. 1538-43
[4] 叶菁华,陈一辉,郭淦,“一种适用于高速数据通信的发送器”,半导体学报 No.5 2003
[5] R. C. Foss, et al., "Memory- fast interfaced for DRAMs," IEEE Spectrum, Oct. 1992, vol. 29, no. 10, pp. 54-7
[6] N. Kushiyama, et al., "A 500-megabyte/s data-rate 4.5 M DRAM," IEEE Journal of Solid-State Circuits, Apr. 1993. vol. 28, no. 4, p. 490-8
[7] A. Le Fevre, R. Flett, "A 100Mb/s Multi-LAN Crosspoint Chip-Set for Cable Management," IEEE Journal of Solid-State Circuits, Jul. 1997, vol. 32, no. 7, pp. 1115-1121
[8] 朱江,陈钰,洪志良“0.18um CMOS工艺784Mb/s的数据发送器的设计”系统工程与电子技术,Vol.23,No.3 2001.
[9] 张展鹏,郭亚炜,汪若鹏“100Base-Tx以太网物理收发器的设计”微电子学 No.6 2002
[10] 陈钰,洪志良,“用于2.5 Gbps千兆以太网发接器的时钟倍频器的设计”,已被《固体电子学研究与进展》录用
[11] 叶菁华,郭淦,陈一辉,“0.18um CMOS工艺3.125Gb/s发送器的设计”半导体学报 No.7 2004
[12] Yueng. E. Y "Design of High-Performance and Low-Cost Parallel Links" Ph. D Dissertation Jan 2002.
[13] Yang. C. K. K "Design of High-Speed Serial Links in CMOS" Ph. D Dissertation Dec. 1998
[14] R. Farjad-Rad, C. Yang, M. A. Horowitz, and T. H. Lee, "A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter," IEEE Journal of Solid-State Circuits, vol. 34, pp. 580-585, May 1999.
[15] http://www.velio.com
[16] 陈学峰,“四通道3.125-Gb/s CMOS发接器的系统研究与集成”,硕士学位论文,2003。
[17] Maxim Integrated Products, "Jitter in digital communication systems- part 1," Application Note HFAN-4.0.3, Sep. 2001.
[18] http://www.serialata.org/
[19] 陈一辉,“高速低噪声锁相时钟发生器的设计”,硕士学位论文,2003。
[20] Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki,"2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology", IEEE Journal of Solid-State Circuits, vol. 31, pp. 2024-2029, December 1996.
[21] John F. Ewen, Albert X. Widmer, Mehmet Soyuer," Single-chip 1062Mbaud CMOS transceiver for serial data communication", IEEE International Solid-State Circuits Conference, vol. ⅩⅩⅩⅧ, pp. 32-33, February 1995.
[22] Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, " A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture", IEEE Journal of Solid-State Circuits, vol. 33, pp. 2139-2147, December 1998.
[23] Dao-Long Chen, Michael O. Baker;" A 1.25Gb/s, 460mW CMOS transceiver for serial data communication", IEEE International Solid-State Circuits Conference, vol. ⅩL, pp. 242-243, February 1997.
[24] 苏彦峰,叶菁华,洪志良“一种用于千兆以太网发接器的高速串并转换电路的设计”,微电子学 Vol.33 No.3 PP247～250 2003
[25] 数字集成电路设计
[26] R. Farjad-Rad et al., "An Equalization Scheme for 10Gb/s 4-PAM Signalling over Long Cables" IEEE Mixed Signal Conference, Digest of technical papers, Cancun, Mexico, July 1997.
[27] 黄林,郭淦,叶菁华,“一种采用半速结构的CMOS串行数据收发器的设计”,半导体学报 Vol.26 No.1 Jan,.2005
[28] 郭淦,叶菁华,黄林,“一种采用半速率时钟的1.25Gbit/s串行数据接收器的设计”,通信学报 Vol.25 No.5 May.2004
[29] 李曙光,“高速锁相环电路的设计及其在1.25/2.5 Gbps高速以太网串并转电路中的应用,”复旦大学硕士学位论文,2001年。
[30] Alan Fiedler, Ross Mactaggart, James Welch, Shoba Krishnan; A 1.0625Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis, IEEE International Solid-State Circuits Conference, vol. ⅩL, pp. 238-239, February
[31] Ramin Farjad-Rad, Chih-Kong Yang, Mark A. Horowitz, Thomas H. Lee; A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial, link transmitter, IEEE Journal of Solid-State Circuits, vol. 34, pp. 580-585, May 1999.
[32] David J. Foley, Michael P. Flynn; A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS, IEEE Journal of Solid-State Circuits, vol. 37, pp. 310-316, March 2002.
[33] Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi; A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1611-1618, November 2000.
[34] Dao-Long Chen, Michael O. Baker; A 1.25Gb/s, 460mW CMOS transceiver for serial data communication, IEEE International Solid-State Circuits Conference, vol. ⅩL, pp. 242-243, February 1997.
[35] Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi; A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture, IEEE Journal of Solid-State Circuits, vol. 33, pp. 2139-2147, December 1998.
[36] Dao-Long Chen, Robert Waldron; A single-chip 266Mb/s CMOS