RS解码器在CMMB系统中的设计及实现
摘要
全球移动通信正在飞速发展,各种新的移动数据业务也在不断地出现。手机电视业务的出现,将带给人们全新的收视体验,让人们无论在机场,公园,商场还是出租车上都能实时地收看电视节目。中国移动多媒体广播(China Mobile Multimedia Broadcasting,CMMB)作为中国自主研发的手机电视标准,代表着中国自主的知识产权,拥有巨大的市场前景。
CMMB信号采用无线传输,为了保证传输的可靠性,就需要对信息进行纠错编码。RS(Reed-Solomon)编码作为一种重要的信道编码,有着很强的纠错能力,配合上字节交织,尤其对突发错误的纠正效果相当不错。CMMB系统中规定用低密度奇偶检验(Low Density Parity Check,LDPC)编码配合RS编码作为前向纠错(Forward Error Correction,FEC)的组成部分。
本文主要针对FEC中RS解码器的设计进行研究。CMMB接收机由于装在移动设备上用于接收移动数据,而其数据量并不是很大,因此对RS解码器的速度要求并不高,而由于移动设备基本都靠电池供电,因此低功耗就成为本文设计的一个主要要求,因此本文中的设计主要以降低RS解码器的面积和功耗为目的,而以牺牲RS解码器的速度为代价。
本文中介绍了几种常用的RS译码算法,通过比较最后确定以修正欧几里德算法为设计的基础。在硬件设计上,参考了各种相关论文中RS解码器的设计,对解码器的各子模块进行了分析,分别选取了一种面积和功耗都比较合适的设计,其中伴随式计算电路部分通过对算法的分析进行了独创的改进,减小了一定的功耗,而面积几乎没有增加。修正欧几里德算法部分通过对系统需求的分析,选择了一种速度较慢但是面积和功耗都比较低的设计。错误位置和错误值的部分本文参考经典设计进行了复用。另外,在整体结构上,本设计结合CMMB接收系统的特点,去掉了用作延时单元的存储器,减少了对硬件资源的占用。最后,用Verilog语言实现了本文中涉及到的各种设计,通过对各实现分别进行综合和仿真,将各种设计的面积和功耗进行了比较分析,验证了本设计可以在CMMB系统中使用,并证实了本文中各种降低功耗和面积的改进是有效的。
Wireless communication is developing rapidly and many new services appeared. Mobile TV as a new service will bring a new experience to us. We can watch TV either at an airport, a park, a department or in taxi in the future. CMMB is a standard of mobile TV developed by China. It stands for the intellectual property of China and will be used widely.
CMMB signal is transmitted wirelessly. For receive the correct information, forward error correction is necessary. RS coding is an important channel coding technology. It has a good performance at error correction. Concatenated with byte interleaving, it works well especially for burst error. RS and LDPC coding is used as part of FEC in CMMB system.
In this thesis, we focused on the design of RS decoder. CMMB receiver is equipped on mobile device. The data rate is not very high, so decoding speed is not very important for our decoder. Low power consumption is necessary because mobile device always powered by a battery. The design described in this thesis is focused on low power and low area, while this design may slow down the decoding speed.
We introduced some RS decoding algorithm and compare them. Finally we choose the MEA algorithm as the base of our design. After referenced some papers on RS decoder, we designed each sub modules of RS decoder. According to analysis of algorithm, syndrome computation circuit is modified for decreasing power consumption, and the area is almost not increased. MEA circuit is designed for low power while slowing down the decoding speed. The last part is the error location and error value computation circuit and typical design is used for this part. Considering the structure of CMMB receiver, delay cell is not used in this design. This brings us low area and low power. At last, we implemented designs mentioned in this thesis on Verilog language. Synthesis and simulation is done for these designs and the result proves that the design in this thesis is available.
CMMB信号采用无线传输,为了保证传输的可靠性,就需要对信息进行纠错编码。RS(Reed-Solomon)编码作为一种重要的信道编码,有着很强的纠错能力,配合上字节交织,尤其对突发错误的纠正效果相当不错。CMMB系统中规定用低密度奇偶检验(Low Density Parity Check,LDPC)编码配合RS编码作为前向纠错(Forward Error Correction,FEC)的组成部分。
本文主要针对FEC中RS解码器的设计进行研究。CMMB接收机由于装在移动设备上用于接收移动数据,而其数据量并不是很大,因此对RS解码器的速度要求并不高,而由于移动设备基本都靠电池供电,因此低功耗就成为本文设计的一个主要要求,因此本文中的设计主要以降低RS解码器的面积和功耗为目的,而以牺牲RS解码器的速度为代价。
本文中介绍了几种常用的RS译码算法,通过比较最后确定以修正欧几里德算法为设计的基础。在硬件设计上,参考了各种相关论文中RS解码器的设计,对解码器的各子模块进行了分析,分别选取了一种面积和功耗都比较合适的设计,其中伴随式计算电路部分通过对算法的分析进行了独创的改进,减小了一定的功耗,而面积几乎没有增加。修正欧几里德算法部分通过对系统需求的分析,选择了一种速度较慢但是面积和功耗都比较低的设计。错误位置和错误值的部分本文参考经典设计进行了复用。另外,在整体结构上,本设计结合CMMB接收系统的特点,去掉了用作延时单元的存储器,减少了对硬件资源的占用。最后,用Verilog语言实现了本文中涉及到的各种设计,通过对各实现分别进行综合和仿真,将各种设计的面积和功耗进行了比较分析,验证了本设计可以在CMMB系统中使用,并证实了本文中各种降低功耗和面积的改进是有效的。
Wireless communication is developing rapidly and many new services appeared. Mobile TV as a new service will bring a new experience to us. We can watch TV either at an airport, a park, a department or in taxi in the future. CMMB is a standard of mobile TV developed by China. It stands for the intellectual property of China and will be used widely.
CMMB signal is transmitted wirelessly. For receive the correct information, forward error correction is necessary. RS coding is an important channel coding technology. It has a good performance at error correction. Concatenated with byte interleaving, it works well especially for burst error. RS and LDPC coding is used as part of FEC in CMMB system.
In this thesis, we focused on the design of RS decoder. CMMB receiver is equipped on mobile device. The data rate is not very high, so decoding speed is not very important for our decoder. Low power consumption is necessary because mobile device always powered by a battery. The design described in this thesis is focused on low power and low area, while this design may slow down the decoding speed.
We introduced some RS decoding algorithm and compare them. Finally we choose the MEA algorithm as the base of our design. After referenced some papers on RS decoder, we designed each sub modules of RS decoder. According to analysis of algorithm, syndrome computation circuit is modified for decreasing power consumption, and the area is almost not increased. MEA circuit is designed for low power while slowing down the decoding speed. The last part is the error location and error value computation circuit and typical design is used for this part. Considering the structure of CMMB receiver, delay cell is not used in this design. This brings us low area and low power. At last, we implemented designs mentioned in this thesis on Verilog language. Synthesis and simulation is done for these designs and the result proves that the design in this thesis is available.
引文
1彭德智,谢子常,DVB-H在手机移动电视中的应用,福建电脑,2006年第9期:170~172
2李卓伟,卓东风,张延华,基于T-DMB技术的视频传输仿真研究,科技情报开发与经济,2007年第17卷第14期:208~210
3孙晓辉,陈晓,MediaFLO和手机电视技术标准,2006年中国数字电视与网络发展高峰论坛第八届全国消费电子技术交流会论文集:248~253
4倪兴,杜娟,李民详,吴伟陵,手机电视技术分析与比较,电视技术,2006年第5期:25~29
5 Hyun-Yong Lee and In-Cheol Park,A Fast Reed-Solomon Product-Code Decoder Without Redundant Computations , Circuits and Systems, 2004:381~384.
6 European Standard, EN 300 421 V1.1.2 (1997-08)
7 European Standard, EN 300 429 V1.2.1 (1998-04)
8国家广播电影电视总局,中华人民共和国广播电影电视行业标准GY/T 220.1 (2006)
9王胜军,张思东,RS编码器的FPGA设计和实现,铁道通信信号,2007年8月,第43卷,第8期:62~64
10孙军英,RS码的编译码算法及DSP实现,2003.12
11樊昌信,通信原理教程,电子工业出版社
12仇佩亮,信息论与编码,高等教育出版社
13姚伟春,DVB-S2系统外码译码的设计与实现,浙江大学硕士学位论文,2006年5月
14李宏,王世练,张尔扬,基于BM算法的RS译码器的FPGA优化实现,第十三届信息论学术年会论文集:60~65
15 Mook Kyou Song, Eung Bae Kim, Hee Sun Won and Min Han Kong, ARCHITECTURE FOR DECODING ADAPTIVE REED-SOLOMON CODES WITH VARIABLE BLOCK LENGTH, IEEE Transaction on Consumer Electronics, Vol 48, No. 3, AUGUST 2002: 631~637
16 Leilei Song and Keshab K. Parhi, LOW-COMPLEXITY MODIFIED MASTROVITO MULTIPLIERS OVER FINITE FIELDS GF(2M), IEEE International Symposium, Volume 1, 30 May-2 June 1999: 508~512
17 IEEE Std802.16, IEEE Standard for Local and Metropolitan Area, IEEE, 2004
18 HOWARD M. SHAO, T.K. TRUONG, LESLIE J. DEUTSCH, JOSEPH H. YUEN, IRVINGS.REED, A VLSI Design of a Pipeline Reed-Solomon Decoder, IEEE TRANSACTION ON COMPUTERS, VOL. C-24, NO. 5, MAY 1985:393~403
19 Qingsheng Hu, Zhigong Wang, Jun Zhang and Jie Xiao, Low Complexity Parallel Chien Search Architecture for RS Decoder, IEEE International Symposium on 23-26 May 2005: 340~343
20 HOWARD M. SHAO and IRVING S. REED. On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays. IEEE TRANSACTIONS ON COMPUTERS, VOL. 37, NO. 10, OCTOBER, 1988, pp. 1273-1280
21 Yousef R. Shayan and Tho Le-Ngoc, A Cellular Structure for a Versatile Reed-Solomon Decoder, IEEE TRANSACTION ON COMPUTERS, VOL. 46, NO. 1, JANUARY, 1997:80~85
22 YOUSEF R. SHAYAN, THO LE-NGOC, VIJAY K. BHARGAVA, A Versatile Time-Domain Reed-Solomon Decoder, IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 8, NO. 8, OCTOBER, 1990:1535~1542
23 Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, AN AREA-EFFICIENT VERSATILE REED-SOLOMON DECODER FOR ADSL, IEEE International Symposium on Volume 1, 30 May-2 June, 1999:517~520
24 Hanho Lee, An Ultra High-Speed Reed-Solomon Decoder, IEEE International Symposium on 23-26 May 2005:1036~1039
25唐冬明,刘玉君,杨忠立,王天宇,Berlekamp-Massey算法和基本迭代算法求错位多项式,信息工程大学学报,2004年12月,第5卷,第4期
26 Ahmed O. El-Rayis, Xin Zhao , Tughrul Arslan, Ahmet T.Erdogan, Dynamically programmable Reed Solomon processor with embedded Galois Field multiplier, Field-Programmable Technology, 2008. International Conference on 8-10 Dec. 2008:269~272
27 Leilei Song and Keshab K. Parhi, Efficient Finite Field Serial/Parallel Multiplication, Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on 19-21 Aug. 1996:72~82
28 Hyunman Chang and Myung H. Sunwoo, A LOW COMPLEXITY REED-SOLOMON ARCHITECTURE USING THE EUCLID’S ALGORITHM. Circuits and Systems. 1999. ISCAS
99. Proceedings of the 1999 IEEE International Symposium on Volume 1, 30 May-2 June 1999:513~516
29 H. M. SHAO, T. K. TRUONG, I. S. HSU, L. J. DEUTSCH, A SINGLE CHIP VLSI REED-SOLOMON DECODER, Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP 86. Volume 11, Apr 1986:2151~2154
30 Dana J. Taipale and Michael J. Seo, An Efficient Soft-Decision Reed-Solomon Decoding Algorithm, IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 40, NO. 4, JULY, 1994:1130~1139
31 Hanho Lee, High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder, IEEE TRANSACTIONS ON VERY LARGE SCALE INTERGRATION (VLSI) SYSTEMS, VOL. 11, NO. 2, APRIL 2003:288~294
32 Shyue-Win Wei and Che-Ho Wei, High-Speed Decoder of Reed-Solomon Codes, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 41, NO. 11, NOVEMBER 1993:1588~1593
33 Fuh-ke Chang, Wei-Chun Hsu, Chien-Ching Lin, and Hsie-Chia Chang, Design and Implementation of a Reconfigurable Architecture for (528,518) Reed-Solomon Codec IP, IEEE-NEWCAS Conference, 2005. The 3rd International 19-22 June 2005:87~90
34 HyunMan Chang and Myung H. Sunwoo, DESIGN OF AN AREA EFFICIENT REED-SOLOMON DECODER ASIC CHIP, Signal Processing Systems, 1999. IEEE Workshop on 20-22 Oct. 1999:578~585
35 YOUSEF R. SHAYAN, THO LE-NGOC, VIJAY K. BHARGAVA, Design of Reed-Solomon (16,12) Codec for North American Advanced Train Control System, IEEE TRANSACTION VEHICULAR TECHNOLOGY, VOL. 39, NO. 4, NOVEMBER, 1990:400~409
36胡庆生,王志功,张军,肖洁,2.5Gb/s Reed-Solomon译码器的VLSI优化实现,电路与系统学报,2005年4月,第10卷,第2期:57~65
37孙伟,吴建辉,顾烊,HDTV解调芯片中RS解码器的电路优化,解放军理工大学学报,2006年6月,第7卷,第3期:225~228
38朱起悦,RS码编码和译码的算法,电讯技术,1999年4月,第39卷,第2期:63~67
39张辅云,葛建华,RS译码的Euclid算法及其FPGA实现,中国有线电视,2003年第14期:6~9
40王梦,李明,严来金,一种高速RS译码器的FPGA实现,电子技术应用,2005年,第1期:75~77
41苏佳宁,田骏骅,沈泊,闵昊,一种适用于DVB系统的低复杂度Reed-Solomon解码器,复旦学报(自然科学版),2006年2月,第45卷第1期:1~5
42袁丹寿,戎蒙恬,陈波,一种并行的有限域乘法器结构,上海交通大学学报,2005年4月,第39卷第4期:636~644
2李卓伟,卓东风,张延华,基于T-DMB技术的视频传输仿真研究,科技情报开发与经济,2007年第17卷第14期:208~210
3孙晓辉,陈晓,MediaFLO和手机电视技术标准,2006年中国数字电视与网络发展高峰论坛第八届全国消费电子技术交流会论文集:248~253
4倪兴,杜娟,李民详,吴伟陵,手机电视技术分析与比较,电视技术,2006年第5期:25~29
5 Hyun-Yong Lee and In-Cheol Park,A Fast Reed-Solomon Product-Code Decoder Without Redundant Computations , Circuits and Systems, 2004:381~384.
6 European Standard, EN 300 421 V1.1.2 (1997-08)
7 European Standard, EN 300 429 V1.2.1 (1998-04)
8国家广播电影电视总局,中华人民共和国广播电影电视行业标准GY/T 220.1 (2006)
9王胜军,张思东,RS编码器的FPGA设计和实现,铁道通信信号,2007年8月,第43卷,第8期:62~64
10孙军英,RS码的编译码算法及DSP实现,2003.12
11樊昌信,通信原理教程,电子工业出版社
12仇佩亮,信息论与编码,高等教育出版社
13姚伟春,DVB-S2系统外码译码的设计与实现,浙江大学硕士学位论文,2006年5月
14李宏,王世练,张尔扬,基于BM算法的RS译码器的FPGA优化实现,第十三届信息论学术年会论文集:60~65
15 Mook Kyou Song, Eung Bae Kim, Hee Sun Won and Min Han Kong, ARCHITECTURE FOR DECODING ADAPTIVE REED-SOLOMON CODES WITH VARIABLE BLOCK LENGTH, IEEE Transaction on Consumer Electronics, Vol 48, No. 3, AUGUST 2002: 631~637
16 Leilei Song and Keshab K. Parhi, LOW-COMPLEXITY MODIFIED MASTROVITO MULTIPLIERS OVER FINITE FIELDS GF(2M), IEEE International Symposium, Volume 1, 30 May-2 June 1999: 508~512
17 IEEE Std802.16, IEEE Standard for Local and Metropolitan Area, IEEE, 2004
18 HOWARD M. SHAO, T.K. TRUONG, LESLIE J. DEUTSCH, JOSEPH H. YUEN, IRVINGS.REED, A VLSI Design of a Pipeline Reed-Solomon Decoder, IEEE TRANSACTION ON COMPUTERS, VOL. C-24, NO. 5, MAY 1985:393~403
19 Qingsheng Hu, Zhigong Wang, Jun Zhang and Jie Xiao, Low Complexity Parallel Chien Search Architecture for RS Decoder, IEEE International Symposium on 23-26 May 2005: 340~343
20 HOWARD M. SHAO and IRVING S. REED. On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays. IEEE TRANSACTIONS ON COMPUTERS, VOL. 37, NO. 10, OCTOBER, 1988, pp. 1273-1280
21 Yousef R. Shayan and Tho Le-Ngoc, A Cellular Structure for a Versatile Reed-Solomon Decoder, IEEE TRANSACTION ON COMPUTERS, VOL. 46, NO. 1, JANUARY, 1997:80~85
22 YOUSEF R. SHAYAN, THO LE-NGOC, VIJAY K. BHARGAVA, A Versatile Time-Domain Reed-Solomon Decoder, IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 8, NO. 8, OCTOBER, 1990:1535~1542
23 Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, AN AREA-EFFICIENT VERSATILE REED-SOLOMON DECODER FOR ADSL, IEEE International Symposium on Volume 1, 30 May-2 June, 1999:517~520
24 Hanho Lee, An Ultra High-Speed Reed-Solomon Decoder, IEEE International Symposium on 23-26 May 2005:1036~1039
25唐冬明,刘玉君,杨忠立,王天宇,Berlekamp-Massey算法和基本迭代算法求错位多项式,信息工程大学学报,2004年12月,第5卷,第4期
26 Ahmed O. El-Rayis, Xin Zhao , Tughrul Arslan, Ahmet T.Erdogan, Dynamically programmable Reed Solomon processor with embedded Galois Field multiplier, Field-Programmable Technology, 2008. International Conference on 8-10 Dec. 2008:269~272
27 Leilei Song and Keshab K. Parhi, Efficient Finite Field Serial/Parallel Multiplication, Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on 19-21 Aug. 1996:72~82
28 Hyunman Chang and Myung H. Sunwoo, A LOW COMPLEXITY REED-SOLOMON ARCHITECTURE USING THE EUCLID’S ALGORITHM. Circuits and Systems. 1999. ISCAS
99. Proceedings of the 1999 IEEE International Symposium on Volume 1, 30 May-2 June 1999:513~516
29 H. M. SHAO, T. K. TRUONG, I. S. HSU, L. J. DEUTSCH, A SINGLE CHIP VLSI REED-SOLOMON DECODER, Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP 86. Volume 11, Apr 1986:2151~2154
30 Dana J. Taipale and Michael J. Seo, An Efficient Soft-Decision Reed-Solomon Decoding Algorithm, IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 40, NO. 4, JULY, 1994:1130~1139
31 Hanho Lee, High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder, IEEE TRANSACTIONS ON VERY LARGE SCALE INTERGRATION (VLSI) SYSTEMS, VOL. 11, NO. 2, APRIL 2003:288~294
32 Shyue-Win Wei and Che-Ho Wei, High-Speed Decoder of Reed-Solomon Codes, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 41, NO. 11, NOVEMBER 1993:1588~1593
33 Fuh-ke Chang, Wei-Chun Hsu, Chien-Ching Lin, and Hsie-Chia Chang, Design and Implementation of a Reconfigurable Architecture for (528,518) Reed-Solomon Codec IP, IEEE-NEWCAS Conference, 2005. The 3rd International 19-22 June 2005:87~90
34 HyunMan Chang and Myung H. Sunwoo, DESIGN OF AN AREA EFFICIENT REED-SOLOMON DECODER ASIC CHIP, Signal Processing Systems, 1999. IEEE Workshop on 20-22 Oct. 1999:578~585
35 YOUSEF R. SHAYAN, THO LE-NGOC, VIJAY K. BHARGAVA, Design of Reed-Solomon (16,12) Codec for North American Advanced Train Control System, IEEE TRANSACTION VEHICULAR TECHNOLOGY, VOL. 39, NO. 4, NOVEMBER, 1990:400~409
36胡庆生,王志功,张军,肖洁,2.5Gb/s Reed-Solomon译码器的VLSI优化实现,电路与系统学报,2005年4月,第10卷,第2期:57~65
37孙伟,吴建辉,顾烊,HDTV解调芯片中RS解码器的电路优化,解放军理工大学学报,2006年6月,第7卷,第3期:225~228
38朱起悦,RS码编码和译码的算法,电讯技术,1999年4月,第39卷,第2期:63~67
39张辅云,葛建华,RS译码的Euclid算法及其FPGA实现,中国有线电视,2003年第14期:6~9
40王梦,李明,严来金,一种高速RS译码器的FPGA实现,电子技术应用,2005年,第1期:75~77
41苏佳宁,田骏骅,沈泊,闵昊,一种适用于DVB系统的低复杂度Reed-Solomon解码器,复旦学报(自然科学版),2006年2月,第45卷第1期:1~5
42袁丹寿,戎蒙恬,陈波,一种并行的有限域乘法器结构,上海交通大学学报,2005年4月,第39卷第4期:636~644