符合数字电视地面传输国标的级联编译码研究与实现
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摘要
前向纠错码被广泛用于现代通信系统中,编码简单,纠错能力强,能够弥补信道噪声污染带来的影响。传统的通信系统中仅使用单一的前向纠错码技术,存在纠错能力不足等原因。为了能够最大程度的接近信道容量,进一步降低误码率,人们不断提出各种纠错码级联技术。中国数字电视地面广播传输标准(DTMB)采用低密度奇偶校验码(LDPC)码与BCH码级联来进行前向纠错。本文在分析已有的LDPC码与BCH码级联性能基础上,对其硬件实现进行了改进研究。本文主要工作如下：
1.对LDPC与BCH级联译码性能进行了研究。基于Matlab平台,加入交织技术进行性能仿真。分析结果表明,BCH有效降低了LDPC译码的误码平台(error floor),误比特率到达10-6数量级时,可以提高0.3dB的编码增益；交织技术显著提高了级联译码器的纠错性能,当误比特率在10-4数量级时,可以提高0.1dB的编码增益；
2.改进了传统的伽罗华域中乘法器电路,减少了组合逻辑延迟和单个门电路的驱动负载。设计出符合DTMB标准的BCH并行编码器,编码器降低了时钟消耗,减少了扇出瓶颈的影响,能对连续码流进行不间断的编码,可以很好的满足连续码流编码的时序要求；
3.改进了伴随式计算电路,改进后的伴随式计算电路仅需要一个乘法器和一个加法器；利用固定因子乘法器设计钱搜索电路,可以显著降低硬件消耗,并改进电路结构使其适合于缩短BCH码；提出了两级流水线BCH译码器结构。该译码器完成一次译码只需96个时钟周期,在EDA工具Altera quartusⅡ中综合结果表明其最大工作频率可达到256.94MHz;
4.设计了基于PDIUSBD12的USB接口电路、PC机上位机程序和USB接口子板。测试结果表明,USB接口能提供200KBps数据传输速率；
5.搭建了FPGA测试平台。设计了位转换、FIFO等模块来传输符合DTMB中译码器需要的数据。测试结果表明硬件测试与软件仿真一致。
本文的研究工作在DTMB标准整体算法实现中具有较好的应用价值,并能扩展到相关的应用领域。
本论文受上海市科委项目《基于LDPC算法的高性能专用指令集处理器系统架构研究》(编号：08700741200)基金资助,中国科学院无线传感网与通信重点实验室《无线通信LDPC专用指令集译码器设计研究》开放课题资助。
Forward Error Correction code (FEC) is widely used in modern communication systems, as it has several advantages such as easily encoding, strong ability to correct errors and avoiding the influence from channel noise. Conventional communication systems only utilizes forward error correction code technique, it is obviously insufficient in the error correction capability and has other disadvantages. In order to approach the maximum channel capacity and decrease the bit error rate, the method of concatenated code was adopted. Low Density Parity Check(LDPC) code concatenated BCH code is utilized by China Digital Television Multimedia Broadcasting System (DTMB) to correct errors. This paper studied the performance of concatenated LDPC and BCH code and carried out its implementation. The major work of this paper is as follows:
1. The performance of the concatenated code is simulated by Matlab with the help of interleave technique. The result shows that BCH code can effectively clear error floor induced by LDPC decoder at bit error rate of 10-6, and the coding gain can rise 0.3dB. After adding interleaver, the coding gain of concatenated decoder can increase 0.1 dB at bit error rate of 10-4.
2. By improving the multiplier in Galois Field, the combinational logic delay and the load of the single gate circuit are decreased. BCH parallel encoder coincided with DTMB is designed to decrease the cost of clock and reduces the influence of fanout bottleneck. The encoder can encode consecutive bitstreams and fulfill the sequence requirement in the standard.
3. Syndrome circuit is improved to decrease the number of multiplier and adder to only one. The parallel Chien search circuit which is designed by using single constant input multiplier has low cost in hardware, and the circuit is adjusted to fit for short BCH code. The structure of BCH decoder with two-stage pipeline is proposed. The decoder needs only 96 clocks to decode one code. The synthesis result from Altera QuartusⅡshows that the max operating frequency of the decoder can achieve 256.94MHz.
4. The USB interface circuit based on chip.PDIUSBD12 is designed, together with PC software and daughterboard of USB interface. Test results show that the transmit speed of the interface is up to 200KBps.
5. The test platform is built and the module of bit changing and FIFO is also designed to meet the data requirement of DTMB decoder. The performance of concatenated decoder was verified in the FPGA of Xilinx Virtex-4. The hardware test shows identical results with the simulation on software. This work shows good value in the realization of DTMB standard algorithm, and
can be extended to applications in related fields.
This dissertation work is supported by Foundation of Shanghai Science and Technology Committee under project "Research on high-performance ASIP architecture based on LDPC" (No. 08700741200), open project of Key Lab of Wireless Sensor Network & Communication, Chinese Academy of Sciences "Research on ASIP architecture based on LDPC in wireless communications"
1.对LDPC与BCH级联译码性能进行了研究。基于Matlab平台,加入交织技术进行性能仿真。分析结果表明,BCH有效降低了LDPC译码的误码平台(error floor),误比特率到达10-6数量级时,可以提高0.3dB的编码增益；交织技术显著提高了级联译码器的纠错性能,当误比特率在10-4数量级时,可以提高0.1dB的编码增益；
2.改进了传统的伽罗华域中乘法器电路,减少了组合逻辑延迟和单个门电路的驱动负载。设计出符合DTMB标准的BCH并行编码器,编码器降低了时钟消耗,减少了扇出瓶颈的影响,能对连续码流进行不间断的编码,可以很好的满足连续码流编码的时序要求；
3.改进了伴随式计算电路,改进后的伴随式计算电路仅需要一个乘法器和一个加法器；利用固定因子乘法器设计钱搜索电路,可以显著降低硬件消耗,并改进电路结构使其适合于缩短BCH码；提出了两级流水线BCH译码器结构。该译码器完成一次译码只需96个时钟周期,在EDA工具Altera quartusⅡ中综合结果表明其最大工作频率可达到256.94MHz;
4.设计了基于PDIUSBD12的USB接口电路、PC机上位机程序和USB接口子板。测试结果表明,USB接口能提供200KBps数据传输速率；
5.搭建了FPGA测试平台。设计了位转换、FIFO等模块来传输符合DTMB中译码器需要的数据。测试结果表明硬件测试与软件仿真一致。
本文的研究工作在DTMB标准整体算法实现中具有较好的应用价值,并能扩展到相关的应用领域。
本论文受上海市科委项目《基于LDPC算法的高性能专用指令集处理器系统架构研究》(编号：08700741200)基金资助,中国科学院无线传感网与通信重点实验室《无线通信LDPC专用指令集译码器设计研究》开放课题资助。
Forward Error Correction code (FEC) is widely used in modern communication systems, as it has several advantages such as easily encoding, strong ability to correct errors and avoiding the influence from channel noise. Conventional communication systems only utilizes forward error correction code technique, it is obviously insufficient in the error correction capability and has other disadvantages. In order to approach the maximum channel capacity and decrease the bit error rate, the method of concatenated code was adopted. Low Density Parity Check(LDPC) code concatenated BCH code is utilized by China Digital Television Multimedia Broadcasting System (DTMB) to correct errors. This paper studied the performance of concatenated LDPC and BCH code and carried out its implementation. The major work of this paper is as follows:
1. The performance of the concatenated code is simulated by Matlab with the help of interleave technique. The result shows that BCH code can effectively clear error floor induced by LDPC decoder at bit error rate of 10-6, and the coding gain can rise 0.3dB. After adding interleaver, the coding gain of concatenated decoder can increase 0.1 dB at bit error rate of 10-4.
2. By improving the multiplier in Galois Field, the combinational logic delay and the load of the single gate circuit are decreased. BCH parallel encoder coincided with DTMB is designed to decrease the cost of clock and reduces the influence of fanout bottleneck. The encoder can encode consecutive bitstreams and fulfill the sequence requirement in the standard.
3. Syndrome circuit is improved to decrease the number of multiplier and adder to only one. The parallel Chien search circuit which is designed by using single constant input multiplier has low cost in hardware, and the circuit is adjusted to fit for short BCH code. The structure of BCH decoder with two-stage pipeline is proposed. The decoder needs only 96 clocks to decode one code. The synthesis result from Altera QuartusⅡshows that the max operating frequency of the decoder can achieve 256.94MHz.
4. The USB interface circuit based on chip.PDIUSBD12 is designed, together with PC software and daughterboard of USB interface. Test results show that the transmit speed of the interface is up to 200KBps.
5. The test platform is built and the module of bit changing and FIFO is also designed to meet the data requirement of DTMB decoder. The performance of concatenated decoder was verified in the FPGA of Xilinx Virtex-4. The hardware test shows identical results with the simulation on software. This work shows good value in the realization of DTMB standard algorithm, and
can be extended to applications in related fields.
This dissertation work is supported by Foundation of Shanghai Science and Technology Committee under project "Research on high-performance ASIP architecture based on LDPC" (No. 08700741200), open project of Key Lab of Wireless Sensor Network & Communication, Chinese Academy of Sciences "Research on ASIP architecture based on LDPC in wireless communications"
引文
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[23]Ivan B. Djordjevic, Lei Xu, Ting Wang, "Reverse Concatenated Coded Modulation for High-Speed Optical Communication" [J], IEEE Photonics Journal, Vol.2, No.6, pp.1034-1039.2010.12
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[2]R.W. Hamming. "Error Detecting and Error Correcting Codes. Bell System Tech" [J]. Vol.29, pp.147-160,1950.
[3]Hocquenghem, "Codes correcteurs d'erreurs" [J],Chiffres, Vol.2, pp.147-156, 1959.
[4]R. C. Bose and D. K. Ray-Chaudhuri, "On a Class of Error CorrectingBinary Group Codes" [J], Information and Control, Volume 3, pp.68-79,March 1960.
[5]E. R. Berlekamp, "Algebraic Coding Theory" [J], New York, McGraw-Hill, 1968,Chap.7.
[6]J. L. Massey, "Shift-register synthesis and BCH decoding" [J], IEEE Trans, 1969, IT-15, pp.122-127.
[7]S. Reed and G. Solomon, "Polynomial Codes over Certain Finite Fields" [J], SI AM Journal of Applied Mathematics, Volume 8, pp.300-304,1960.
[8]C. Berrou, A.Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding:Turbo-codes" [C], in Proc. IEEE Int. Conf. Commun., Geneva, Switzerland, May 1993, pp.1064-1070.
[9]R. G. Gallager, "Low density parity check codes" [J], IRE Trans. Inform. Theory, vol. IT-8, Jan.1962, pp.21-28.
[10]G. D. Forney. "Concatenated codes" [D], Cambridge, Massachusetts:MIT Press, 1967.
[11]Andrews, K.S. Divsalar, D. Dolinar, S. Hamkins, J. Jones, C. Pollara, "The Development of Turbo and LDPC Codes for Deep-Space Applications" [J], Proceedings of the IEEE, Vol.95, no.11, pp.2142-2156, Nov.2007.
[12]T. Richardson, "Error floors of LDPC codes" [C], in Proc.41st Allerton Conf. Comm., Control, and Comput., Monticello, IL,2003.
[13]张军,“光纤通信中的级联码技术及其实现研究”[D],东南大学博士学位论文,2007
[14]ETSI. "Digital Video Broadcasting (DVB), Second generation framing structure,channel coding and modulation systems for Broadcasting, Interactive Services, Ne- ws Gathering and other broadband satellite applications" [S], EN 302 307 V1.1.2.
[15]ATSC standard,A/53, "ATSC digitial television standard" [S],. USA:ATSC. 1995.9.
[16]ISDB-T, "Specification of channel coding framing structure and modulation" [S],1998.9.28.
[17]中国国家标准化管理委员会.“数字电视地面广播传输系统帧结构、信道编码和调制”.[S],GB20600-2006：2006.08.18.
[18]Krishna R. Narayanan,Gordon L. Stuber, "Selective Serial Concatenation of Turbo Codes" [J], IEEE Communications Letters, Vol.1, No.5,1997.9.
[19]ITU-T Recommendation G.975, "Forward error correction for submarine systems" [S],1996.11.
[20]K. Seki, K. Mikami, A. Katayama, S. Suzuki, N. Shinohara, M. Nakabayashi, "Single-chip FEC codec using a concatenated BCH code for 10Gb/s long-haul optical transmission systems" [C], IEEE Custom Integrated circuits Conference,2003.9
[21]ITU-T Recommendation G.975.1, "Forward error correction for high bit-rate DWDM submarine systems" [S],2004.2
[22]Ningde Xie, Wei Xu, Tong Zhang, Erich F. Haratsch, and Jaekyun Moon, "Concatenated Low-Density Parity-Check and BCH Coding System for Magnetic Recording Read Channel With 4kB Sector Format" [J], IEEE Transaction on Magnetics, Vol.44, No.12, pp.4784-4789,2008.12
[23]Ivan B. Djordjevic, Lei Xu, Ting Wang, "Reverse Concatenated Coded Modulation for High-Speed Optical Communication" [J], IEEE Photonics Journal, Vol.2, No.6, pp.1034-1039.2010.12
[24]王新梅,肖国振,纠错码--原理与方法.修订版[M].西安：西安电子科技大学出版社,2001.
[25]贺鹤云,LDPC码基础与应用[M],北京：人民邮电出版社.2009
[26]Joiner, L.L.; Komo, J. J., "Decoding binary BCH codes," [C], Southeastcon'95. 'Visualize the Future'., Proceedings., IEEE, pp.67-73,26-29 Mar 1995
[27]R. M. Tanner. A Recursive Approach to Low Complexity Codes. IEEE Transactions On Information. Theory, Vol.27, pp.533-547,1981
[28]Mohammad M. Mansour, Naresh R.Shanbhag, "High-Through LDPC Decoders" [J], IEEE Transaction on Very Large Scale Integration Systems, Vol. 11,No.6, Dec.2003..
[29]Sae-Young Chung, Forney, GD., Jr. Richardson, T.J. Urbanke, R, "On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit" [J], IEEE Communications Letters,2001,5, (2):58-60.
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