GPON中FEC编解码器的研究与实现
摘要
在现代通信系统中,前向纠错(FEC)得到了广泛的应用。最新的无源光网络GPON就引入了FEC这一功能。GPON中应用FEC可以减小接收端的误码率,增加通信的可靠性。同时,FEC也可以降低对光器件的性能要求,从而节约成本。
GPON中的FEC采用RS码的纠错编码方式。本文重点研究了最流行的两种RS解码算法—Berlekamp–Massey算法和Euclidean算法及其各种改进形式。本文利用VLSI设计思想,将算法映射到硬件结构,实现了RS编码器和三款RS解码器。
本文基于修正的欧几里德算法(MEA)设计了一种新的硬件解码器实现结构,称其为FPrME(Fully-pipelined recursive modified Euclidean)解码器。它关键路径延时很小,并且为全流水线连续解码工作方式。对比Altera公司最新的IP Core,FPrME解码器在占用芯片资源和工作频率两方面性能都更好。
本文的编解码器采用Altera公司的FPGA芯片Stratix GX EP1SGX25DF672C7在系统时钟125MHz的情况下完成了电路板测试。
在RS(255,239)硬件编码器/解码器实现的基础上,本文按照GPON协议要求,针对GPON中最高速率2.488Gbps的下行帧,通过设计复杂的操作时序,实现了符合协议规定的32位并行FEC编解码和解扰码电路,并作了仿真。
本文实现的RS(255,239)FPrME硬件解码器的性能在国内外具有领先水平。本文给出的并行FEC实现电路完全符合ITU-T标准,具有很大的应用价值。
Forward Error Correction(FEC) has been widely used in the modern communication system. FEC is adopted in Gigabit Passive Optical Network(GPON). FEC in the GPON can reduce the error ratio at the receiver and increase the reliability of communication. At the same time, FEC can decrease the requisition for the performance of the optical devices.
FEC in the GPON adopts the Reed-Solomon(RS) code. This paper emphasizes on the most popular RS decoding algorithm: Berlekamp–Massey algorithm and Euclidean algorithm, and their improved form. This paper utilizes the VLSI design method to map the algorithms to the hardware architecture, and has realized the RS encoder and three kinds of RS decoders.
In this paper, a new architecture of hardware decoder based on the Modified Euclidean Algorithm(MEA) is provided, and it is called the FPrME (Fully-pipelined recursive modified Euclidean)decoder. It’s critical path delay is very little, and it operates in the fully-pipelined continuous decoding manner. Compared to the Altera’s newest IP Core, the FPrME decoder is better in either size or rate. The encoder and decoders in the paper has been tested on the circuit board using the Altera’s FPGA of Stratix GX EP1SGX25DF672C7 with the system clock of 125MHz.
Based on the realization of the encoder/decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel FEC circuit and scrambler complying with the protocols and maken a simulation.
The FPrME decoder is advanced in the world. The parallel FEC circuit completely conforms to the ITU-T protocols ,and has important practical value.
GPON中的FEC采用RS码的纠错编码方式。本文重点研究了最流行的两种RS解码算法—Berlekamp–Massey算法和Euclidean算法及其各种改进形式。本文利用VLSI设计思想,将算法映射到硬件结构,实现了RS编码器和三款RS解码器。
本文基于修正的欧几里德算法(MEA)设计了一种新的硬件解码器实现结构,称其为FPrME(Fully-pipelined recursive modified Euclidean)解码器。它关键路径延时很小,并且为全流水线连续解码工作方式。对比Altera公司最新的IP Core,FPrME解码器在占用芯片资源和工作频率两方面性能都更好。
本文的编解码器采用Altera公司的FPGA芯片Stratix GX EP1SGX25DF672C7在系统时钟125MHz的情况下完成了电路板测试。
在RS(255,239)硬件编码器/解码器实现的基础上,本文按照GPON协议要求,针对GPON中最高速率2.488Gbps的下行帧,通过设计复杂的操作时序,实现了符合协议规定的32位并行FEC编解码和解扰码电路,并作了仿真。
本文实现的RS(255,239)FPrME硬件解码器的性能在国内外具有领先水平。本文给出的并行FEC实现电路完全符合ITU-T标准,具有很大的应用价值。
Forward Error Correction(FEC) has been widely used in the modern communication system. FEC is adopted in Gigabit Passive Optical Network(GPON). FEC in the GPON can reduce the error ratio at the receiver and increase the reliability of communication. At the same time, FEC can decrease the requisition for the performance of the optical devices.
FEC in the GPON adopts the Reed-Solomon(RS) code. This paper emphasizes on the most popular RS decoding algorithm: Berlekamp–Massey algorithm and Euclidean algorithm, and their improved form. This paper utilizes the VLSI design method to map the algorithms to the hardware architecture, and has realized the RS encoder and three kinds of RS decoders.
In this paper, a new architecture of hardware decoder based on the Modified Euclidean Algorithm(MEA) is provided, and it is called the FPrME (Fully-pipelined recursive modified Euclidean)decoder. It’s critical path delay is very little, and it operates in the fully-pipelined continuous decoding manner. Compared to the Altera’s newest IP Core, the FPrME decoder is better in either size or rate. The encoder and decoders in the paper has been tested on the circuit board using the Altera’s FPGA of Stratix GX EP1SGX25DF672C7 with the system clock of 125MHz.
Based on the realization of the encoder/decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel FEC circuit and scrambler complying with the protocols and maken a simulation.
The FPrME decoder is advanced in the world. The parallel FEC circuit completely conforms to the ITU-T protocols ,and has important practical value.
引文
[1] ITU-T.G.984.1.Gigabit-capable Passive Optical Networks(GPON):General characteristics.2003
[2] ITU-T.G.984.2.Gigabit-capable Passive Optical Networks (GPON):Physical Media Dependent (PMD) layer specification.2003
[3] ITU-T.G.984.3.Gigabit-capable Passive Optical Networks (G-PON): Transmission convergence layer specification.2004
[4] ITU-T.G.984.4.Gigabit-capable Passive Optical Networks (G-PON):ONT management and control interface specification.2004
[5] ITU-T.G.975.Forward error correction for submarine systems.2000
[6] Xu Youzhi.Implementation of Berlekamp-Massey algorithm without inversion.IEE PROCEEDINGS-I,1991,138(2):138-140
[7] Hsie-Chia Chang,C. Bernard Shung.New Serial Architecture for the Berlekamp–Massey Algorithm.IEEE TRANSACTIONS ON COMMUNICATIONS,1999,47(4):481-483
[8] Dilip V. Sarwate, Naresh R. Shanbhag. High-Speed Architectures for Reed–Solomon Decoders. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9(5):641-655
[9] H.M.Shao,T.K.Truong,L.J.Deutsch,J.H.Yuen. A VLSI Design of a pipeline Reed-Solomon Decoder. IEEE Trans. On Computer,1985,34(5):393-403
[10] Hanho Lee. High-Speed VLSI Architecture for ParallelReed–Solomon Decoder. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11(2):288-294
[11] Hanho Lee. A High-Speed Low-Complexity Reed–Solomon Decoder for Optical Communications. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 2005,52(8):461-465
[12] M.H.Cheng. Generalised Berlekamp-Massey algorithm.IEE Proc.Commun.,2002, 149(4):207-210
[13] 张辅云, 葛建华. RS 译码的 Euclid 算法及其 FPGA 实现. 中国有线电视 ,2003,14:6-9
[14] 张宗橙. 纠错编码原理和应用. 北京:电子工业出版社, 2003, 34-149
[15] 王冬梅 DVB 系统中 RS 编/解码器的 FPGA 实现:[硕士学位论文], 成都:电子科技大学, 2003
[16] 茹国宝, 苏利, 秦丹青, 赵. R-S 码快速译码算法的研究. 武汉大学学报 ,1999,45(5): 631-633
[17] 于伟,鞠德航. 一种 RS 码变换域译码算法及其并行流水结构. 宇航学报, 2000,21(1): 71-78
[18] A. Shiozaki, T.K. Truong, K.M. Cheung, IS. Reed. Fast transform decoding of nonsystematic Reed-Solomon codes. IEE PROCEEDINGS,1990,137(2):139-143
[19] ROBERT J. McELIECE AND LAIF SWANSON. On the Decoder Error Probability for Reed-Solomon Codes. IEEE TRANSACTIONS ON INFORMATION THEORY,1986, 32(5):701-703
[20] T.Buerner,R.Dohmen. On a High-Speed Reed-Solomon Codec Architecture for 43 Gb/s Optical Transmission System. PROC. 24fh INTERNATIONAL CONFERENCE ON MICROELECTRONICS,2004,2:743-746
[21] I. S. HSU, T. K. TRUONG, L. J. DEUTSCH, ANDI. S. REED. A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases. IEEE TRANSACTIONS ON COMPUTERS, 1988, 37(6):735-739
[22] Rurness R, Fenn S.T.J, Benaissa M. Multiplication using the triangular basis representation over GF(2m). IEEE GLOBECOM'96 Communications,1996,788-792
[23] 胡庆生, 王志功, 张军, 肖洁. 2.5Gb/s Reed-Solomon 译码器的 VLSI 优化实现. 电路与系统学报 ,2005,10(2):57-65
[24] Altera. lpm_rom Megafunction User Guide. 2005
[25] Altera. Single- & Dual-Clock FIFO Megafunction User Guide. 2005
[26] Mook Kyou Song, Eung Bae Kim, Hee Sun Won, Min Han Kong. ARCHITECTURE FOR DECODING ADAPTIVE REED-SOLOMON CODES WITH VARIABLE BLOCK LENGTH. IEEE Transactions on Consumer Electronics, 2002,48(3):631-637
[27] Altera. Quartus?II 简介. 2005
[28] Altera. Reed-Solomon Compiler User Guide. 2004
[29] Altera. Stratix GX Device Family Data Sheet. 2005
[30] 石军, 刘增基. 并行 SDH 扰码器/解扰器的设计. 西安电子科技大学学报, 1997,24(3): 342-345
[2] ITU-T.G.984.2.Gigabit-capable Passive Optical Networks (GPON):Physical Media Dependent (PMD) layer specification.2003
[3] ITU-T.G.984.3.Gigabit-capable Passive Optical Networks (G-PON): Transmission convergence layer specification.2004
[4] ITU-T.G.984.4.Gigabit-capable Passive Optical Networks (G-PON):ONT management and control interface specification.2004
[5] ITU-T.G.975.Forward error correction for submarine systems.2000
[6] Xu Youzhi.Implementation of Berlekamp-Massey algorithm without inversion.IEE PROCEEDINGS-I,1991,138(2):138-140
[7] Hsie-Chia Chang,C. Bernard Shung.New Serial Architecture for the Berlekamp–Massey Algorithm.IEEE TRANSACTIONS ON COMMUNICATIONS,1999,47(4):481-483
[8] Dilip V. Sarwate, Naresh R. Shanbhag. High-Speed Architectures for Reed–Solomon Decoders. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9(5):641-655
[9] H.M.Shao,T.K.Truong,L.J.Deutsch,J.H.Yuen. A VLSI Design of a pipeline Reed-Solomon Decoder. IEEE Trans. On Computer,1985,34(5):393-403
[10] Hanho Lee. High-Speed VLSI Architecture for ParallelReed–Solomon Decoder. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11(2):288-294
[11] Hanho Lee. A High-Speed Low-Complexity Reed–Solomon Decoder for Optical Communications. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 2005,52(8):461-465
[12] M.H.Cheng. Generalised Berlekamp-Massey algorithm.IEE Proc.Commun.,2002, 149(4):207-210
[13] 张辅云, 葛建华. RS 译码的 Euclid 算法及其 FPGA 实现. 中国有线电视 ,2003,14:6-9
[14] 张宗橙. 纠错编码原理和应用. 北京:电子工业出版社, 2003, 34-149
[15] 王冬梅 DVB 系统中 RS 编/解码器的 FPGA 实现:[硕士学位论文], 成都:电子科技大学, 2003
[16] 茹国宝, 苏利, 秦丹青, 赵. R-S 码快速译码算法的研究. 武汉大学学报 ,1999,45(5): 631-633
[17] 于伟,鞠德航. 一种 RS 码变换域译码算法及其并行流水结构. 宇航学报, 2000,21(1): 71-78
[18] A. Shiozaki, T.K. Truong, K.M. Cheung, IS. Reed. Fast transform decoding of nonsystematic Reed-Solomon codes. IEE PROCEEDINGS,1990,137(2):139-143
[19] ROBERT J. McELIECE AND LAIF SWANSON. On the Decoder Error Probability for Reed-Solomon Codes. IEEE TRANSACTIONS ON INFORMATION THEORY,1986, 32(5):701-703
[20] T.Buerner,R.Dohmen. On a High-Speed Reed-Solomon Codec Architecture for 43 Gb/s Optical Transmission System. PROC. 24fh INTERNATIONAL CONFERENCE ON MICROELECTRONICS,2004,2:743-746
[21] I. S. HSU, T. K. TRUONG, L. J. DEUTSCH, ANDI. S. REED. A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases. IEEE TRANSACTIONS ON COMPUTERS, 1988, 37(6):735-739
[22] Rurness R, Fenn S.T.J, Benaissa M. Multiplication using the triangular basis representation over GF(2m). IEEE GLOBECOM'96 Communications,1996,788-792
[23] 胡庆生, 王志功, 张军, 肖洁. 2.5Gb/s Reed-Solomon 译码器的 VLSI 优化实现. 电路与系统学报 ,2005,10(2):57-65
[24] Altera. lpm_rom Megafunction User Guide. 2005
[25] Altera. Single- & Dual-Clock FIFO Megafunction User Guide. 2005
[26] Mook Kyou Song, Eung Bae Kim, Hee Sun Won, Min Han Kong. ARCHITECTURE FOR DECODING ADAPTIVE REED-SOLOMON CODES WITH VARIABLE BLOCK LENGTH. IEEE Transactions on Consumer Electronics, 2002,48(3):631-637
[27] Altera. Quartus?II 简介. 2005
[28] Altera. Reed-Solomon Compiler User Guide. 2004
[29] Altera. Stratix GX Device Family Data Sheet. 2005
[30] 石军, 刘增基. 并行 SDH 扰码器/解扰器的设计. 西安电子科技大学学报, 1997,24(3): 342-345