纳米级CMOS逐次逼近A/D转换器设计研究与实现
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摘要
作为片上系统(SoC: System-on-Chip)的一种重要模块单元,A/D转换器(ADC: Analog-to-Digital Converter)的应用日益广泛。集成电路工艺尺寸的不断减小在推动数字电路迅速发展的同时增加了高性能模拟电路的设计难度,A/D转换器作为典型的数模混合信号电路,在纳米级CMOS工艺下既面临着机会也面临着挑战。作为应用最为广泛的一种ADC类型,逐次逼近(SAR: Successive Approximation Register)A/D转换器所含模拟电路较少,具有结构简单、功耗低、易集成等优点,在纳米级CMOS工艺下有很好的发展前景。
基于多种SAR ADC结构类型,采用理论分析推导结合Matlab建模验证的方式,对SAR ADC D/A转换网络无源元件匹配性以及能耗进行了研究。详细分析和讨论了SAR ADC中比较器、开关以及电压基准的设计技术。在以上研究的基础上,基于纳米级CMOS工艺设计实现了两种SAR A/D转换器。
基于SMIC 65nm CMOS低漏电工艺设计实现了一种8通道12-bit 200kS/s触摸屏SAR A/D转换器。提出了一种新型R-C混合式D/A转换结构,通过一种二进制比例的电容对实现了电阻梯的复用,减小了转换器的面积,整个ADC的面积小于0.13mm~2。提出了一种与SAR ADC工作原理完全兼容并且不增加任何额外时序逻辑的新型失调消除技术,有效减小了伪差分比较器的失调电压。提出了一种结合双端分段非线性补偿、对数项消除技术以及混合模式拓扑输出的新型温度补偿技术,提高了ADC内部电压基准源的温度稳定性。测试结果显示,12-bit SAR ADC具有70.13dB的信噪失真比(SNDR: Signal to Noise and Distortion Ratio),失调误差为1.28LSB,功耗仅为2.8mW,满足触摸屏SoC的应用要求。
基于SMIC 90nm CMOS Logic工艺设计实现了一种8通道10-bit SAR A/D转换器。提出了一种能够用于高速低功耗系统的新型电平转换器,和传统结构相比,在速度和功耗方面都得到了显著优化。通过采用该新型电平转换器,并对内部R-C混合式D/A转换网络以及低失调伪差分比较器进行速度优化,该转换器实现了2.5MS/s的采样速率。整个ADC的面积为0.051mm~2。在3.3V模拟电压和1.0V数字电压下,当输入为100kHz,3.0V峰-峰值的正弦信号时,该10-bit ADC具有9.41-bits有效位(ENOB: Effective Number of Bits),功耗为6.62mW。
通过采用双电源进行设计,两种纳米级ADC均在较小的面积下实现了良好的信噪比,优良指数(FoM: Figure-of-Merit)也分别达到5.32 pJ/conversion step和4.47 pJ/conversion step,已经达到同类设计的优秀水平。
A/D converters have been widely used as the SoCs’fundamental building blocks. With the silicon feature dimension downscaling into nanoscale, great improvement has been made in the performance of digital circuits, but making high performance analog circuits design increasingly difficult. As typical mixed signal circuits, A/D converters are facing both opportunities and challenges to realize high performance based on nanoscale CMOS. SAR A/D converter is one of the most popular ADCs due to its simple architecture, small area and easiness to be integrated with other blocks. SAR ADC contains less analog circuits and has advantages over other ADCs along with CMOS technology downscaling.
Based on different types of SAR A/D converter, the passive components’mismatch and energy dissipation of internal D/A conversion networks is explored with theoretical derivation and verified by modeling using Matlab. The key design techniques for the comparators, switches and voltage references in SAR ADCs are discussed in detail. Two A/D converters suitable for different applications are designed and implemented in nanoscale CMOS process.
An 8-channel 12-bit 200kS/s touch screen SAR ADC is realized based on SMIC 65nm CMOS low leakage process. The chip size is reduced to be less than 0.13mm~2 by using a novel R-C hybrid D/A conversion network, in which the resistor string is reused by a binary-ratioed capacitor pair. Without adding any additional control logic, a novel offset cancellation technique compatible with the operation of SAR ADC is proposed to reduce the offset of the pseudo-differential comparator. A novel temperature compensation technique used for the ADC internal bandgap voltage reference is proposed. With the double-end piecewise nonlinearity correction method, logarithm cancellation technique and the mixed mode output, the temperature stability of the internal voltage reference is improved. The measurement results of this 12-bit ADC show that the SNDR (Signal to Noise and Distortion Ratio) is 70.13dB and its power dissipation is only 2.8mW, meeting the requirement of the touch screen SoC application.
An 8-channal 10-bit SAR ADC is realized based on SMIC 90nm CMOS Logic process. A novel voltage level-shifter suitable for high-speed and low power SoC is described. Compared with traditional one, this level-shifter can operate at higher speed and dissipate even less power. By taking this new level-shifter, together with the optimization on speed of the low-offset pseudo-differential comparator and the internal R-C hybrid D/A conversion network, the 10-bit ADC can operate in a sampling rate of up to 2.5MS/s. This SAR A/D converter occupies an area of 0.051mm2. Under the condition of 3.3V analog supply, 1.0V digital supply and a 100 kHz 3.0Vp-p sinusoidal input signal, the ENOB (Effective Number of Bits) of this ADC is measured to be 9.41 and the power dissipation is 6.62mW.
Operated with two power supplies, both of these two nanoscale ADCs achieve high SNDR with small area. The FoM (Figure-of-Merit) of these two converters are 5.32-pJ/conv. step and 4.47 pJ/conv. step respectively, which are at the advanced level in this direction.
基于多种SAR ADC结构类型,采用理论分析推导结合Matlab建模验证的方式,对SAR ADC D/A转换网络无源元件匹配性以及能耗进行了研究。详细分析和讨论了SAR ADC中比较器、开关以及电压基准的设计技术。在以上研究的基础上,基于纳米级CMOS工艺设计实现了两种SAR A/D转换器。
基于SMIC 65nm CMOS低漏电工艺设计实现了一种8通道12-bit 200kS/s触摸屏SAR A/D转换器。提出了一种新型R-C混合式D/A转换结构,通过一种二进制比例的电容对实现了电阻梯的复用,减小了转换器的面积,整个ADC的面积小于0.13mm~2。提出了一种与SAR ADC工作原理完全兼容并且不增加任何额外时序逻辑的新型失调消除技术,有效减小了伪差分比较器的失调电压。提出了一种结合双端分段非线性补偿、对数项消除技术以及混合模式拓扑输出的新型温度补偿技术,提高了ADC内部电压基准源的温度稳定性。测试结果显示,12-bit SAR ADC具有70.13dB的信噪失真比(SNDR: Signal to Noise and Distortion Ratio),失调误差为1.28LSB,功耗仅为2.8mW,满足触摸屏SoC的应用要求。
基于SMIC 90nm CMOS Logic工艺设计实现了一种8通道10-bit SAR A/D转换器。提出了一种能够用于高速低功耗系统的新型电平转换器,和传统结构相比,在速度和功耗方面都得到了显著优化。通过采用该新型电平转换器,并对内部R-C混合式D/A转换网络以及低失调伪差分比较器进行速度优化,该转换器实现了2.5MS/s的采样速率。整个ADC的面积为0.051mm~2。在3.3V模拟电压和1.0V数字电压下,当输入为100kHz,3.0V峰-峰值的正弦信号时,该10-bit ADC具有9.41-bits有效位(ENOB: Effective Number of Bits),功耗为6.62mW。
通过采用双电源进行设计,两种纳米级ADC均在较小的面积下实现了良好的信噪比,优良指数(FoM: Figure-of-Merit)也分别达到5.32 pJ/conversion step和4.47 pJ/conversion step,已经达到同类设计的优秀水平。
A/D converters have been widely used as the SoCs’fundamental building blocks. With the silicon feature dimension downscaling into nanoscale, great improvement has been made in the performance of digital circuits, but making high performance analog circuits design increasingly difficult. As typical mixed signal circuits, A/D converters are facing both opportunities and challenges to realize high performance based on nanoscale CMOS. SAR A/D converter is one of the most popular ADCs due to its simple architecture, small area and easiness to be integrated with other blocks. SAR ADC contains less analog circuits and has advantages over other ADCs along with CMOS technology downscaling.
Based on different types of SAR A/D converter, the passive components’mismatch and energy dissipation of internal D/A conversion networks is explored with theoretical derivation and verified by modeling using Matlab. The key design techniques for the comparators, switches and voltage references in SAR ADCs are discussed in detail. Two A/D converters suitable for different applications are designed and implemented in nanoscale CMOS process.
An 8-channel 12-bit 200kS/s touch screen SAR ADC is realized based on SMIC 65nm CMOS low leakage process. The chip size is reduced to be less than 0.13mm~2 by using a novel R-C hybrid D/A conversion network, in which the resistor string is reused by a binary-ratioed capacitor pair. Without adding any additional control logic, a novel offset cancellation technique compatible with the operation of SAR ADC is proposed to reduce the offset of the pseudo-differential comparator. A novel temperature compensation technique used for the ADC internal bandgap voltage reference is proposed. With the double-end piecewise nonlinearity correction method, logarithm cancellation technique and the mixed mode output, the temperature stability of the internal voltage reference is improved. The measurement results of this 12-bit ADC show that the SNDR (Signal to Noise and Distortion Ratio) is 70.13dB and its power dissipation is only 2.8mW, meeting the requirement of the touch screen SoC application.
An 8-channal 10-bit SAR ADC is realized based on SMIC 90nm CMOS Logic process. A novel voltage level-shifter suitable for high-speed and low power SoC is described. Compared with traditional one, this level-shifter can operate at higher speed and dissipate even less power. By taking this new level-shifter, together with the optimization on speed of the low-offset pseudo-differential comparator and the internal R-C hybrid D/A conversion network, the 10-bit ADC can operate in a sampling rate of up to 2.5MS/s. This SAR A/D converter occupies an area of 0.051mm2. Under the condition of 3.3V analog supply, 1.0V digital supply and a 100 kHz 3.0Vp-p sinusoidal input signal, the ENOB (Effective Number of Bits) of this ADC is measured to be 9.41 and the power dissipation is 6.62mW.
Operated with two power supplies, both of these two nanoscale ADCs achieve high SNDR with small area. The FoM (Figure-of-Merit) of these two converters are 5.32-pJ/conv. step and 4.47 pJ/conv. step respectively, which are at the advanced level in this direction.
引文
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