血细胞分析仪通用信号采集存储系统设计
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摘要
数据采集技术是信息技术的重要组成之一,是计算机获取信息的主要手段,在工业生产和科学研究等许多领域具有广泛的应用。
本文以实际工程应用为背景,在分析了血细胞分析仪的基本原理以及应用需求的基础上,并基于系统对数据采集高速、大容量、同步等特点的要求,提出采用Nios II +μC/OS II + DDR2 + Ethernet的数据采集系统设计方案。该方案中Nios II为软核处理器,运行嵌入式实时操作系统μC/OS II,DDR2为高速数据存储设备,Ethernet为系统与计算机的连接方式——百兆以太网。
硬件设计上,着重探讨了DDR2高速电路的设计与信号完整性仿真、基于FPGA的以太网模块设计、系统电源模块设计等,并对各模块设计的关键部分进行了详细介绍。然后通过实验初步调试来验证系统硬件设计的正确性。
逻辑设计上,深入研究了当前各种IP核(知识产权核),并根据需求设计自定义外设控制器IP核,同时利用IP核技术设计数据采集模块逻辑电路,解决了系统设计中用传统方案难于解决的高速数据同步采集难题。然后基于已有IP核和自定义IP核构建SOPC系统。
嵌入式系统设计上,研究了基于μC/OS II的驱动程序设计和软件开发,通过消息邮箱通信机制和中断处理实现了嵌入式多任务应用程序的设计,最终建立了数据采集系统的RTOS。
最后,设计数据采集系统的远程控制软件平台和数据分析处理软件平台。通过实验测试和工程应用验证了该数据采集存储系统方案设计的正确性以及工程应用的可行性,为数据采集领域尤其是高速数据采集提供一种高效的解决方案。
The data acquisition technology, which is one of the important parts and parcels of the information technology and the primary means for computers to acquire information, is widely used in many fields, such as industry, science and so on.
This thesis takes the actual project as a background. In the analysis of the hematology analyzer’s basic principle as well as in the application demand, and based on high-speed, high-capacity, synchronization, and other characteristics of the system requirements, a data acquisition system design proposal that uses Nios II +μC/OS II + DDR2 + Ethernet is proposed. In this plan Nios II takes the soft-core processor, running embedded real-time operating systemμC/OS II. DDR2 is the high speed data storage device, and the interface between system and computer is 100Mbit/s ethernet.
Hardware design of this thesis, focuses on DDR2 high-speed circuit design and signal integrity simulation, FPGA-based Ethernet module design, system power source module design and so on, and also carries on the detailed introduction to the various modules design's essential part. The accuracy of the design is confirmed through the experiment preliminary debugging.
Logic design, in-depth study of the current IP cores (intellectual property core), accomplishes custom peripheral controller IP core design according to the demand. Simultaneously, the data gathering module logic circuit is achieved by using the IP core techno logy. This has solved the high speed data gathering difficult problem which is difficulty to solve with traditional plans in the system design. And then, the SOPC system is structured by using the acquired IP cores and self designed IP cores.
Embedded systems design, in study of driver design and the software development based onμC/OS II, realizes the embedded multi-duty application programm design through the news mailbox correspondence mechanism and the interrupt processing. The data acquisition system's RTOS is established ultimately.
Finally, the remote control software platform and the data analysis & process software platform for the data acquisition system are designed and accomplished. By analyzing the test results and engineering application, the correctness of the system design and the feasibility of its engineering application have been validated. This research provides one kind of highly effective solution for data acquisition domain particularly in high-speed data gathering.
本文以实际工程应用为背景,在分析了血细胞分析仪的基本原理以及应用需求的基础上,并基于系统对数据采集高速、大容量、同步等特点的要求,提出采用Nios II +μC/OS II + DDR2 + Ethernet的数据采集系统设计方案。该方案中Nios II为软核处理器,运行嵌入式实时操作系统μC/OS II,DDR2为高速数据存储设备,Ethernet为系统与计算机的连接方式——百兆以太网。
硬件设计上,着重探讨了DDR2高速电路的设计与信号完整性仿真、基于FPGA的以太网模块设计、系统电源模块设计等,并对各模块设计的关键部分进行了详细介绍。然后通过实验初步调试来验证系统硬件设计的正确性。
逻辑设计上,深入研究了当前各种IP核(知识产权核),并根据需求设计自定义外设控制器IP核,同时利用IP核技术设计数据采集模块逻辑电路,解决了系统设计中用传统方案难于解决的高速数据同步采集难题。然后基于已有IP核和自定义IP核构建SOPC系统。
嵌入式系统设计上,研究了基于μC/OS II的驱动程序设计和软件开发,通过消息邮箱通信机制和中断处理实现了嵌入式多任务应用程序的设计,最终建立了数据采集系统的RTOS。
最后,设计数据采集系统的远程控制软件平台和数据分析处理软件平台。通过实验测试和工程应用验证了该数据采集存储系统方案设计的正确性以及工程应用的可行性,为数据采集领域尤其是高速数据采集提供一种高效的解决方案。
The data acquisition technology, which is one of the important parts and parcels of the information technology and the primary means for computers to acquire information, is widely used in many fields, such as industry, science and so on.
This thesis takes the actual project as a background. In the analysis of the hematology analyzer’s basic principle as well as in the application demand, and based on high-speed, high-capacity, synchronization, and other characteristics of the system requirements, a data acquisition system design proposal that uses Nios II +μC/OS II + DDR2 + Ethernet is proposed. In this plan Nios II takes the soft-core processor, running embedded real-time operating systemμC/OS II. DDR2 is the high speed data storage device, and the interface between system and computer is 100Mbit/s ethernet.
Hardware design of this thesis, focuses on DDR2 high-speed circuit design and signal integrity simulation, FPGA-based Ethernet module design, system power source module design and so on, and also carries on the detailed introduction to the various modules design's essential part. The accuracy of the design is confirmed through the experiment preliminary debugging.
Logic design, in-depth study of the current IP cores (intellectual property core), accomplishes custom peripheral controller IP core design according to the demand. Simultaneously, the data gathering module logic circuit is achieved by using the IP core techno logy. This has solved the high speed data gathering difficult problem which is difficulty to solve with traditional plans in the system design. And then, the SOPC system is structured by using the acquired IP cores and self designed IP cores.
Embedded systems design, in study of driver design and the software development based onμC/OS II, realizes the embedded multi-duty application programm design through the news mailbox correspondence mechanism and the interrupt processing. The data acquisition system's RTOS is established ultimately.
Finally, the remote control software platform and the data analysis & process software platform for the data acquisition system are designed and accomplished. By analyzing the test results and engineering application, the correctness of the system design and the feasibility of its engineering application have been validated. This research provides one kind of highly effective solution for data acquisition domain particularly in high-speed data gathering.
引文
1左连富.流式细胞术与生物医学.沈阳:辽宁人民出版社,1996: 129~422
2沈关心,周汝麟.现代免疫学实验技术.武汉:湖北科学技术出版社, 2002: 226~230
3周丽,周振英.流式细胞仪研制的技术发展.现代医学仪器与应用. 2003,(1): 11~17
4胡建华,周金生.血细胞分析仪研究现状与进展.医疗装备.1999,(2):2~3
5陈俊梅,周为.血液分析仪技术的原理与应用.医疗设备信息. 2002,(10): 38~40
6刘洪祥.流式细胞术近期发展动向.中华物理医学杂志.1992,(14赠刊): 81~83
7杨海涛,苏涛.基于FPGA的高速大容量固态存储设备设计.国外电子元器件.2007,6(8)
8王阿川.基于FPGA高速图像采集卡的研制.自动化仪表.第26卷第6期: 21~23
9门亮,王立欣.基于FPGA的DDR SDRAM控制器在高速数据采集系统中的应用.哈尔滨工业大学电气工程及自动化学院.2007,4
10吴春付.光学多通道表面检测系统的研究.哈尔滨工业大学工学硕士学位论文. 2006,6
11方苗,陈泽文,彭橙廉.S0PC设计中的用户自定义逻辑.计算机工程.2004,(9)
12 Altera Corporation. Nios II embedded processor 32-bit programmers refrence manual [EB/OL]. http://www.altera.com/literature/lit-nio.html
13徐宁仪,周祖成. Avalon总线与SOPC系统架构实例.半导体技术.2003,2 (28)
14陈秀玲,周欣,陈黎平.新的片上可编程系统(SOPC)解决方案Nios II[J].今日电子.2003,7
15方茁,彭澄廉,陈泽文.基于Nios II的SOPC设计.计算机工程与设计.2004年4月,第25卷第4期
16黄正谨. CPLD系统设计技术入门与应用.电子工业出版社,2002: 17~42
17孙航.xilinx可编程逻辑器件的高级应用与设计技巧.电子工业出版社,2004: 21~160
18冯寿廷.FPGA/SOPC开发简明教程.http://www.21control.com
19 Altera Corporation. Dual DIMM DDR2 SDRAM memory interface design guidelines. Altera Corporation.2007
20 Micron Technology Incorporated. DDR2 design guide for Two-DIMM systems. TN-47-01
21 JEDEC STANDARD. DDR2 SDRAM specification. JESD79-2C, May 2006
22 JEDEC STANDARD. Stub series terminated logic for 1.8V (SSTL_18). JESD8-15A, Sep 2003
23 Altera Corporation. Design guidelines for implementing DDR and DDR2 SDRAM interfaces in Cyclone III devices. Altera Corporation. March 2007
24 Altera Corporation. Cyclone III device handbook. Altera Corporation. March 2007
25 Altera Corporation. Cyclone III design guidelines. Altera Corporation. August 2007
26 Altera Corporation. Cyclone III device handbook. Altera Corporation. March 2007: 238
27 Altera Corporation. External memory interfaces in Cyclone III devices. July 2007: 4
28 Intel Corporation. LXT971A 3.3 V dual-speed gast ethernet transceiver. Intel Corporation. August 2002: 49~51
29 Cypress Semiconductor Corporation. CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) Flow-Through SRAM with NoBL? Architecture. Cypress Semiconductor Corporation. November, 2004: 23
30 Altera Corporation.Altera embedded peripherals.Altera Corporation.2005
31 Altera Corporation.Avalon bus specification reference manual. Altera Corporation. 2003
32 Altera Corporation.Quartus II user’s manual.Altera Corporation.2007
33 Altera Corporation.Nios II development kit getting started user guide. Altera Corporation.2007
34邵贝贝译.嵌入式实时操作系统μC/OS-Ⅱ.北京航空航天出版社,2003,5: 34~71
35王莹莹.实时操作系统μC/OS-II内核分析与移植.重庆大学硕士学位论文.2007: 39~54
36 B. Zhou, W. D. Qiu, C. L. Peng. An Operating System Framework for Reconfigurable Systems. Computer and Information Technology, 2005. CIT 2005. The Fifth International Conference on 21-23 Sept. 2005: 781~787
37王命延,余爱军.一种加载在μC/OS-II内核上的嵌入式文件系统.南昌大学学报(理科版). 2005, 29(2): 197~204
38周立功. ARM与嵌入式系统实验教程.广州周立功单片机发展有限公司. 2004: 11~18
39 J. J.Labrosse.MicroC/OS-II the Real-Time Kernel.Second Edition.北京航空航天大学出版社, 2003: 72~115
40张谦,竹利平.μC/OS-II实时嵌入式操作系统的实时性分析与测试.计算机工程与设计.2005,26(9): 2422~2424
41邵贝贝译.嵌入式实时操作系统μC/OS-Ⅱ.北京航空航天出版社,2003,5: 111~115
42 L. Phillips A. Real-time Systems Design and Analysis, An Enginneer’s Handbook. Piseataway New Jersey. US: IEEE Computer Society Press. 1992
43 Altera Corporation. Nios II Software Developer’s Handbook. Altera Corporation. May 2008: 303~382
44 Altera Corporation. Quartus II Version 7.2 Handbook. Altera Corporation. October 2007: 2516~2520
2沈关心,周汝麟.现代免疫学实验技术.武汉:湖北科学技术出版社, 2002: 226~230
3周丽,周振英.流式细胞仪研制的技术发展.现代医学仪器与应用. 2003,(1): 11~17
4胡建华,周金生.血细胞分析仪研究现状与进展.医疗装备.1999,(2):2~3
5陈俊梅,周为.血液分析仪技术的原理与应用.医疗设备信息. 2002,(10): 38~40
6刘洪祥.流式细胞术近期发展动向.中华物理医学杂志.1992,(14赠刊): 81~83
7杨海涛,苏涛.基于FPGA的高速大容量固态存储设备设计.国外电子元器件.2007,6(8)
8王阿川.基于FPGA高速图像采集卡的研制.自动化仪表.第26卷第6期: 21~23
9门亮,王立欣.基于FPGA的DDR SDRAM控制器在高速数据采集系统中的应用.哈尔滨工业大学电气工程及自动化学院.2007,4
10吴春付.光学多通道表面检测系统的研究.哈尔滨工业大学工学硕士学位论文. 2006,6
11方苗,陈泽文,彭橙廉.S0PC设计中的用户自定义逻辑.计算机工程.2004,(9)
12 Altera Corporation. Nios II embedded processor 32-bit programmers refrence manual [EB/OL]. http://www.altera.com/literature/lit-nio.html
13徐宁仪,周祖成. Avalon总线与SOPC系统架构实例.半导体技术.2003,2 (28)
14陈秀玲,周欣,陈黎平.新的片上可编程系统(SOPC)解决方案Nios II[J].今日电子.2003,7
15方茁,彭澄廉,陈泽文.基于Nios II的SOPC设计.计算机工程与设计.2004年4月,第25卷第4期
16黄正谨. CPLD系统设计技术入门与应用.电子工业出版社,2002: 17~42
17孙航.xilinx可编程逻辑器件的高级应用与设计技巧.电子工业出版社,2004: 21~160
18冯寿廷.FPGA/SOPC开发简明教程.http://www.21control.com
19 Altera Corporation. Dual DIMM DDR2 SDRAM memory interface design guidelines. Altera Corporation.2007
20 Micron Technology Incorporated. DDR2 design guide for Two-DIMM systems. TN-47-01
21 JEDEC STANDARD. DDR2 SDRAM specification. JESD79-2C, May 2006
22 JEDEC STANDARD. Stub series terminated logic for 1.8V (SSTL_18). JESD8-15A, Sep 2003
23 Altera Corporation. Design guidelines for implementing DDR and DDR2 SDRAM interfaces in Cyclone III devices. Altera Corporation. March 2007
24 Altera Corporation. Cyclone III device handbook. Altera Corporation. March 2007
25 Altera Corporation. Cyclone III design guidelines. Altera Corporation. August 2007
26 Altera Corporation. Cyclone III device handbook. Altera Corporation. March 2007: 238
27 Altera Corporation. External memory interfaces in Cyclone III devices. July 2007: 4
28 Intel Corporation. LXT971A 3.3 V dual-speed gast ethernet transceiver. Intel Corporation. August 2002: 49~51
29 Cypress Semiconductor Corporation. CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) Flow-Through SRAM with NoBL? Architecture. Cypress Semiconductor Corporation. November, 2004: 23
30 Altera Corporation.Altera embedded peripherals.Altera Corporation.2005
31 Altera Corporation.Avalon bus specification reference manual. Altera Corporation. 2003
32 Altera Corporation.Quartus II user’s manual.Altera Corporation.2007
33 Altera Corporation.Nios II development kit getting started user guide. Altera Corporation.2007
34邵贝贝译.嵌入式实时操作系统μC/OS-Ⅱ.北京航空航天出版社,2003,5: 34~71
35王莹莹.实时操作系统μC/OS-II内核分析与移植.重庆大学硕士学位论文.2007: 39~54
36 B. Zhou, W. D. Qiu, C. L. Peng. An Operating System Framework for Reconfigurable Systems. Computer and Information Technology, 2005. CIT 2005. The Fifth International Conference on 21-23 Sept. 2005: 781~787
37王命延,余爱军.一种加载在μC/OS-II内核上的嵌入式文件系统.南昌大学学报(理科版). 2005, 29(2): 197~204
38周立功. ARM与嵌入式系统实验教程.广州周立功单片机发展有限公司. 2004: 11~18
39 J. J.Labrosse.MicroC/OS-II the Real-Time Kernel.Second Edition.北京航空航天大学出版社, 2003: 72~115
40张谦,竹利平.μC/OS-II实时嵌入式操作系统的实时性分析与测试.计算机工程与设计.2005,26(9): 2422~2424
41邵贝贝译.嵌入式实时操作系统μC/OS-Ⅱ.北京航空航天出版社,2003,5: 111~115
42 L. Phillips A. Real-time Systems Design and Analysis, An Enginneer’s Handbook. Piseataway New Jersey. US: IEEE Computer Society Press. 1992
43 Altera Corporation. Nios II Software Developer’s Handbook. Altera Corporation. May 2008: 303~382
44 Altera Corporation. Quartus II Version 7.2 Handbook. Altera Corporation. October 2007: 2516~2520