低电压低功耗CMOS射频低噪声放大器设计
摘要
随着无线通信和CMOS工艺的发展,采用CMOS工艺实现射频通信电路和系统成为合理的选择。这样的混合信号系统要求前端电路能够在低电压下工作。同时,现代射频通信前端尤其是LNA必须具有低噪声、高线性,在低功耗的条件下实现这些要求是实现射频通信系统关键技术之一。
本论文研究了低电压、低功耗CMOS低噪声放大器(LNA)的设计,包括以下内容:
1.对短沟道MOSFET电路仿真模型在特定运用状态下(强反型饱和区)进行简化,提出了一个简化设计模型以及通过电路仿真和数据拟合提取模型参数的方法。用这个方法可以推出MOSFET的大信号、小信号和噪声模型,用来分析预测电感源极负反馈LNA的增益、噪声、线性度和功耗,减少设计迭代次数。
2.分析了0.18微米工艺下MOSFET中各种噪声对于电感源极负反馈LNA噪声系数的影响,得到了计算噪声系数的解析式,并由此得出结论,由于寄生电容的作用,LNA的噪声系数依然主要决定于沟道热噪声电流;因此适当设计输入跨导级MOSFET的尺寸,可以实现低功耗低噪声。设计了一个低电压的折叠结构电感源极负反馈共源共栅LNA,仿真验证了上述结论。
3.应用级数展开的方法分析了电感源极负反馈LNA的非线性,得到了LNA线性度和功耗关于栅源偏置电压和MOSFET尺寸的解析表达式。为了获得高的线性度,有必要采取补偿的办法。比较了各种非线性补偿方法,提出了一种低电压的用线性区MOSFET补偿来提高线性度的折叠型电感源极负反馈共源共栅LNA,给出了该电路的设计原则。流片测试结果证明了采用这种按照这个原则设计的补偿结构电路能够以较小的功耗代价将输入三阶交截点功率提高约5dB。
4.解析分析了封装寄生效应对源极电感负反馈LNA各项性能的影响。指出在给定封装寄生参数的条件下,为了保证LNA输入端阻抗严格匹配以及高增益、低噪声,应当适当加大输入级MOSFET的栅源之间的电容。比较了两种加大电容的方法,指出适当加大MOSFET沟道长度的方法优于添加附加并联电容的方法。仿真验证了上述结论。
With the development of radio frequency (RF) communications and the CMOStechnology, it has become a reasonable choice to implement the RF communicationcircuits and systems in CMOS process. The RF front-end circuits in this kind ofmixed-signal systems are required to be able to work under low voltage. Front-ends,especially LNAs for modern RF communications are also required to be low-noiseand highly linear and to fulfill those requirements with low power is among the keytechnologies for the implementation of RF communication systems.
The design of low-voltage, low-power CMOS low noise amplifiers (LNA) isconducted in this thesis and includes:
1. A simple design model and the method to extract its parameters by circuitsimulation and data fitting is proposed based on simplifying the circuit simulationmodel of short channel MOSFET in a specific operation region (strong inversion andsaturation). The large-and small-signal model, and noise model can be derived toanalyze the gain, noise, linearity and power of inductively source-degenerated CMOSLNAs and to predict their simulation results so that the design iterations can bereduced.
2. The contribution of different noise components of MOSFETs in 0.18micrometer process to the noise figure (NF) of the inductively source-degeneratedLNA is calculated and the analytical expression of the NF is derived. It is shown thatdue to the parasitic capacitance NF is still dominated by the channel thermal noisecurrent;therefore, low noise can be achieved with low power dissipation by properlysizing the MOSFET in the input transconductance stage. A low-voltage foldedcascode inductively degenerated LNA is designed and the above analysis is verifiedby simulation.
3. The nonlinearity of the inductively source-degenerated LNA is analyzed withseries expansion method and analytical expressions relating the power and linearity tothe size and bias of the MOSFET are found. Compensation is needed to achieve highlinearity, and different compensation methods are compared. A low-voltage folded
cascode LNA compensated using MOSFET in the triode region is proposed, and thenthe design guides are given. About 5dB input-inferred third-order interception pointpower enhancement at little power cost has been demonstrated by the measurementsof the fabricated IC chip compensated with this technique and designed under thegiven guides.4. The effects of packaging parasitics on the performance of inductivelydegenerated LNAs are analytically studied. It is shown that, with parasitics given, toachieve perfect input matching, high gain and low noise, the capacitance across thegate and source of MOSFET in the input stage should be properly large. Two ways toenlarge the capacitance are compared and using longer channel MOSFET ispreferable to adding an extra parallel capacitor. These observations are verifiedthrough circuit simulation.
本论文研究了低电压、低功耗CMOS低噪声放大器(LNA)的设计,包括以下内容:
1.对短沟道MOSFET电路仿真模型在特定运用状态下(强反型饱和区)进行简化,提出了一个简化设计模型以及通过电路仿真和数据拟合提取模型参数的方法。用这个方法可以推出MOSFET的大信号、小信号和噪声模型,用来分析预测电感源极负反馈LNA的增益、噪声、线性度和功耗,减少设计迭代次数。
2.分析了0.18微米工艺下MOSFET中各种噪声对于电感源极负反馈LNA噪声系数的影响,得到了计算噪声系数的解析式,并由此得出结论,由于寄生电容的作用,LNA的噪声系数依然主要决定于沟道热噪声电流;因此适当设计输入跨导级MOSFET的尺寸,可以实现低功耗低噪声。设计了一个低电压的折叠结构电感源极负反馈共源共栅LNA,仿真验证了上述结论。
3.应用级数展开的方法分析了电感源极负反馈LNA的非线性,得到了LNA线性度和功耗关于栅源偏置电压和MOSFET尺寸的解析表达式。为了获得高的线性度,有必要采取补偿的办法。比较了各种非线性补偿方法,提出了一种低电压的用线性区MOSFET补偿来提高线性度的折叠型电感源极负反馈共源共栅LNA,给出了该电路的设计原则。流片测试结果证明了采用这种按照这个原则设计的补偿结构电路能够以较小的功耗代价将输入三阶交截点功率提高约5dB。
4.解析分析了封装寄生效应对源极电感负反馈LNA各项性能的影响。指出在给定封装寄生参数的条件下,为了保证LNA输入端阻抗严格匹配以及高增益、低噪声,应当适当加大输入级MOSFET的栅源之间的电容。比较了两种加大电容的方法,指出适当加大MOSFET沟道长度的方法优于添加附加并联电容的方法。仿真验证了上述结论。
With the development of radio frequency (RF) communications and the CMOStechnology, it has become a reasonable choice to implement the RF communicationcircuits and systems in CMOS process. The RF front-end circuits in this kind ofmixed-signal systems are required to be able to work under low voltage. Front-ends,especially LNAs for modern RF communications are also required to be low-noiseand highly linear and to fulfill those requirements with low power is among the keytechnologies for the implementation of RF communication systems.
The design of low-voltage, low-power CMOS low noise amplifiers (LNA) isconducted in this thesis and includes:
1. A simple design model and the method to extract its parameters by circuitsimulation and data fitting is proposed based on simplifying the circuit simulationmodel of short channel MOSFET in a specific operation region (strong inversion andsaturation). The large-and small-signal model, and noise model can be derived toanalyze the gain, noise, linearity and power of inductively source-degenerated CMOSLNAs and to predict their simulation results so that the design iterations can bereduced.
2. The contribution of different noise components of MOSFETs in 0.18micrometer process to the noise figure (NF) of the inductively source-degeneratedLNA is calculated and the analytical expression of the NF is derived. It is shown thatdue to the parasitic capacitance NF is still dominated by the channel thermal noisecurrent;therefore, low noise can be achieved with low power dissipation by properlysizing the MOSFET in the input transconductance stage. A low-voltage foldedcascode inductively degenerated LNA is designed and the above analysis is verifiedby simulation.
3. The nonlinearity of the inductively source-degenerated LNA is analyzed withseries expansion method and analytical expressions relating the power and linearity tothe size and bias of the MOSFET are found. Compensation is needed to achieve highlinearity, and different compensation methods are compared. A low-voltage folded
cascode LNA compensated using MOSFET in the triode region is proposed, and thenthe design guides are given. About 5dB input-inferred third-order interception pointpower enhancement at little power cost has been demonstrated by the measurementsof the fabricated IC chip compensated with this technique and designed under thegiven guides.4. The effects of packaging parasitics on the performance of inductivelydegenerated LNAs are analytically studied. It is shown that, with parasitics given, toachieve perfect input matching, high gain and low noise, the capacitance across thegate and source of MOSFET in the input stage should be properly large. Two ways toenlarge the capacitance are compared and using longer channel MOSFET ispreferable to adding an extra parallel capacitor. These observations are verifiedthrough circuit simulation.
引文
[1] Prasad R, Dasilva J S, Arroyo-Fernandez B. Air Interface Access Schemes for Wireless Communications. IEEE Communications Magazine, 1999, 37 (9): 104~115
[2] Layer D H. Digital Radio Takes to the Road. IEEE Spectrum, 2001, 38 (7): 40~46
[3] Behbahani F, Leete J C, Kishigami Y, et al. 2.4-GHz Low-IF Receiver for Wideband WLAN in 0.6-μm CMOS--Architecture and Front-End. IEEE J. Solid-State Circuits, 2000, 35 (12): 1908~1916
[4] Samavati H, Rategh H R, Lee T H. A 5-GHz CMOS Wireless LAN Receiver Front End. IEEE J. Solid-State Circuits, 2000, 35 (5): 765~772
[5] Lee K, Park J, Lee J-W, et al. A Single-Chip 2.4-GHz Direct-Conversion CMOS Receiver for Wireless Local Loop using Multiphase Reduced Frequency Conversion Technique. IEEE J. Solid-State Circuits, 2001, 36 (5): 800~809
[6] Online, available at http://bwrc.eecs.berkeley.edu/Research/Pico_Radio/Default.htm
[7] Haartsen J C, Mattisson S. Bluetooth: a New Low-Power Radio Interface Providing Short-Range Connectivity. Proceedings of the IEEE, 2000, 88 (10): 1651~1661
[8] Rudell J C, Ou J-J, Cho T B, et al. A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Application. IEEE J. Solid-State Circuits, 1997, 32 (12): 2071~2088
[9] Porret A-S, Melly T, Python D, et al. An Ultralow-Power UHF Transceiver Integrated in a Standard Digital CMOS Process: Architecture, Receiver. IEEE J. Solid-State Circuits, 2001. 36 (3): 452~466
[10] Abou-Allam E, Manku T, Ting M, et al. Impact of Technology Scaling on CMOS RF Devices and Circuits. In: Proceedings of IEEE CICC 2000, 2000. 361~363
[11] Tiemeijer L F, Boots H M J, Havens R J, et al. A Record High 150 GHz fmax Realized at 0.18 μm Gate Length in an Industrial RF-CMOS Technology. In: Technical Digest of International Electron Devices Meeting, 2001. 10.4.1~10.4.4
[12] Chen C H, Chang C S, Chao C P, et al. A 90nm CMOS MS/RF Based Foundry SoC Technology Comprising Superb 185GHz ft RFMOS and Versatile, High-Q Passive Components for Cost/Performance Optimization. In: Technical Digest of International Electron Devices Meeting, 2003. 2.5.1~2.5.4
[13] Shahani A R, Shaeffer D K, Lee T H. A 12-mV Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver. IEEE J. Solid-State Circuits, 1997, 32 (12): 2061~2070
[14] Shaeffer D K, Shahani A R, Mohan S S, et al. A 115-mW, 0.5μm CMOS GPS Receiver with Wide Dynamic-Range Active Filters. IEEE J. Solid-State Circuits, 1998, 33 (12): 2219~2231
[15] Darabi H, Khorran S, Chien H-M(Ed), et al. A 2.4-GHz CMOS Transceiver for Bluetooth. IEEE J. Solid-State Circuits, 2001, 36 (12): 2016~2024
[16] Jussila J, Ryynancen J, Kiveskas K, et al. A 22-mA 3.0-dB NF Direct Conversion Receiver for 3G WCDMA. IEEE J. Solid-State Circuits, 2001, 36 (12): 2025~2029
[17] Huang Q. CMOS RF Design-the Low Power Dimension. In: Proceedings of IEEE CICC, 2000. 161~166
[18] Abidi A A, Pottie G J, Kaiser W J. Power-Conscious Design of Wireless Circuits and Systems. Proceedings of the IEEE, 2000, 88 (10): 1528~1545
[19] Enberg J. Simultaneous Input Power Match and Noise Optimization Using Feedback. European Microwave Conference Digest, 1972. 385~389
[20] Meyer R G, Mack W D. A 1-GHz BiCMOS RF Front-End IC. IEEE J. Solid-State Circuits, 1994, 29 (3): 350~355
[21] Ko B K, Lee K. A Comparative Study on the Various Monolithic Low Noise Amplifier Circuit Topologies for RF and Microwave Applications. IEEE J. Solid-State Circuits, 1996, 31 (8): 1220~1225
[22] van der Ziel A. 固体器件及电路中的噪声(彭毅译). 成都:成都电讯工程学院出版社, 1988: 90~112. van der Ziel A. Noise in Solid State Devices and Circuits. John Wiley & Sons, 1986
[23] Ho Y-C, Biyani M, Colvin J, et al. 3V Low Noise Amplifier Implemented Using a 0.8μm CMOS Process with Three Metal Layers for 900MHz Operation. Electronics Letters, 1996, 32(13): 1191~1193
[24] Shaeffer D K, Lee T H. A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier. IEEE J. Solid-State Circuits, 1997, 32 (5): 745~759
[25] Shaeffer D K. The Design and Implementation of Low-Power CMOS Radio Receivers. PhD Thesis. Stanford University, Dec. 1998
[26] Huang Q, Orsatti P, Piazza F. GSM Transceiver Front-End Circuits in 0.25-μm CMOS. IEEE J. Solid-State Circuits, 1999, 34 (3): 292~303
[27] Andreani P, Sj?land H. Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 2001, 48 (9): 835~841
[28] Girlando G, Palmisano G. Noise Figure and Impedance Matching in RF Cascode Amplifiers. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (11): 1388~1396
[29] Chiu H-W, Lu S-S, Lin Y-S. A 2.17-dB NF 5-GHz-Band Monolithic CMOS LNA With 10-mW DC Power Consumption. IEEE T. Microwave Theory and Techniques,2005, 53 (3): 813~824
[30] Triantis D, Birbas A N, Kondis D. Thermal Noise Modeling for Short-Channel MOSFETs. IEEE T. Electron Devices, 1996, 43 (11): 1950~1955
[31] Triantis D P, Birbas A N, Plevridis S E. Induced Gate Noise in MOSFETs Revisited: the Submicron Case. Solid-State Electronics, 1997, 41 (12): 1937~1942
[32] Manku T, Obrecht M, Yi Lin. High-Frequency Dependence of Channel Noise in Short-Channel RF MOSFET's. IEEE Electron Device Letters, 1999, 20 (9): 481~483
[33] Park C H, Park Y J. Modeling of Thermal Noise in Short-Channel MOSFETs at Saturation. Solid-State Electronics, 2000, 44 (11): 2053~2057
[34] Knoblinger G, Klein P, Tiebout M. A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design. IEEE J. Solid-State Circuits, 2001, 36 (5): 831~837
[35] Goo J-S. High Frequency Noise in CMOS Low Noise Amplifiers. PhD Thesis. Stanford University, Aug. 2001
[36] Obrecht M S, Abou-Allam E, Manku T. Diffusion Current and Its Effect on Noise in Submicron MOSFETs. IEEE T. Electron Devices, 2002, 49 (3): 524~526
[37] Chen C-H, Deen M J. Channel Noise Modeling of Deep Submicron MOSFETs. IEEE T. Electron Devices, 2002, 49 (8): 1484-1487
[38] Kraus R, Knoblinger G. Modeling the Gate-Related High-Frequency and Noise Characteristics of Deep-Submicron MOSFETs. In: Proceedings of the IEEE CICC, 2002. 209~212
[39] Scholten A J, Tiemeijer L F, van Langevelde R, et al. Noise Modeling for RF CMOS Circuit Simulation. IEEE T. Electron Devices, 2003, 50 (3): 618~632
[40] Han K, Gil J, Song S-S, et al. Complete High-Frequency Thermal Noise Modeling of Short-Channel MOSFETs and Design of 5.2-GHz Low Noise Amplifier. IEEE J. Solid-State Circuits, 2005, 40 (3): 726~735
[41] Cassan D J, Long J R. A 1-V Transformer-feedback Low-noise Amplifier for 5-GHz Wireless LAN in 0.18-μm CMOS. IEEE J. Solid-State Circuits, 2003, 38 (3):427~435
[42] Long J R, Copeland M A. A 1.9 GHz Low-Voltage Silicon Bipolar Receiver Front-End for Wireless Personal Communications Systems. IEEE J. Solid-State Circuits, 1995, 30 (12): 1438~1448
[43] van der Heijden M P, de Vreede L C N, Burghartz J N. On the Design of Unilateral Dual-Loop Feedback Low-Noise Amplifiers with Simultaneous Noise, Impedance, and IIP3 Match. IEEE J. Solid-State Circuits, 2004, 39 (10): 1727~1736
[44] Allstot D J, Li X, Shekhar S. Design Considerations for CMOS Low Noise Amplifiers. In: Digest Papers of Radio Frequency Integrated Circuits Symposium, 2004, IEEE. 97~100
[45] Taris T, Begueret J B, Lapuyade H, et al. A 1-V 2GHz VLSI CMOS Low Noise Amplifier. In: Digest of Technical Papers of IEEE Radio Frequency Integrated Circuits Symposium, 2003. 123~126
[46] Abou-Allam E, Nisbet J J, Maliepaard M C. Low-Voltage 1.9-GHz Front-End Receiver in 0.5-μm CMOS Technology. IEEE J. Solid-State Circuits, 2001, 36 (10): 1434~1443
[47] Fong K L, Meyer R G. High-frequency Nonlinearity Analysis of Common-Emitter and Differential-Pair Transconductance Stages. IEEE J. Solid-State Circuits, 1998, 33 (4): 548~555
[48] Fong K L. High-frequency Analysis of Linearity Improvement Technique of Common-Emitter Transconductance Stage Using a Low-Frequency-Trap Network. IEEE J. Solid-State Circuits, 2000, 35 (8): 1249~1252
[49] Aparin V, Persico C. Effect of out-of-band Terminations on Intermodulation Distortion in Common-Emitter Circuits. In: Proceedings of IEEE MTT-S, 1999. 977~980
[50] Toole B, Plett C, Cloutier M. RF Circuits Implications of Moderate Inversion Enhanced Linear Region in MOSFETs. IEEE T. Circuits and Systems-I: Regular Papers, 2004, 51 (2): 319~328
[51] Aparin V, Brown G, Larson L E. Linearization of CMOS LNA's via Optimum Gate Biasing. In: Proceedings of the 2004 International Symposium on Circuits and Systems, Vol.4, 2004. 748-751
[52] Popa C, Coada D. A New Linearization Technique for a CMOS Differential Amplifier Using Bulk-Driven Weak Inversion MOS Transistors. In: Proceeding of International Symposium on Signals, Circuits and Systems, Vol.2, 2003. 589~592
[53] Mitrea O, Popa C, Manolescu A M, et al. A Linearization Technique for Radio Frequency CMOS Gilbert-Type Mixers. In: Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, Vol.3, 2003. 1086~1089
[54] Ding Y, Haryani R. A +18dBm IIP3 LNA in 0.35μm CMOS. In: Proceedings of IEEE ISSCC, 2001. 161~162
[55] Lin M, Li Y, Chen H. A Novel IP3 Boosting Technique Using Feedforward Distortion Cancellation Method for 5 GHz CMOS LNA. In: Proceedings of IEEE RFIC 2003
[56] Kim T W, Kim B, Lee K. Highly Linear Receiver Front-End Adopting MOSFET Transconductance Linearization by Multiple Gated Transistors. IEEE J. Solid-State Circuits, 2004, 39 (1): 223~229
[57] Aparin V, Larson L E. Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers. IEEE T. Microwave Theory and Techniques, 2005, 53 (2): 571~581
[58] Tanaka S, Behbahani F, Abidi A A. A Linearization Technique For CMOS RF Power Amplifiers. In: Proceedings of IEEE Symposium on VLSI Circuits, 1997. 93~94
[59] Youn Y-S, Chang J-H, Koh K-J, et al. A 2GHz 16dBm IIP3 Low Noise Amplifier in 0.25μm CMOS Technology. In: Proceedings of IEEE ISSCC 2003
[60] Donnay S, Pieters P, Vaesen K, et al. Chip-Package Codesign of a Low-Power 5-GHz RF Front End. Proceedings of the IEEE, 2000, 88 (10): 1583~1597
[61] Tummala R R, Laskar J. Gigabit Wireless: System-on-a-Package Technology. Proceedings of the IEEE, 2004, 92 (2): 376~387
[62] Chandrasekhar V, Mayaram K. Analysis of CMOS RF LNAs with ESD protection. In: Proceedings of the IEEE ISCAS 2002. Phoenix, Arizona: IEEE Press, 2002. 799~802
[63] Leroux P, Janssens J, Steyaert M. A 0.8-dB NF ESD-protected 9-mW CMOS LNA operating at 1.23GHz. IEEE J. Solid-State Circuits, 2002, 37 (6): 760~765
[64] Sivonen P, Kangasama S, P?rssinen A. Analysis of Packaging Effects and Optimization in Inductively Degenerated Common-Emitter Low-Noise Amplifiers. IEEE T. Microwave Theory and Techniques, 2003, 51 (4): 1220~1226
[65] Tsui H-Y, Lau J. SPICE Simulation and Tradeoffs of CMOS LNA Performance with Source-Degeneration Inductor. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 2000, 47 (1): 62~65
[66] Ellinger Frank, Barras D, Schmatz M, et al. A Low Power DC-7.8 GHz BiCMOS LNA for UWB and Optical Communication. In: IEEE MTT-S International Microwave Symposium Digest, Vol.1, 2004. 13~16
[67] Vishwakarma S, Jung S, Joo Y. Ultra Wideband CMOS Low Noise Amplifier with Active Input Matching. In: Joint UWBST and IWUWBS, 2004. 415~419
[68] Shi B, Chia Y W. Design of a SiGe Low Noise Amplifier for 3.1-10.6 GHz Ultra-Wideband Radio. In: Proceedings of the IEEE International Symposium on Circuits and Systems, 2004. I101~I104
[69] Ismail A, Abidi A A. A 3-10-GHz Low-Noise Amplifier with Wideband LC-Ladder Matching Network. IEEE J. Solid-State Circuits, 2004, 39 (12): 2269~2277
[70] Guan X, Hajimiri A. A 24-GHz CMOS Front-End. IEEE J. Solid-State Circuits, 2004, 39 (2): 368~373
[71] Samavati H, Rategh H R, Lee T H. A 5-GHz CMOS Wireless LAN Receiver Front End. . IEEE J. Solid-State Circuits, 2000, 35 (5): 765~772
[72] Nguyen T-K, Oh N-J, Cha C-Y, et al. Image-Rejection CMOS Low-Noise Amplifier Design Optimization Techniques. IEEE T. Microwave Theory and Techniques, 2005, 53 (2): 538~547
[73] Hashemi H, Hajimiri A. Concurrent Multiband Low-Noise Amplifiers-Theory, Design, and Applications. IEEE T. Microwave Theory and Techniques, 2002, 50 (1): 288~301
[74] Li Z, Quintal R, O K K. A Dual-Band CMOS Front-End with Two Gain Modes for Wireless LAN Applications. IEEE J. Solid-State Circuits, 2004, 39 (11): 2069~2073
[75] online, available at http://www-device.eecs.berkeley.edu/~bsim3/latenews.html
[76] online, available at http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
[77] online, available at http://www.semiconductors.philips.com/Philips_Models/mos_models/model9/index.html
[77] online, available at http://www.semiconductors.philips.com/Philips_Models/mos_models/model11/code_history/index.html
[79] Enz C C, Krummenacher F, Vittoz E A. An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications. Analog Integrated Circuits and Signal Processing, 1995, 8 (1): 83~114
[80] online, available at http://legwww.epfl.ch/research/pdf/ekvf.pdf
[81] online, available at http://legwww.epfl.ch/ekv/pdf/ekv_v262.pdf
[82] Enz C. An MOS Transistor Model for RF IC Design Valid in All Regions of Operation. IEEE T. Microwave Theory and Techniques, 2002, 50 (1): 342~359
[83] Gray P R, Hurst P J, Lewis S H, et al. Analysis and Design of Analog Integrated Circuits, 4th Ed. New York : John Wiley & Sons, 2001
[84] Wambacq P, Gielen G E, Kinget P R, et al. High-Frequency Distortion Analysis of Analog integrated Circuits. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (3): 335~345
[85] Wambacq P, Sansen W. Distortion analysis of Analog Integrated Circuits. Kluwer Academic, 1998
[86] van Langevelde R, Klaassen F M. Effect of Gate-Field Dependent Mobility Degradation on Distortion Analysis in MOSFET's. IEEE T. Electron Devices, 1997, 44 (11): 2044~2052
[87] Lee T H. The Design of CMOS Integrated Circuits. Cambridge University Press, 1998
[88] Tsividis Y. Operation and Modeling of the MOS Transistor, 2nd Ed.. New York: McGraw-Hill. 1999. 440~508
[89] Razavi B, Yan R-H, Lee K F. Impact of Distributed Gate Resistance on the Performance of MOS Devices. IEEE T. Circuits and Systems I: Fundamental Theory and Applications, 1994, 41 (11): 750~754
[90] Yee D G-W. A Design Methodology for Highly-Integrated Low-Power Receivers for Wireless Communications. PhD Thesis., University of California, Berkeley, 2001
[91] Wolf S, Tauber R N. Silicon Processing for the VLSI Era, Vol.3: The Submicron MOSFET. Sunset Beach, Calif.: Lattice Press, 1995
[92] Abidi A A. High-Frequency Noise Measurements on FET's with Small Dimensions. IEEE T. Electron Devices, 1986, 33 (11): 1801~1805
[93] Darabi H, Abidi A A. A 4.5-mW 900-MHz CMOS Receiver for Wireless Paging. IEEE J. Solid-State Circuits, 2000, 35 (8): 1085~1096
[94] Bruccoleri F, Klumperink E A M, Nauta B. Wide-band CMOS Low-noise Amplifier Exploiting Thermal Noise Canceling. IEEE J. Solid-State Circuits, 2004, 39 (2): 275~282
[95] Tsang T K K, El-Gamal M N. Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA. In: Proceedings of IEEE ISCAS, Vol.4, 2002. 795~798
[96] Razavi B. RF Microelectronics. Prentice Hall, 1998
[97] Maas S A. Nonlinear Microwave and RF Circuits, 2nd Ed. Artech House, 2003
[98] Weiner D D, Spina J F. Sinusoidal Analysis and Modeling of Weakly Nonlinear Circuits. van Nostrand Reinhold Company, 1980
[99] Brinkhoff J, Parker A E. Effect of Baseband Impedance on FET Intermodulation. IEEE T. Microwave Theory and Techniques, 2003, 51 (3): 1045~1051
[100] Feng C-H, Jonsson F, Ismail M, et al. Analysis of Nonlinearities in RF CMOS Amplifiers. In: Proceedings of 6th IEEE International Conference on Electronics, Circuits and Systems, 1999. IEEE Press, Vol.1, 1999. 137~140
[101] Biber C E, Schmatz M L, Morf T, et al. A Nonlinear Microwave MOSFET Model for SPICE Simulators. IEEE T. Microwave Theory and Techniques, 1998, 46 (5): 604~610
[102] Kobb B Z. Wireless Spectrum Finder. McGrall-Hill, 2001
[103] Aparin V, Larson L E. Analysis and Reduction of Cross-Modulation Distortion in CDMA Receivers. IEEE T. Microwave Theory and Techniques, 2003, 51 (5): 1591~1602
[104] Gilbert B. A Precise Four-Quadrant Multiplier with Subnanosecond Response. IEEE J Solid-State Circuits, 1968, 3 (4): 365~373
[105] Fong K L, Meyer R G. Monolithic RF Active Mixer Design. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (3): 231~239
[106] Razavi B. CMOS Technology Characterization for Analog and RF Design. IEEE J. Solid-State Circuits, 1999, 34 (3): 268~276
[107] Larson L E. Silicon Technology Tradeoffs for Radio-Frequency/Mixed-Signal "Systems-on-a-Chip". IEEE T. Electron Devices, 2003, 50 (3): 683~699
[108] Sansen W. Distortion in Elementary Transistor Circuits. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (3): 315~324
[109] Maas S A, Nelson B L, Tait D L. Intermodulation in Heterojunction Bipolar Transistors. IEEE T. Microwave Theory and Techniques, 1992, 40 (3): 442~447
[110] Lee T-L, Cheng Y. MOSFET HF Distortion Behavior and Modeling for RFIC Design. In: Proceedings of IEEE CICC, 2003. 138~142
[111] Lee T-L, Cheng Y. High-Frequency Characterization and Modeling of Distortion Behavior of MOSFETs for RF IC Design. IEEE J. Solid-State Circuits, 2004, 39 (9): 1407~1414
[112] Xin C, Sánchez-Sinencio E. A Linearization Technique For RF Low Noise Amplifier. In: Proceedings of IEEE ISCAS 2004
[113] van Langevelde R, Klaassen F M. Accurate Drain Conductance Modeling for Distortion Analysis in MOSFETs. In: Proceedings of IEEE IEDM 1997. 313~316
[114] Kang S, Choi B, Kim B. Linearity Analysis of CMOS for RF Application. IEEE T. Microwave theory and Techniques, 2003, 51 (3): 972~977
[115] online, available at http://www.designers-guide.com/Analysis/intercept-point.pdf
[116] online available at http://www.amkor.com/Products/all_datasheets/LQFP.pdf
[117] Gramegna G, Paparo M, Erratico P G, et al. A sub-1-dB ±2.3-kV ESD-protected 900-MHz CMOS LNA. IEEE J. Solid-State Circuits, 2001, 36 (7): 1010~1017
[118] Goo J-S, Ahn H-T, Ladwig D J, et al. A Noise Optimization Technique for Integrated Low-Noise Amplifiers. IEEE J. Solid-State Circuits, 2002, 37 (8): 994~1002
[119] Colvin J T, Bhatia S S, Kenneth K O. Effects of Substrate Resistances on LNA Performance and Bondpad Structure for Reducing the Effects in a Silicon Bipolar Technology. IEEE J. Solid-State Circuits, 1999, 34 (9): 1339~1344
[120] Lam S, Mok P K T, Ko P K, et al. High-Isolation Bonding Pad Design for Silicon RFIC up to 20 GHz. IEEE Electron Device Letters, 2003, 24 (9): 601~603
[121] Vinson J E, Liou J J. Electrostatic Discharge in Semiconductor Devices: an Overview. Proceedings of the IEEE, 1998, 86 (2): 399~420
[122] Vinson J E, Liou J J. Electrostatic Discharge in Semiconductor Devices: Protection Techniques. Proceedings of the IEEE, 2000, 88 (12): 1878~1902
[123] Gong K, Feng H, Zhan R, et al. A Study of Parasitic effects of ESD Protection on RF ICs. IEEE T. Microwave Theory and Techniques, 2002, 50 (1): 393~402
[124] Kleveland B, Maloney T J, Morgan I, Madden L, et al. Distributed ESD Protection for High-Speed Integrated Circuits. IEEE Electron Devices Letters, 2000, 21 (8): 390~392
[125] Wang A Z, Feng H G, Gong K, et al. On-Chip ESD Protection Design for Integrated Circuits: an Overview for IC Designers. Microelectronics Journal, 2001, 32 (9): 733~747
[126] Ito C, Banerjee K, Dutton R W. Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs. IEEE T. Electron Devices, 2002, 49 (8): 1444~1454
[127] Galal S, Razavi B. Broadband ESD Protection Circuits in CMOS Technology. IEEE J. Solid-State Circuits, 2003, 38 (12): 2334~2340
[128] Richier C, Salome P, Mabboux G, et al. Investigation on Different ESD Protection Strategies Devoted to 3.3V RF Applications (2GHz) in 0.18um CMOS Process. In: Proceedings of EOS/ESD Symposium 2000. Anaheim, CA: ESD Association, 2000. 251~259
[129] Wang A Z H. On-chip ESD Protection for Integrated Circuits: an IC Design Perspective. Kluwer Academic Publishers, 2002
[130] online, available at http://www.amkor.com/services/electrical/newabstr.pdf
[131] Rogers J, Plett C. Radio Frequency Integrated Circuit Design, Artech House,2003
[132] Nguyen T-K, Kim C-H, Ihm G-J, et al. CMOS Low-Noise Amplifier Design Optimization Techniques. IEEE T. Microwave Theory and Techniques, 2004, 52 (5): 1433~1442
[133] Janssens J, Steyaert M. Optimum MOS Power Matching by Exploiting Non-quasistatic Effect. IEE Electronics Letters, 1999, 35 (8): 672~673
[134] Janssens J, Steyaert M. MOS Noise Performance under Impedance Matching Constraints. IEE Electronics Letters, 1999, 35 (15): 1278~1280
[2] Layer D H. Digital Radio Takes to the Road. IEEE Spectrum, 2001, 38 (7): 40~46
[3] Behbahani F, Leete J C, Kishigami Y, et al. 2.4-GHz Low-IF Receiver for Wideband WLAN in 0.6-μm CMOS--Architecture and Front-End. IEEE J. Solid-State Circuits, 2000, 35 (12): 1908~1916
[4] Samavati H, Rategh H R, Lee T H. A 5-GHz CMOS Wireless LAN Receiver Front End. IEEE J. Solid-State Circuits, 2000, 35 (5): 765~772
[5] Lee K, Park J, Lee J-W, et al. A Single-Chip 2.4-GHz Direct-Conversion CMOS Receiver for Wireless Local Loop using Multiphase Reduced Frequency Conversion Technique. IEEE J. Solid-State Circuits, 2001, 36 (5): 800~809
[6] Online, available at http://bwrc.eecs.berkeley.edu/Research/Pico_Radio/Default.htm
[7] Haartsen J C, Mattisson S. Bluetooth: a New Low-Power Radio Interface Providing Short-Range Connectivity. Proceedings of the IEEE, 2000, 88 (10): 1651~1661
[8] Rudell J C, Ou J-J, Cho T B, et al. A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Application. IEEE J. Solid-State Circuits, 1997, 32 (12): 2071~2088
[9] Porret A-S, Melly T, Python D, et al. An Ultralow-Power UHF Transceiver Integrated in a Standard Digital CMOS Process: Architecture, Receiver. IEEE J. Solid-State Circuits, 2001. 36 (3): 452~466
[10] Abou-Allam E, Manku T, Ting M, et al. Impact of Technology Scaling on CMOS RF Devices and Circuits. In: Proceedings of IEEE CICC 2000, 2000. 361~363
[11] Tiemeijer L F, Boots H M J, Havens R J, et al. A Record High 150 GHz fmax Realized at 0.18 μm Gate Length in an Industrial RF-CMOS Technology. In: Technical Digest of International Electron Devices Meeting, 2001. 10.4.1~10.4.4
[12] Chen C H, Chang C S, Chao C P, et al. A 90nm CMOS MS/RF Based Foundry SoC Technology Comprising Superb 185GHz ft RFMOS and Versatile, High-Q Passive Components for Cost/Performance Optimization. In: Technical Digest of International Electron Devices Meeting, 2003. 2.5.1~2.5.4
[13] Shahani A R, Shaeffer D K, Lee T H. A 12-mV Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver. IEEE J. Solid-State Circuits, 1997, 32 (12): 2061~2070
[14] Shaeffer D K, Shahani A R, Mohan S S, et al. A 115-mW, 0.5μm CMOS GPS Receiver with Wide Dynamic-Range Active Filters. IEEE J. Solid-State Circuits, 1998, 33 (12): 2219~2231
[15] Darabi H, Khorran S, Chien H-M(Ed), et al. A 2.4-GHz CMOS Transceiver for Bluetooth. IEEE J. Solid-State Circuits, 2001, 36 (12): 2016~2024
[16] Jussila J, Ryynancen J, Kiveskas K, et al. A 22-mA 3.0-dB NF Direct Conversion Receiver for 3G WCDMA. IEEE J. Solid-State Circuits, 2001, 36 (12): 2025~2029
[17] Huang Q. CMOS RF Design-the Low Power Dimension. In: Proceedings of IEEE CICC, 2000. 161~166
[18] Abidi A A, Pottie G J, Kaiser W J. Power-Conscious Design of Wireless Circuits and Systems. Proceedings of the IEEE, 2000, 88 (10): 1528~1545
[19] Enberg J. Simultaneous Input Power Match and Noise Optimization Using Feedback. European Microwave Conference Digest, 1972. 385~389
[20] Meyer R G, Mack W D. A 1-GHz BiCMOS RF Front-End IC. IEEE J. Solid-State Circuits, 1994, 29 (3): 350~355
[21] Ko B K, Lee K. A Comparative Study on the Various Monolithic Low Noise Amplifier Circuit Topologies for RF and Microwave Applications. IEEE J. Solid-State Circuits, 1996, 31 (8): 1220~1225
[22] van der Ziel A. 固体器件及电路中的噪声(彭毅译). 成都:成都电讯工程学院出版社, 1988: 90~112. van der Ziel A. Noise in Solid State Devices and Circuits. John Wiley & Sons, 1986
[23] Ho Y-C, Biyani M, Colvin J, et al. 3V Low Noise Amplifier Implemented Using a 0.8μm CMOS Process with Three Metal Layers for 900MHz Operation. Electronics Letters, 1996, 32(13): 1191~1193
[24] Shaeffer D K, Lee T H. A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier. IEEE J. Solid-State Circuits, 1997, 32 (5): 745~759
[25] Shaeffer D K. The Design and Implementation of Low-Power CMOS Radio Receivers. PhD Thesis. Stanford University, Dec. 1998
[26] Huang Q, Orsatti P, Piazza F. GSM Transceiver Front-End Circuits in 0.25-μm CMOS. IEEE J. Solid-State Circuits, 1999, 34 (3): 292~303
[27] Andreani P, Sj?land H. Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 2001, 48 (9): 835~841
[28] Girlando G, Palmisano G. Noise Figure and Impedance Matching in RF Cascode Amplifiers. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (11): 1388~1396
[29] Chiu H-W, Lu S-S, Lin Y-S. A 2.17-dB NF 5-GHz-Band Monolithic CMOS LNA With 10-mW DC Power Consumption. IEEE T. Microwave Theory and Techniques,2005, 53 (3): 813~824
[30] Triantis D, Birbas A N, Kondis D. Thermal Noise Modeling for Short-Channel MOSFETs. IEEE T. Electron Devices, 1996, 43 (11): 1950~1955
[31] Triantis D P, Birbas A N, Plevridis S E. Induced Gate Noise in MOSFETs Revisited: the Submicron Case. Solid-State Electronics, 1997, 41 (12): 1937~1942
[32] Manku T, Obrecht M, Yi Lin. High-Frequency Dependence of Channel Noise in Short-Channel RF MOSFET's. IEEE Electron Device Letters, 1999, 20 (9): 481~483
[33] Park C H, Park Y J. Modeling of Thermal Noise in Short-Channel MOSFETs at Saturation. Solid-State Electronics, 2000, 44 (11): 2053~2057
[34] Knoblinger G, Klein P, Tiebout M. A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design. IEEE J. Solid-State Circuits, 2001, 36 (5): 831~837
[35] Goo J-S. High Frequency Noise in CMOS Low Noise Amplifiers. PhD Thesis. Stanford University, Aug. 2001
[36] Obrecht M S, Abou-Allam E, Manku T. Diffusion Current and Its Effect on Noise in Submicron MOSFETs. IEEE T. Electron Devices, 2002, 49 (3): 524~526
[37] Chen C-H, Deen M J. Channel Noise Modeling of Deep Submicron MOSFETs. IEEE T. Electron Devices, 2002, 49 (8): 1484-1487
[38] Kraus R, Knoblinger G. Modeling the Gate-Related High-Frequency and Noise Characteristics of Deep-Submicron MOSFETs. In: Proceedings of the IEEE CICC, 2002. 209~212
[39] Scholten A J, Tiemeijer L F, van Langevelde R, et al. Noise Modeling for RF CMOS Circuit Simulation. IEEE T. Electron Devices, 2003, 50 (3): 618~632
[40] Han K, Gil J, Song S-S, et al. Complete High-Frequency Thermal Noise Modeling of Short-Channel MOSFETs and Design of 5.2-GHz Low Noise Amplifier. IEEE J. Solid-State Circuits, 2005, 40 (3): 726~735
[41] Cassan D J, Long J R. A 1-V Transformer-feedback Low-noise Amplifier for 5-GHz Wireless LAN in 0.18-μm CMOS. IEEE J. Solid-State Circuits, 2003, 38 (3):427~435
[42] Long J R, Copeland M A. A 1.9 GHz Low-Voltage Silicon Bipolar Receiver Front-End for Wireless Personal Communications Systems. IEEE J. Solid-State Circuits, 1995, 30 (12): 1438~1448
[43] van der Heijden M P, de Vreede L C N, Burghartz J N. On the Design of Unilateral Dual-Loop Feedback Low-Noise Amplifiers with Simultaneous Noise, Impedance, and IIP3 Match. IEEE J. Solid-State Circuits, 2004, 39 (10): 1727~1736
[44] Allstot D J, Li X, Shekhar S. Design Considerations for CMOS Low Noise Amplifiers. In: Digest Papers of Radio Frequency Integrated Circuits Symposium, 2004, IEEE. 97~100
[45] Taris T, Begueret J B, Lapuyade H, et al. A 1-V 2GHz VLSI CMOS Low Noise Amplifier. In: Digest of Technical Papers of IEEE Radio Frequency Integrated Circuits Symposium, 2003. 123~126
[46] Abou-Allam E, Nisbet J J, Maliepaard M C. Low-Voltage 1.9-GHz Front-End Receiver in 0.5-μm CMOS Technology. IEEE J. Solid-State Circuits, 2001, 36 (10): 1434~1443
[47] Fong K L, Meyer R G. High-frequency Nonlinearity Analysis of Common-Emitter and Differential-Pair Transconductance Stages. IEEE J. Solid-State Circuits, 1998, 33 (4): 548~555
[48] Fong K L. High-frequency Analysis of Linearity Improvement Technique of Common-Emitter Transconductance Stage Using a Low-Frequency-Trap Network. IEEE J. Solid-State Circuits, 2000, 35 (8): 1249~1252
[49] Aparin V, Persico C. Effect of out-of-band Terminations on Intermodulation Distortion in Common-Emitter Circuits. In: Proceedings of IEEE MTT-S, 1999. 977~980
[50] Toole B, Plett C, Cloutier M. RF Circuits Implications of Moderate Inversion Enhanced Linear Region in MOSFETs. IEEE T. Circuits and Systems-I: Regular Papers, 2004, 51 (2): 319~328
[51] Aparin V, Brown G, Larson L E. Linearization of CMOS LNA's via Optimum Gate Biasing. In: Proceedings of the 2004 International Symposium on Circuits and Systems, Vol.4, 2004. 748-751
[52] Popa C, Coada D. A New Linearization Technique for a CMOS Differential Amplifier Using Bulk-Driven Weak Inversion MOS Transistors. In: Proceeding of International Symposium on Signals, Circuits and Systems, Vol.2, 2003. 589~592
[53] Mitrea O, Popa C, Manolescu A M, et al. A Linearization Technique for Radio Frequency CMOS Gilbert-Type Mixers. In: Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, Vol.3, 2003. 1086~1089
[54] Ding Y, Haryani R. A +18dBm IIP3 LNA in 0.35μm CMOS. In: Proceedings of IEEE ISSCC, 2001. 161~162
[55] Lin M, Li Y, Chen H. A Novel IP3 Boosting Technique Using Feedforward Distortion Cancellation Method for 5 GHz CMOS LNA. In: Proceedings of IEEE RFIC 2003
[56] Kim T W, Kim B, Lee K. Highly Linear Receiver Front-End Adopting MOSFET Transconductance Linearization by Multiple Gated Transistors. IEEE J. Solid-State Circuits, 2004, 39 (1): 223~229
[57] Aparin V, Larson L E. Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers. IEEE T. Microwave Theory and Techniques, 2005, 53 (2): 571~581
[58] Tanaka S, Behbahani F, Abidi A A. A Linearization Technique For CMOS RF Power Amplifiers. In: Proceedings of IEEE Symposium on VLSI Circuits, 1997. 93~94
[59] Youn Y-S, Chang J-H, Koh K-J, et al. A 2GHz 16dBm IIP3 Low Noise Amplifier in 0.25μm CMOS Technology. In: Proceedings of IEEE ISSCC 2003
[60] Donnay S, Pieters P, Vaesen K, et al. Chip-Package Codesign of a Low-Power 5-GHz RF Front End. Proceedings of the IEEE, 2000, 88 (10): 1583~1597
[61] Tummala R R, Laskar J. Gigabit Wireless: System-on-a-Package Technology. Proceedings of the IEEE, 2004, 92 (2): 376~387
[62] Chandrasekhar V, Mayaram K. Analysis of CMOS RF LNAs with ESD protection. In: Proceedings of the IEEE ISCAS 2002. Phoenix, Arizona: IEEE Press, 2002. 799~802
[63] Leroux P, Janssens J, Steyaert M. A 0.8-dB NF ESD-protected 9-mW CMOS LNA operating at 1.23GHz. IEEE J. Solid-State Circuits, 2002, 37 (6): 760~765
[64] Sivonen P, Kangasama S, P?rssinen A. Analysis of Packaging Effects and Optimization in Inductively Degenerated Common-Emitter Low-Noise Amplifiers. IEEE T. Microwave Theory and Techniques, 2003, 51 (4): 1220~1226
[65] Tsui H-Y, Lau J. SPICE Simulation and Tradeoffs of CMOS LNA Performance with Source-Degeneration Inductor. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 2000, 47 (1): 62~65
[66] Ellinger Frank, Barras D, Schmatz M, et al. A Low Power DC-7.8 GHz BiCMOS LNA for UWB and Optical Communication. In: IEEE MTT-S International Microwave Symposium Digest, Vol.1, 2004. 13~16
[67] Vishwakarma S, Jung S, Joo Y. Ultra Wideband CMOS Low Noise Amplifier with Active Input Matching. In: Joint UWBST and IWUWBS, 2004. 415~419
[68] Shi B, Chia Y W. Design of a SiGe Low Noise Amplifier for 3.1-10.6 GHz Ultra-Wideband Radio. In: Proceedings of the IEEE International Symposium on Circuits and Systems, 2004. I101~I104
[69] Ismail A, Abidi A A. A 3-10-GHz Low-Noise Amplifier with Wideband LC-Ladder Matching Network. IEEE J. Solid-State Circuits, 2004, 39 (12): 2269~2277
[70] Guan X, Hajimiri A. A 24-GHz CMOS Front-End. IEEE J. Solid-State Circuits, 2004, 39 (2): 368~373
[71] Samavati H, Rategh H R, Lee T H. A 5-GHz CMOS Wireless LAN Receiver Front End. . IEEE J. Solid-State Circuits, 2000, 35 (5): 765~772
[72] Nguyen T-K, Oh N-J, Cha C-Y, et al. Image-Rejection CMOS Low-Noise Amplifier Design Optimization Techniques. IEEE T. Microwave Theory and Techniques, 2005, 53 (2): 538~547
[73] Hashemi H, Hajimiri A. Concurrent Multiband Low-Noise Amplifiers-Theory, Design, and Applications. IEEE T. Microwave Theory and Techniques, 2002, 50 (1): 288~301
[74] Li Z, Quintal R, O K K. A Dual-Band CMOS Front-End with Two Gain Modes for Wireless LAN Applications. IEEE J. Solid-State Circuits, 2004, 39 (11): 2069~2073
[75] online, available at http://www-device.eecs.berkeley.edu/~bsim3/latenews.html
[76] online, available at http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
[77] online, available at http://www.semiconductors.philips.com/Philips_Models/mos_models/model9/index.html
[77] online, available at http://www.semiconductors.philips.com/Philips_Models/mos_models/model11/code_history/index.html
[79] Enz C C, Krummenacher F, Vittoz E A. An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications. Analog Integrated Circuits and Signal Processing, 1995, 8 (1): 83~114
[80] online, available at http://legwww.epfl.ch/research/pdf/ekvf.pdf
[81] online, available at http://legwww.epfl.ch/ekv/pdf/ekv_v262.pdf
[82] Enz C. An MOS Transistor Model for RF IC Design Valid in All Regions of Operation. IEEE T. Microwave Theory and Techniques, 2002, 50 (1): 342~359
[83] Gray P R, Hurst P J, Lewis S H, et al. Analysis and Design of Analog Integrated Circuits, 4th Ed. New York : John Wiley & Sons, 2001
[84] Wambacq P, Gielen G E, Kinget P R, et al. High-Frequency Distortion Analysis of Analog integrated Circuits. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (3): 335~345
[85] Wambacq P, Sansen W. Distortion analysis of Analog Integrated Circuits. Kluwer Academic, 1998
[86] van Langevelde R, Klaassen F M. Effect of Gate-Field Dependent Mobility Degradation on Distortion Analysis in MOSFET's. IEEE T. Electron Devices, 1997, 44 (11): 2044~2052
[87] Lee T H. The Design of CMOS Integrated Circuits. Cambridge University Press, 1998
[88] Tsividis Y. Operation and Modeling of the MOS Transistor, 2nd Ed.. New York: McGraw-Hill. 1999. 440~508
[89] Razavi B, Yan R-H, Lee K F. Impact of Distributed Gate Resistance on the Performance of MOS Devices. IEEE T. Circuits and Systems I: Fundamental Theory and Applications, 1994, 41 (11): 750~754
[90] Yee D G-W. A Design Methodology for Highly-Integrated Low-Power Receivers for Wireless Communications. PhD Thesis., University of California, Berkeley, 2001
[91] Wolf S, Tauber R N. Silicon Processing for the VLSI Era, Vol.3: The Submicron MOSFET. Sunset Beach, Calif.: Lattice Press, 1995
[92] Abidi A A. High-Frequency Noise Measurements on FET's with Small Dimensions. IEEE T. Electron Devices, 1986, 33 (11): 1801~1805
[93] Darabi H, Abidi A A. A 4.5-mW 900-MHz CMOS Receiver for Wireless Paging. IEEE J. Solid-State Circuits, 2000, 35 (8): 1085~1096
[94] Bruccoleri F, Klumperink E A M, Nauta B. Wide-band CMOS Low-noise Amplifier Exploiting Thermal Noise Canceling. IEEE J. Solid-State Circuits, 2004, 39 (2): 275~282
[95] Tsang T K K, El-Gamal M N. Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA. In: Proceedings of IEEE ISCAS, Vol.4, 2002. 795~798
[96] Razavi B. RF Microelectronics. Prentice Hall, 1998
[97] Maas S A. Nonlinear Microwave and RF Circuits, 2nd Ed. Artech House, 2003
[98] Weiner D D, Spina J F. Sinusoidal Analysis and Modeling of Weakly Nonlinear Circuits. van Nostrand Reinhold Company, 1980
[99] Brinkhoff J, Parker A E. Effect of Baseband Impedance on FET Intermodulation. IEEE T. Microwave Theory and Techniques, 2003, 51 (3): 1045~1051
[100] Feng C-H, Jonsson F, Ismail M, et al. Analysis of Nonlinearities in RF CMOS Amplifiers. In: Proceedings of 6th IEEE International Conference on Electronics, Circuits and Systems, 1999. IEEE Press, Vol.1, 1999. 137~140
[101] Biber C E, Schmatz M L, Morf T, et al. A Nonlinear Microwave MOSFET Model for SPICE Simulators. IEEE T. Microwave Theory and Techniques, 1998, 46 (5): 604~610
[102] Kobb B Z. Wireless Spectrum Finder. McGrall-Hill, 2001
[103] Aparin V, Larson L E. Analysis and Reduction of Cross-Modulation Distortion in CDMA Receivers. IEEE T. Microwave Theory and Techniques, 2003, 51 (5): 1591~1602
[104] Gilbert B. A Precise Four-Quadrant Multiplier with Subnanosecond Response. IEEE J Solid-State Circuits, 1968, 3 (4): 365~373
[105] Fong K L, Meyer R G. Monolithic RF Active Mixer Design. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (3): 231~239
[106] Razavi B. CMOS Technology Characterization for Analog and RF Design. IEEE J. Solid-State Circuits, 1999, 34 (3): 268~276
[107] Larson L E. Silicon Technology Tradeoffs for Radio-Frequency/Mixed-Signal "Systems-on-a-Chip". IEEE T. Electron Devices, 2003, 50 (3): 683~699
[108] Sansen W. Distortion in Elementary Transistor Circuits. IEEE T. Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46 (3): 315~324
[109] Maas S A, Nelson B L, Tait D L. Intermodulation in Heterojunction Bipolar Transistors. IEEE T. Microwave Theory and Techniques, 1992, 40 (3): 442~447
[110] Lee T-L, Cheng Y. MOSFET HF Distortion Behavior and Modeling for RFIC Design. In: Proceedings of IEEE CICC, 2003. 138~142
[111] Lee T-L, Cheng Y. High-Frequency Characterization and Modeling of Distortion Behavior of MOSFETs for RF IC Design. IEEE J. Solid-State Circuits, 2004, 39 (9): 1407~1414
[112] Xin C, Sánchez-Sinencio E. A Linearization Technique For RF Low Noise Amplifier. In: Proceedings of IEEE ISCAS 2004
[113] van Langevelde R, Klaassen F M. Accurate Drain Conductance Modeling for Distortion Analysis in MOSFETs. In: Proceedings of IEEE IEDM 1997. 313~316
[114] Kang S, Choi B, Kim B. Linearity Analysis of CMOS for RF Application. IEEE T. Microwave theory and Techniques, 2003, 51 (3): 972~977
[115] online, available at http://www.designers-guide.com/Analysis/intercept-point.pdf
[116] online available at http://www.amkor.com/Products/all_datasheets/LQFP.pdf
[117] Gramegna G, Paparo M, Erratico P G, et al. A sub-1-dB ±2.3-kV ESD-protected 900-MHz CMOS LNA. IEEE J. Solid-State Circuits, 2001, 36 (7): 1010~1017
[118] Goo J-S, Ahn H-T, Ladwig D J, et al. A Noise Optimization Technique for Integrated Low-Noise Amplifiers. IEEE J. Solid-State Circuits, 2002, 37 (8): 994~1002
[119] Colvin J T, Bhatia S S, Kenneth K O. Effects of Substrate Resistances on LNA Performance and Bondpad Structure for Reducing the Effects in a Silicon Bipolar Technology. IEEE J. Solid-State Circuits, 1999, 34 (9): 1339~1344
[120] Lam S, Mok P K T, Ko P K, et al. High-Isolation Bonding Pad Design for Silicon RFIC up to 20 GHz. IEEE Electron Device Letters, 2003, 24 (9): 601~603
[121] Vinson J E, Liou J J. Electrostatic Discharge in Semiconductor Devices: an Overview. Proceedings of the IEEE, 1998, 86 (2): 399~420
[122] Vinson J E, Liou J J. Electrostatic Discharge in Semiconductor Devices: Protection Techniques. Proceedings of the IEEE, 2000, 88 (12): 1878~1902
[123] Gong K, Feng H, Zhan R, et al. A Study of Parasitic effects of ESD Protection on RF ICs. IEEE T. Microwave Theory and Techniques, 2002, 50 (1): 393~402
[124] Kleveland B, Maloney T J, Morgan I, Madden L, et al. Distributed ESD Protection for High-Speed Integrated Circuits. IEEE Electron Devices Letters, 2000, 21 (8): 390~392
[125] Wang A Z, Feng H G, Gong K, et al. On-Chip ESD Protection Design for Integrated Circuits: an Overview for IC Designers. Microelectronics Journal, 2001, 32 (9): 733~747
[126] Ito C, Banerjee K, Dutton R W. Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs. IEEE T. Electron Devices, 2002, 49 (8): 1444~1454
[127] Galal S, Razavi B. Broadband ESD Protection Circuits in CMOS Technology. IEEE J. Solid-State Circuits, 2003, 38 (12): 2334~2340
[128] Richier C, Salome P, Mabboux G, et al. Investigation on Different ESD Protection Strategies Devoted to 3.3V RF Applications (2GHz) in 0.18um CMOS Process. In: Proceedings of EOS/ESD Symposium 2000. Anaheim, CA: ESD Association, 2000. 251~259
[129] Wang A Z H. On-chip ESD Protection for Integrated Circuits: an IC Design Perspective. Kluwer Academic Publishers, 2002
[130] online, available at http://www.amkor.com/services/electrical/newabstr.pdf
[131] Rogers J, Plett C. Radio Frequency Integrated Circuit Design, Artech House,2003
[132] Nguyen T-K, Kim C-H, Ihm G-J, et al. CMOS Low-Noise Amplifier Design Optimization Techniques. IEEE T. Microwave Theory and Techniques, 2004, 52 (5): 1433~1442
[133] Janssens J, Steyaert M. Optimum MOS Power Matching by Exploiting Non-quasistatic Effect. IEE Electronics Letters, 1999, 35 (8): 672~673
[134] Janssens J, Steyaert M. MOS Noise Performance under Impedance Matching Constraints. IEE Electronics Letters, 1999, 35 (15): 1278~1280