低功耗高性能采样保持电路的研究与设计
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摘要
近年来,随着通信系统和消费类电子设备的发展,作为VLSI数字信号处理系统中重要模块的模/数转换器(ADC)在制造工艺、结构、性能上都有了很大的进步,正在朝着低压、低功耗、高速和高分辨率的方向发展。采样/保持电路(S/H)作为ADC中的关键单元电路,其线性度、功耗、速度和精度将直接影响到ADC系统的指标。
本文分别从S/H架构、采样开关及其误差、S/H和运算放大器优化设计和S/H版图设计技术等方面研究和探讨了相关理论和相应的电路实现途径,同时基于中芯国际1.8V 0.18μm混合信号CMOS工艺,完成了12bit、100MSample/s (100MSPS)的S/H电路的设计仿真和版图绘制。文章主要内容和结果包括:
1)系统分析和对比了各种S/H电路结构,针对12bit采样精度和100MHz采样速度的指标要求,选取基于开关电容技术的电容翻转型闭环S/H电路结构,以保证S/H电路设计的可行性和可靠性;
2)分别建立了单管采样开关和栅压自举采样开关的等效电路模型,分析了开关的电荷注入、非线性导通电阻和采样时刻不确定性等非理想因素。针对简化S/H电路中,两种开关的非线性导通电阻引入的谐波分量进行了细致地分析和推导,并进行了Matlab仿真。在此基础上,设计了一种双边栅压自举CMOS采样开关;
3)对电容翻转型S/H电路的保持态建立行为进行了深入的数学建模,系统分析了影响S/H电路大信号建立行为和小信号建立行为的各种因素,推导了S/H的总建立时间与负载电容、反馈系数、运放极点、偏置电流、信号摆幅和建立精度之间的关系式。按总建立时间小于3ns的要求,计算出运算放大器的偏置电流。运算放大器采用增益增强型折叠共源共栅结构,按照最小建立时间(MST)的要求推算了所需的增益、单位增益带宽和相位裕度等指标;
4)基于SMIC 1.8V 0.18μm数模混合标准CMOS工艺,采用Hspice设计仿真了满足12bit、100MSPS要求的电容翻转型S/H电路,并采用Virtuso完成了S/H电路版图的绘制。
Nowadays, along the increasing market of telecommunication systems and consumer electronic appliances, the Analog-to-Digital converters (ADCs), which are of great importance in modern VLSI digital signal processing systems, have got great development in process, architecture and performance, and are developing towards higher sampling rate, higher resolution, and lower power consumption. As the key cell of ADCs, the linearity, power consumption, speed, and resolution of the sample and hold (S/H) circuit affect the performance of the whole ADC directly.
This thesis studies the academic models and corresponding circuit implementations for high speed, high resolution S/H circuits. They cover the S/H architectures, sampling switches with error sources, optimization on settling features of S/H, and layout-drawing technical. Finally, a 12bit 100MSample/s S/H circuit is designed based on SMIC 1.8V 0.18μm mixed-signal CMOS process. The details include:
1) The main architectures of S/H circuits are discussed, and it specifies that the switched-capacitor close-loop flip-over S/H topology can achieve 12bit 100MSample/s performance under sufficient feasibility and reliability.
2) .Equivalence circuit models are established for the single MOS switch and the bootstrapped switch, with studying on the nonideals of them, such as charge injection, nonlinear analog bandwidth and sampling moment uncertainty. For the simple S/H circuit, the harmonic, which is introduced by the nonlinear conducting resistance of two kinds of switches, is analyzed and deduced carefully. And a double-side bootstrapped CMOS switch is designed, in which buck-effect is reduced.
3) Mathematic model of the flip-over S/H circuit is established, which studied the factors affecting the large-signal settling behavior and the small-signal settling behavior of S/H. The relationship among settling time, feedback factor, poles of the OPA, bias current, signal swing, and setting accuracy is deduced. For a setting time of 3ns, the bias current of OPA is deduced regarding the former relationship. The gain-boosted folded-cascode architecture has been chosen for the OPA. The gain and the GBW, as well as the phase margin of the OPA are designed to achieve minimum setting time.
4) Based on SMIC 1.8V 0.18μm mixed-signal CMOS process, a 12bit 100MSample/s S/H circuit is designed with Hspice simulation environment and Virtuso layout tool.
本文分别从S/H架构、采样开关及其误差、S/H和运算放大器优化设计和S/H版图设计技术等方面研究和探讨了相关理论和相应的电路实现途径,同时基于中芯国际1.8V 0.18μm混合信号CMOS工艺,完成了12bit、100MSample/s (100MSPS)的S/H电路的设计仿真和版图绘制。文章主要内容和结果包括:
1)系统分析和对比了各种S/H电路结构,针对12bit采样精度和100MHz采样速度的指标要求,选取基于开关电容技术的电容翻转型闭环S/H电路结构,以保证S/H电路设计的可行性和可靠性;
2)分别建立了单管采样开关和栅压自举采样开关的等效电路模型,分析了开关的电荷注入、非线性导通电阻和采样时刻不确定性等非理想因素。针对简化S/H电路中,两种开关的非线性导通电阻引入的谐波分量进行了细致地分析和推导,并进行了Matlab仿真。在此基础上,设计了一种双边栅压自举CMOS采样开关;
3)对电容翻转型S/H电路的保持态建立行为进行了深入的数学建模,系统分析了影响S/H电路大信号建立行为和小信号建立行为的各种因素,推导了S/H的总建立时间与负载电容、反馈系数、运放极点、偏置电流、信号摆幅和建立精度之间的关系式。按总建立时间小于3ns的要求,计算出运算放大器的偏置电流。运算放大器采用增益增强型折叠共源共栅结构,按照最小建立时间(MST)的要求推算了所需的增益、单位增益带宽和相位裕度等指标;
4)基于SMIC 1.8V 0.18μm数模混合标准CMOS工艺,采用Hspice设计仿真了满足12bit、100MSPS要求的电容翻转型S/H电路,并采用Virtuso完成了S/H电路版图的绘制。
Nowadays, along the increasing market of telecommunication systems and consumer electronic appliances, the Analog-to-Digital converters (ADCs), which are of great importance in modern VLSI digital signal processing systems, have got great development in process, architecture and performance, and are developing towards higher sampling rate, higher resolution, and lower power consumption. As the key cell of ADCs, the linearity, power consumption, speed, and resolution of the sample and hold (S/H) circuit affect the performance of the whole ADC directly.
This thesis studies the academic models and corresponding circuit implementations for high speed, high resolution S/H circuits. They cover the S/H architectures, sampling switches with error sources, optimization on settling features of S/H, and layout-drawing technical. Finally, a 12bit 100MSample/s S/H circuit is designed based on SMIC 1.8V 0.18μm mixed-signal CMOS process. The details include:
1) The main architectures of S/H circuits are discussed, and it specifies that the switched-capacitor close-loop flip-over S/H topology can achieve 12bit 100MSample/s performance under sufficient feasibility and reliability.
2) .Equivalence circuit models are established for the single MOS switch and the bootstrapped switch, with studying on the nonideals of them, such as charge injection, nonlinear analog bandwidth and sampling moment uncertainty. For the simple S/H circuit, the harmonic, which is introduced by the nonlinear conducting resistance of two kinds of switches, is analyzed and deduced carefully. And a double-side bootstrapped CMOS switch is designed, in which buck-effect is reduced.
3) Mathematic model of the flip-over S/H circuit is established, which studied the factors affecting the large-signal settling behavior and the small-signal settling behavior of S/H. The relationship among settling time, feedback factor, poles of the OPA, bias current, signal swing, and setting accuracy is deduced. For a setting time of 3ns, the bias current of OPA is deduced regarding the former relationship. The gain-boosted folded-cascode architecture has been chosen for the OPA. The gain and the GBW, as well as the phase margin of the OPA are designed to achieve minimum setting time.
4) Based on SMIC 1.8V 0.18μm mixed-signal CMOS process, a 12bit 100MSample/s S/H circuit is designed with Hspice simulation environment and Virtuso layout tool.
引文
[1] Rudy van de Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edition. Dordrecht, the Netherlands: Kluwer Academic Publishers, 2003, 79-84
[2] Sanjit K.Mitra. Digital Signal Processing, 2nd edition. University of California, Santa Barbara: Tsinghua University Press, 2001, 98-107
[3] Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan. CMOS Data Converters for Communications. New York, USA: Kluwer Academic Publishers, 2002, 71-74
[4] Junhua Shen, Peter R. Kinget. A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS. IEEE, JSSCC, 2008, 43(4):787-795
[5] Sounak Roy, Swapna Banerjee. A 9 bit 400 MHz CMOS double-sampled Sample-and-Hold Amplifier. IEEE, 2008 International Conference on VLSI Design, Vol.2:323-327
[6] Tsung-Sum Lee, Chi-Chang Lu, Chih-Chieh Ho. A 330MHz 11Bit 26.4mW CMOS Low-Hold-Pedestal Fully Differential Track-and-Hold Circuit. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.1:711-714
[7] Jian Ruan, Chung Len Lee. A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. IEEE, 2008 4th IEEE International Symposium on Electronic Design, Test & Application, Vol.2:99-102
[8] Mousa Yousefi, Ziaaddin Daie KoozeKanani. A Flexible Sample and Hold Circuit for Data Converter Applications. IEEE, 2008 REGION 8 SIBIRCON, Vol.1:318-321
[9] Shan Jiang, Manh Anh Do. An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. IEEE, Transactions on Circuits and Systems, 2008, 55(6):1430-1440
[10] Quincy Fung, Armin A. Fomani. Design of a 2-GSample/s Track-and-Hold Amplifier implemented in a 60-GHz SiGe BiCMOS Process. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.2:937-940
[11] Mahmoud Sadollahy. A High-Speed Highly-Linear CMOS S/H Circuit. IEEE, 2008 Proceedings of the International Conference on Computer and Communication Engineering, Vol.1:550-553
[12] Chadi Jabbour, David Camarero. Optimizing the Number of Channels for Time-Interleaved Sample-and-Hold Circuits. IEEE, 2008 4th IEEE International Symposium on Electronic Design, Test & Application, Vol.2:245-248
[13] J. Rami rez-Angulo. Rail-to-rail fully differential sample and hold based on differential difference amplifier. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.1:701-703
[14] Christian Jesus B. FAYOMI, Gilson I. WIRTH. "The Flipped Voltage Follower"-based Low Voltage Fully Differential CMOS Sample-and-Hold Circuit. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.2:1716-1719
[15] Gianfranco Avitabile, Giuseppe Coviello. Complete time-domain behavioral model of Sample-and-Hold Amplifier using SIMULINK. IEEE, 2008 The 14th IEEE Mediterranean, Vol.2:102-107
[16] Behzad Razavi. Principles of Data Conversion System Design. New York: IEEE Press, 1995, 140-149
[17] Stuart K. Tewksbury, Frederick C. Meyer, David C. Rollenhagen. Terminology Related to the Performance of S/H, A/D, and D/A Circuit. IEEE, Transactions on Circuits and Systems, 1978, 25(7):419-426
[18] Rudy van de Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edition. Dordrecht, the Netherlands: Kluwer Academic Publishers, 2003, 79-84
[19] Walt Kester. Data Conversion Handbook. New York, USA: Elsevier, 2005, 127-140
[20] Abraham Peled, Bede Liu. Digital signal processing: theory, design, and implementation. New York, USA: Wiley, 1976, 202—207
[21] Alan V. Oppenheim, Alan S. Willsky, S. Hamid Nawab, Signals and Systems,第二版,北京:清华大学出版社,1998,514-555
[22] K, R. Stafford, P. R. Gray, R. A. Blanchard. A Complete Monolithic Sample/Hold Amplifier. IEEE Journal of Solid-State Circuits, 1974, SC-9: 381-387
[23] Davide Vecchi, Cristiano Azzolini, Andrea Boni. 100-MS/s 14-b Track-and-Hold Amplifier in 0.18-μm CMOS. Proceedings of ESSCIRC. Grenoble, France: IEEE, 2005, 259-262
[24] Y. Chouia, K. El-Sankary, A. Saleh. 14b, 50MS/s CMOS Front-End Sample and Hold Module Dedicated to a Pipelined ADC. the 47th IEEE Intemational Midwest Symposium on Circuits and Systems. Hiroshima, Japan: IEEE, 2004, 353-356
[25] P. Vorenkamp, J. P. M. Verdaasdonk. Fully Bipolar 120-Msample/s 10-b Track-and-Hold Circuit. IEEE Journal of Solid-State Circuits, 1992, 27:988-992
[26] Mohamed Zin, Kobayashi, Ichimure, et al. A High-Speed CMOS Track/Hold Circuit. IEEE Circuits and Systems, 1999, 3(9):1709-1712
[27] Yang W., Kelly D., Mehr I, et al. A 3-V 340mW 14-b 75Msample/s CMOS ADC with 85dB SFDR at Nyquist Input. IEEE J Solid-State Circuits, 2001, 36(12):1931-1936
[28] P. J. Lim, B. A. Wooley. A High-speed Sample-and-Hold Technique Using a Miller Hold Capacitance, IEEE Journal of Solid-State Circuits, 1991, SC-26: 643-651
[29] Wegmann. Charge Injection in Analog MOS Switches. IEEE Journal of Solid-State Circuits, 1987, 36(12):1091-1093
[30] Sheu B J, Hu C. Switch-Induced Error Voltage on a Switched Capacitor. IEEE Journal of Solid-State Circuits, 1984, 19(8):519–525
[31] Behzad Razavi. Design of Analog CMOS Integrated Circuits. Beijing: Tsinghua University Press, 2005, 343-348
[32] Erik Sall. Design of a Low Power, High Performance Track-and-hold Circuit in a 0.18μm CMOS Technology: [Master dissertation]. Sweden, Linkoping University, 2002
[33] T. B. Cho. Low-Power, Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures: [Ph.D. Dissertation], Berkeley, University of California, 1995
[34] T. B. Cho, P. R. Gray. A 10 b, 20Msample/s, 35 mW Pipeline A/D Converter. IEEE Journal of Solid-State Circuits, 1995, 30: 166-172
[35] A. M. Abo, P. R. Gray. A 1.5-V, 10-bit, 14-MS/s CMOS Pipeline Analogto-Digital Converter. IEEE JSSC, 1999, 34:599–606
[36] Andrew Masami Abo. Design for Reliability of Low-Voltage Switched-Capacitor Circuits: [Ph.D dissertation], Berkeley, University of California, 1999
[37] Fayomi C. B., Robert s G. W., Sawan M. Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit design and chip characterization. 2005 Proceedings of the International Conference on Computer and Communication Engineering, Vol.2:2200-2203
[38] Wang Lei, Yin Wen jing, Xu Jun. A Bootstrapped Sampling Circuit for High-Resolution and High-Speed A/D Converter. Microelectronics, 2007, 37(1):80-84
[39] Kamath B Y, Meyer R G, Gray P R. Relationship Between Frequency Response and Settling Time of Operational Amplifiers. IEEE Journal of Solid-State Circuits, 1974, 9(12):347-352
[40] Das M. Improved Design Criteria of Gain-Boosted CMOS OTA with High-Speed Optimizations. IEEE Trans on Circuits and Systems II, 2002, 49(3):294-297
[41] Flandre D. Improved Synthesis of Gain-Boosted Regulated-Cascode CMOS Stages Using Symbolic Analysis and gm/ID Methodology. IEEE Journal of Solid State Circuits, 1997, 32 (7):1006-1012
[42]刘源.新型Pipeline ADC系统建模与优化方法:[硕士学位论文].成都:电子科技大学,2007,55-56
[43] Chouia, Y., El-Sankary, K., Saleh, A. A new technique for designing high performance front-end sample and hold circuits. 2004 International Conference on Communication, Circuits and Systems, Vol.2:16-19
[44] Francesco Centurelli, Pietro Monsurro, Alessandro Trifiletti. A model for the distortion due to switch on-resistance in sample-and-hold circuits. ISCAS 2006, Vol.2:4787-4790
[45] Mikko Waltari. Circuit Techniques for Low-Voltage and High-Speed A/D Converters: [Dissertation for Doctor of Science in technology]. Finland, Helsinki: University of Technology, 2002
[46] Willy M. C. Sansen, Huang Qiuting, Kari A. I. Halonen. Transient Analysis of Charge Transfer in SC Filters-Gain Error and Distortion. IEEE Journal of Solid-State Circuits. 1987, 22(2): 341-346
[47] Alan V. Oppenheim, Alan S. Willsky. Signals & Systems, Second Edition.西安:西安交通大学出版社,1998,321-327
[48] Howard C. Yang, David J. Allstot. Considerations for fast settling operational amplifiers. IEEE Transactions on Circuits and Systems, 1990, 37(3): 326-334
[49] David Johns,Ken Martin. Analog Integrated Circuit Design. New York: Wiley, 1997, 266-271
[50] Klaas Bult, Govert J. G. M. Geelen. A fast-settling CMOS op amp for SC circuits with 90-dB DC gain. IEEE Journal of Solid-State Circuits, 1990, 12:1379—1384
[51] Ke Liu, Hai-gong Yang. Optimum Design of A Fully Differential 12bit 100MS/s Sample and Hold Module with over 77dB SFDR. 2007 ASICON 7th International Conference on Communication, Circuits and Systems, Vol.2:442-445
[52] Behzad Razavi.模拟集成电路设计.西安:西安交通大学出版社,2002,521-526
[53] Christopher Saint, Judy Saint. IC Mask Design-Essential Layout Techniques. NewYork: McGraw-Hill, 2001, 95-136
[54]朱正涌.半导体集成电路.北京:清华大学出版社,2001,42-44
[2] Sanjit K.Mitra. Digital Signal Processing, 2nd edition. University of California, Santa Barbara: Tsinghua University Press, 2001, 98-107
[3] Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan. CMOS Data Converters for Communications. New York, USA: Kluwer Academic Publishers, 2002, 71-74
[4] Junhua Shen, Peter R. Kinget. A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS. IEEE, JSSCC, 2008, 43(4):787-795
[5] Sounak Roy, Swapna Banerjee. A 9 bit 400 MHz CMOS double-sampled Sample-and-Hold Amplifier. IEEE, 2008 International Conference on VLSI Design, Vol.2:323-327
[6] Tsung-Sum Lee, Chi-Chang Lu, Chih-Chieh Ho. A 330MHz 11Bit 26.4mW CMOS Low-Hold-Pedestal Fully Differential Track-and-Hold Circuit. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.1:711-714
[7] Jian Ruan, Chung Len Lee. A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. IEEE, 2008 4th IEEE International Symposium on Electronic Design, Test & Application, Vol.2:99-102
[8] Mousa Yousefi, Ziaaddin Daie KoozeKanani. A Flexible Sample and Hold Circuit for Data Converter Applications. IEEE, 2008 REGION 8 SIBIRCON, Vol.1:318-321
[9] Shan Jiang, Manh Anh Do. An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. IEEE, Transactions on Circuits and Systems, 2008, 55(6):1430-1440
[10] Quincy Fung, Armin A. Fomani. Design of a 2-GSample/s Track-and-Hold Amplifier implemented in a 60-GHz SiGe BiCMOS Process. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.2:937-940
[11] Mahmoud Sadollahy. A High-Speed Highly-Linear CMOS S/H Circuit. IEEE, 2008 Proceedings of the International Conference on Computer and Communication Engineering, Vol.1:550-553
[12] Chadi Jabbour, David Camarero. Optimizing the Number of Channels for Time-Interleaved Sample-and-Hold Circuits. IEEE, 2008 4th IEEE International Symposium on Electronic Design, Test & Application, Vol.2:245-248
[13] J. Rami rez-Angulo. Rail-to-rail fully differential sample and hold based on differential difference amplifier. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.1:701-703
[14] Christian Jesus B. FAYOMI, Gilson I. WIRTH. "The Flipped Voltage Follower"-based Low Voltage Fully Differential CMOS Sample-and-Hold Circuit. IEEE, 2008 Custom Intergrated Circuits Conference, Vol.2:1716-1719
[15] Gianfranco Avitabile, Giuseppe Coviello. Complete time-domain behavioral model of Sample-and-Hold Amplifier using SIMULINK. IEEE, 2008 The 14th IEEE Mediterranean, Vol.2:102-107
[16] Behzad Razavi. Principles of Data Conversion System Design. New York: IEEE Press, 1995, 140-149
[17] Stuart K. Tewksbury, Frederick C. Meyer, David C. Rollenhagen. Terminology Related to the Performance of S/H, A/D, and D/A Circuit. IEEE, Transactions on Circuits and Systems, 1978, 25(7):419-426
[18] Rudy van de Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edition. Dordrecht, the Netherlands: Kluwer Academic Publishers, 2003, 79-84
[19] Walt Kester. Data Conversion Handbook. New York, USA: Elsevier, 2005, 127-140
[20] Abraham Peled, Bede Liu. Digital signal processing: theory, design, and implementation. New York, USA: Wiley, 1976, 202—207
[21] Alan V. Oppenheim, Alan S. Willsky, S. Hamid Nawab, Signals and Systems,第二版,北京:清华大学出版社,1998,514-555
[22] K, R. Stafford, P. R. Gray, R. A. Blanchard. A Complete Monolithic Sample/Hold Amplifier. IEEE Journal of Solid-State Circuits, 1974, SC-9: 381-387
[23] Davide Vecchi, Cristiano Azzolini, Andrea Boni. 100-MS/s 14-b Track-and-Hold Amplifier in 0.18-μm CMOS. Proceedings of ESSCIRC. Grenoble, France: IEEE, 2005, 259-262
[24] Y. Chouia, K. El-Sankary, A. Saleh. 14b, 50MS/s CMOS Front-End Sample and Hold Module Dedicated to a Pipelined ADC. the 47th IEEE Intemational Midwest Symposium on Circuits and Systems. Hiroshima, Japan: IEEE, 2004, 353-356
[25] P. Vorenkamp, J. P. M. Verdaasdonk. Fully Bipolar 120-Msample/s 10-b Track-and-Hold Circuit. IEEE Journal of Solid-State Circuits, 1992, 27:988-992
[26] Mohamed Zin, Kobayashi, Ichimure, et al. A High-Speed CMOS Track/Hold Circuit. IEEE Circuits and Systems, 1999, 3(9):1709-1712
[27] Yang W., Kelly D., Mehr I, et al. A 3-V 340mW 14-b 75Msample/s CMOS ADC with 85dB SFDR at Nyquist Input. IEEE J Solid-State Circuits, 2001, 36(12):1931-1936
[28] P. J. Lim, B. A. Wooley. A High-speed Sample-and-Hold Technique Using a Miller Hold Capacitance, IEEE Journal of Solid-State Circuits, 1991, SC-26: 643-651
[29] Wegmann. Charge Injection in Analog MOS Switches. IEEE Journal of Solid-State Circuits, 1987, 36(12):1091-1093
[30] Sheu B J, Hu C. Switch-Induced Error Voltage on a Switched Capacitor. IEEE Journal of Solid-State Circuits, 1984, 19(8):519–525
[31] Behzad Razavi. Design of Analog CMOS Integrated Circuits. Beijing: Tsinghua University Press, 2005, 343-348
[32] Erik Sall. Design of a Low Power, High Performance Track-and-hold Circuit in a 0.18μm CMOS Technology: [Master dissertation]. Sweden, Linkoping University, 2002
[33] T. B. Cho. Low-Power, Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures: [Ph.D. Dissertation], Berkeley, University of California, 1995
[34] T. B. Cho, P. R. Gray. A 10 b, 20Msample/s, 35 mW Pipeline A/D Converter. IEEE Journal of Solid-State Circuits, 1995, 30: 166-172
[35] A. M. Abo, P. R. Gray. A 1.5-V, 10-bit, 14-MS/s CMOS Pipeline Analogto-Digital Converter. IEEE JSSC, 1999, 34:599–606
[36] Andrew Masami Abo. Design for Reliability of Low-Voltage Switched-Capacitor Circuits: [Ph.D dissertation], Berkeley, University of California, 1999
[37] Fayomi C. B., Robert s G. W., Sawan M. Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit design and chip characterization. 2005 Proceedings of the International Conference on Computer and Communication Engineering, Vol.2:2200-2203
[38] Wang Lei, Yin Wen jing, Xu Jun. A Bootstrapped Sampling Circuit for High-Resolution and High-Speed A/D Converter. Microelectronics, 2007, 37(1):80-84
[39] Kamath B Y, Meyer R G, Gray P R. Relationship Between Frequency Response and Settling Time of Operational Amplifiers. IEEE Journal of Solid-State Circuits, 1974, 9(12):347-352
[40] Das M. Improved Design Criteria of Gain-Boosted CMOS OTA with High-Speed Optimizations. IEEE Trans on Circuits and Systems II, 2002, 49(3):294-297
[41] Flandre D. Improved Synthesis of Gain-Boosted Regulated-Cascode CMOS Stages Using Symbolic Analysis and gm/ID Methodology. IEEE Journal of Solid State Circuits, 1997, 32 (7):1006-1012
[42]刘源.新型Pipeline ADC系统建模与优化方法:[硕士学位论文].成都:电子科技大学,2007,55-56
[43] Chouia, Y., El-Sankary, K., Saleh, A. A new technique for designing high performance front-end sample and hold circuits. 2004 International Conference on Communication, Circuits and Systems, Vol.2:16-19
[44] Francesco Centurelli, Pietro Monsurro, Alessandro Trifiletti. A model for the distortion due to switch on-resistance in sample-and-hold circuits. ISCAS 2006, Vol.2:4787-4790
[45] Mikko Waltari. Circuit Techniques for Low-Voltage and High-Speed A/D Converters: [Dissertation for Doctor of Science in technology]. Finland, Helsinki: University of Technology, 2002
[46] Willy M. C. Sansen, Huang Qiuting, Kari A. I. Halonen. Transient Analysis of Charge Transfer in SC Filters-Gain Error and Distortion. IEEE Journal of Solid-State Circuits. 1987, 22(2): 341-346
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