应变硅MOS器件的应变特性
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摘要
近年来,应变硅(Strained Si)技术由于在提高MOS器件性能方面的卓越表现而备受关注。例如,通过在沟道中引入适当的压应力和张应力能分别提高PMOS的空穴迁移率和NMOS的电子迁移率。因此,通过工艺、材料、结构参数的优化设计,研究半导体MOS器件中应力、应变的控制有重要的科学意义和实用价值。
超深亚微米半导体结构中的局域微应力、应变的精确测量通常必须借助复杂的微结构分析、测量手段。本文探索了运用有限元分析工具ANSYS研究具有典型SiGe源漏结构的单轴应变硅MOS器件和应变Si/SiGe结构的双轴应变硅MOS器件的应力应变分布情况和影响因素。首先介绍应力应变的关系,发现它们均只与材料的杨氏模量和泊松比有关,确定了有限元软件ANSYS的可行性,再利用会聚束电子衍射(CBED)测量获得的应变值与ANSYS对单轴应变硅MOS器件沟道应变的计算结果进行了比较,发现能很好吻合,证明了有限元方法的可靠性。
建立单轴SiGe源漏MOS器件的二维模型后,根据SiGe结构的杨氏模量和虚拟热膨胀系数的不同,再对其均匀升温1000℃后,以模拟晶格结构的不匹配所带来的应力应变,所得图形中应变的分布很有层次,能很好的说明器件沟道内应变的分布。再逐步模拟了不同的Ge组分、源漏间距、源漏刻蚀深度和抬高高度对器件的影响,分布绘制出它们与应变值的曲线趋势图,发现高的Ge组分、小的源漏间距、深的刻蚀深度、高的抬高高度均可有效提高沟道内的应变值。
同样的,用有限元方法分析了双轴应变Si/SiGe结构MOS器件内应变的分布情况,建立双轴应变硅MOS器件的二维模型后,采用与单轴器件同样的原理,分析了锗组分、应变硅层厚度、弛豫SiGe层厚度和器件宽度对器件的影响,也绘制出它们与应变值的曲线趋势图,发现高的Ge组分、小的应变Si层厚度、大的弛豫SiGe层厚度、小的器件宽度均可有效提高应变Si层中的应变值。
Recently, Strained Si technology has attracted wide attention because of improving significantly the MOS devices performances. For example, the hole mobility in PMOS and the electron mobility in NMOS can be significantly enhanced by introducing appropriate compressive and tensile channel stresses, respectively. Thus, through the optimization design of the process、material and structural parameters, investigating the influence of stress and strain in semiconductor nano-devices has important scientific significance and practical value.
The accurate measurements of local micro-stress and strain in ultra deep sub-micron semiconductor structures usually resort to complicated microstructure analysis, measurement methods. Therefore, this paper explored to use the finite element analysis tool ANSYS to research stress and strain distributions and influencing factors for a uniaxial strained Si MOS device with typical SiGe source-drain structure and a biaxial strained Si MOS device with strained Si/SiGe heterostructure, respectively. Firstly there introduced the relationship between stress and strain, and found them only related to the material Young's modulus and Poisson's ratio, verified the feasibility by using ANSYS. By compared the simulation results in the uniaxial strained Si MOS device obtained by ANSYS and the experimental data measured by the convergent beam electron diffraction (CBED), there found them fit very well, also verified the reliability by using ANSYS.
According to the differences of Young's modulus and the virtual thermal expansion coefficient of SiGe structure, this paper established a two-dimensional model of uniaxial SiGe source-drain MOS devices, and then increased a uniform temperature 1000℃, to simulate stress and strain caused by the lattice mismatch. The strain in the simulation results charts hierarchically distributed, can well explained the distribution of strain in the device channels. And then this paper respectively simulated Ge composition, source and drain spacing, source and drain etch depth and the elevated height on the impact of the device, mapping out their strain curve trends, found that higher Ge composition, smaller source and drain spacing, deeper etch depth and higher elevation height can effectively raised the channel strain.
Similarly, using finite element method, this paper analyzed the distributions of strain in a biaxial strained MOS device with the Si/SiGe structure, established a two-dimensional model, used the same principle of the uniaxial device, analyzed Ge composition, thickness of strained Si layer, thickness of relaxed SiGe layer and device width on the impact of the device, mapping out their strain curve trends, found that higher Ge composition, smaller thickness of strained Si layer, larger thickness of relaxed SiGe layer, smaller device width can effectively improved the strain in strained Si layer.
超深亚微米半导体结构中的局域微应力、应变的精确测量通常必须借助复杂的微结构分析、测量手段。本文探索了运用有限元分析工具ANSYS研究具有典型SiGe源漏结构的单轴应变硅MOS器件和应变Si/SiGe结构的双轴应变硅MOS器件的应力应变分布情况和影响因素。首先介绍应力应变的关系,发现它们均只与材料的杨氏模量和泊松比有关,确定了有限元软件ANSYS的可行性,再利用会聚束电子衍射(CBED)测量获得的应变值与ANSYS对单轴应变硅MOS器件沟道应变的计算结果进行了比较,发现能很好吻合,证明了有限元方法的可靠性。
建立单轴SiGe源漏MOS器件的二维模型后,根据SiGe结构的杨氏模量和虚拟热膨胀系数的不同,再对其均匀升温1000℃后,以模拟晶格结构的不匹配所带来的应力应变,所得图形中应变的分布很有层次,能很好的说明器件沟道内应变的分布。再逐步模拟了不同的Ge组分、源漏间距、源漏刻蚀深度和抬高高度对器件的影响,分布绘制出它们与应变值的曲线趋势图,发现高的Ge组分、小的源漏间距、深的刻蚀深度、高的抬高高度均可有效提高沟道内的应变值。
同样的,用有限元方法分析了双轴应变Si/SiGe结构MOS器件内应变的分布情况,建立双轴应变硅MOS器件的二维模型后,采用与单轴器件同样的原理,分析了锗组分、应变硅层厚度、弛豫SiGe层厚度和器件宽度对器件的影响,也绘制出它们与应变值的曲线趋势图,发现高的Ge组分、小的应变Si层厚度、大的弛豫SiGe层厚度、小的器件宽度均可有效提高应变Si层中的应变值。
Recently, Strained Si technology has attracted wide attention because of improving significantly the MOS devices performances. For example, the hole mobility in PMOS and the electron mobility in NMOS can be significantly enhanced by introducing appropriate compressive and tensile channel stresses, respectively. Thus, through the optimization design of the process、material and structural parameters, investigating the influence of stress and strain in semiconductor nano-devices has important scientific significance and practical value.
The accurate measurements of local micro-stress and strain in ultra deep sub-micron semiconductor structures usually resort to complicated microstructure analysis, measurement methods. Therefore, this paper explored to use the finite element analysis tool ANSYS to research stress and strain distributions and influencing factors for a uniaxial strained Si MOS device with typical SiGe source-drain structure and a biaxial strained Si MOS device with strained Si/SiGe heterostructure, respectively. Firstly there introduced the relationship between stress and strain, and found them only related to the material Young's modulus and Poisson's ratio, verified the feasibility by using ANSYS. By compared the simulation results in the uniaxial strained Si MOS device obtained by ANSYS and the experimental data measured by the convergent beam electron diffraction (CBED), there found them fit very well, also verified the reliability by using ANSYS.
According to the differences of Young's modulus and the virtual thermal expansion coefficient of SiGe structure, this paper established a two-dimensional model of uniaxial SiGe source-drain MOS devices, and then increased a uniform temperature 1000℃, to simulate stress and strain caused by the lattice mismatch. The strain in the simulation results charts hierarchically distributed, can well explained the distribution of strain in the device channels. And then this paper respectively simulated Ge composition, source and drain spacing, source and drain etch depth and the elevated height on the impact of the device, mapping out their strain curve trends, found that higher Ge composition, smaller source and drain spacing, deeper etch depth and higher elevation height can effectively raised the channel strain.
Similarly, using finite element method, this paper analyzed the distributions of strain in a biaxial strained MOS device with the Si/SiGe structure, established a two-dimensional model, used the same principle of the uniaxial device, analyzed Ge composition, thickness of strained Si layer, thickness of relaxed SiGe layer and device width on the impact of the device, mapping out their strain curve trends, found that higher Ge composition, smaller thickness of strained Si layer, larger thickness of relaxed SiGe layer, smaller device width can effectively improved the strain in strained Si layer.
引文
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[3] G Abstreiter, I S Gergis, T Wolf, et al. Strain-Induced Two-Dimensional Electron Gas in Selectively Doped Si/ Si x Ge1 ? x Superlattices. Physics Review Letter.1985, 54(22). 2441-2444.
[4] E A Fitzgerald, Y H Xie, D Monroe, et al. Relaxed Si1 ? x Gex structures for III-V integration with Si and high mobility two-dimensional electron gases in Si. Journal of Vacuum Science&Technology B: Microelectronics Processing and Phenomena, 1992, 10(4). 1807
[5] J Welser, J L Hoyt, J F Gibbons, et al. NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures. International Electron Devices Meeting Technical Digest. 1992, Dec. 1000-1002.
[6] D K Nayak, J C S Woo, J S Park, et al. High-mobilityΡ-channel metal-semiconductor field-effect transistor on strained Si. Applied Physics Letters, 1993, 62(22). 2853-2855.
[7] M T Currie, S B Samavedam, T A Langdo, et al. controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing. Applied Physics Letter. 1998, 72(14). 1718-1720.
[8] T Mizuno, S Takagi, N Sugiyama, et al. Electron and hole mobility enhancement in strained-Si MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology[J]. IEEE Electron Device Letters. 2000, 21(5). 230-232.
[9] G Hock, E Kohn, C Rosenblad, et al. High hole mobility in Si0.17Ge0.83 channel metal-oxide-semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition. Applied Physics Letters, 2000, 76(26). 3920-3922
[10] L J Huang, J O Chu, D F Cananei, et al. SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors. Applied Physics Letter. 2001, 78(9). 1267-1269.
[11] J L Hoyt, H M Nayfeh, S Eguchi. Strained Silicon MOSFET technology. International Electron Devices Meeting Technical Digest. 2002, Dec. 23-26.
[12] K Rim, J Chu, H Chen, et al. Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs. Symposium on VLSI Technology Digest of Technical Papers. 2002. 98-99.
[13] Q Xiang, J S Goo, J Pan, et al. Strained silicon NMOS with nickel-silicide metal gate. Symposium on VLSI Technology Digest of Technical Papers. 2003. 101-102.
[14] H S Yang, R Malik, S Narasimha, et al. Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing. International Electron Devices Meeting Technical Digest. 2004, Dec. 1075-1078.
[15] P Ranade, T Ghani, K Kuhn, et al. High performance 35nm gate length CMOS transistors featuring NiSi metal gate, uniaxial strained silicon channels and 1.2nm gate oxide[C]. IEDM Tech.Dig. Washington D C, USA. 2005. 227-230.
[16] K M Tan, M Zhu, W W Fang, et al. A New Liner Stressor with Very High Intrinsic Stress (>6 GPa) and Low Permittivity Comprising Diamond-Like Carbon (DLC) for Strained P-Channel Transistors[C]. IEDM Tech.Dig. Washington D C, USA. 2007, 127-130.
[17] Yeh Wen-Kuan, Wang Jean-An, Lin Chien-Ting, et al. The Impact of Stain Technology on FUSI Gate SOI CMOSFET and Device Performance Enhancement for 45nm node and beyond. IEEE Trans on Devics and Materials Reliability. 2009, March, 9. 74-79
[18] Zubia D, Hersee S D, Khraishi T. Strain partitioning in coherent compliant heterostructures [J]. Appl.Phys.Lett. 2002, 80(5). 740-742.
[19] H Yin, K D Hobart, F J Kub. Strain partition of Si/SiGe and SiO2/SiGe on compliant substrates [J]. Appl.Phys.Lett. 2003, 82(22). 3853-3855.
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[23] Yeo Y C, Sun J. Finite-element study of strain distribution in transistor with silicon-germanium source and drain Regions. Appl.Phys.Lett. 2005, 83(023103). 1-3
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[26]刘恩科,朱秉升,罗晋生等。半导体物理学,第四版。北京:国防工业出版社,1994.
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[29] D Nayak. High-mobility p-channel metal-oxide-semiconductor field effect transistor on strained Si. Applied Physics Letters. 1993, 62. 2853
[30]J L Liu. A surfactant-mediated relaxed Si 0.5 Ge0 .5 graded layer with a very low threading dislocation density and smooth surface. Applied Physics Letters. 1999, 75(11). 1586-1588
[31]K K Linden. Reduction of dislocation density in mismatched SiGe/Si using a low-temperature Si buffer layer. Applied Physics Letters. 1997, 70(24). 3224
[32]T Tezuka. Novel fully-depleted Site-on-insulator pMOSFETs with high-mobility Site surface channels. In: IEDM Technical Digest. 2001. 946-948
[33]S E Thompson. A Logic Nanotechnology Featuring Strained-Silicon. IEEE Electron Device Letters. 2004, 25(4). 191-193
[34]Z Y Cheng. Site-on-insulator(SGOI): Substrate preparation and MOSFET fabrication for electron mobility evaluation. IEEE International SOI Conference. 2001. 13-14
[35]N Sugiyama. A novel fabrication technique of ultra-thin and relaxed Site buffer layers with high Ge fraction for sub-100 nm strained silicon-on-insulator MOSFETs. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Solid State Devices and Materials. 2001, 40 (4). 2866-2874
[36]华杰,徐秋霞。应变硅技术。第十四届全国半导体集成电路、硅材料学术会议。2005,11, 52-56。
[37]T Ghani, M Armstrong, C Auth, et al. A 90 nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors[C].Tech Dig IEEE Int Elec Dev Meet. Washington, USA. 2003. 11. 6. 1-11. 6. 3.
[38]K W Ang, K J Chui, V Bliznetsov, et al. Thin body silicon-on-insulator N-MOSFET with silicon-carbon source/drain regions for performance enhancement[C]. Tech Dig IEEE Int Elec Dev Meet. Washington, USA. 2005. 497-500.
[39]H S Yang, R Maik, S Naraimha, et al. Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing[C]. Tech Dig IEEE Int Elec Dev Meet. San Francisco, USA. 2004. 1075-1077.
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[2] R People, J C Bean, D V Lang, et al. Modulation doping in Si1 ? x Gex/Si strained layer heterostructures. Applied Physics Letter. 1984, 45(11). 1231-1233.
[3] G Abstreiter, I S Gergis, T Wolf, et al. Strain-Induced Two-Dimensional Electron Gas in Selectively Doped Si/ Si x Ge1 ? x Superlattices. Physics Review Letter.1985, 54(22). 2441-2444.
[4] E A Fitzgerald, Y H Xie, D Monroe, et al. Relaxed Si1 ? x Gex structures for III-V integration with Si and high mobility two-dimensional electron gases in Si. Journal of Vacuum Science&Technology B: Microelectronics Processing and Phenomena, 1992, 10(4). 1807
[5] J Welser, J L Hoyt, J F Gibbons, et al. NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures. International Electron Devices Meeting Technical Digest. 1992, Dec. 1000-1002.
[6] D K Nayak, J C S Woo, J S Park, et al. High-mobilityΡ-channel metal-semiconductor field-effect transistor on strained Si. Applied Physics Letters, 1993, 62(22). 2853-2855.
[7] M T Currie, S B Samavedam, T A Langdo, et al. controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing. Applied Physics Letter. 1998, 72(14). 1718-1720.
[8] T Mizuno, S Takagi, N Sugiyama, et al. Electron and hole mobility enhancement in strained-Si MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology[J]. IEEE Electron Device Letters. 2000, 21(5). 230-232.
[9] G Hock, E Kohn, C Rosenblad, et al. High hole mobility in Si0.17Ge0.83 channel metal-oxide-semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition. Applied Physics Letters, 2000, 76(26). 3920-3922
[10] L J Huang, J O Chu, D F Cananei, et al. SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors. Applied Physics Letter. 2001, 78(9). 1267-1269.
[11] J L Hoyt, H M Nayfeh, S Eguchi. Strained Silicon MOSFET technology. International Electron Devices Meeting Technical Digest. 2002, Dec. 23-26.
[12] K Rim, J Chu, H Chen, et al. Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs. Symposium on VLSI Technology Digest of Technical Papers. 2002. 98-99.
[13] Q Xiang, J S Goo, J Pan, et al. Strained silicon NMOS with nickel-silicide metal gate. Symposium on VLSI Technology Digest of Technical Papers. 2003. 101-102.
[14] H S Yang, R Malik, S Narasimha, et al. Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing. International Electron Devices Meeting Technical Digest. 2004, Dec. 1075-1078.
[15] P Ranade, T Ghani, K Kuhn, et al. High performance 35nm gate length CMOS transistors featuring NiSi metal gate, uniaxial strained silicon channels and 1.2nm gate oxide[C]. IEDM Tech.Dig. Washington D C, USA. 2005. 227-230.
[16] K M Tan, M Zhu, W W Fang, et al. A New Liner Stressor with Very High Intrinsic Stress (>6 GPa) and Low Permittivity Comprising Diamond-Like Carbon (DLC) for Strained P-Channel Transistors[C]. IEDM Tech.Dig. Washington D C, USA. 2007, 127-130.
[17] Yeh Wen-Kuan, Wang Jean-An, Lin Chien-Ting, et al. The Impact of Stain Technology on FUSI Gate SOI CMOSFET and Device Performance Enhancement for 45nm node and beyond. IEEE Trans on Devics and Materials Reliability. 2009, March, 9. 74-79
[18] Zubia D, Hersee S D, Khraishi T. Strain partitioning in coherent compliant heterostructures [J]. Appl.Phys.Lett. 2002, 80(5). 740-742.
[19] H Yin, K D Hobart, F J Kub. Strain partition of Si/SiGe and SiO2/SiGe on compliant substrates [J]. Appl.Phys.Lett. 2003, 82(22). 3853-3855.
[20] S Christiansen, M Albrecht, H P Strunk. Strained state of Ge (Si) islands on Si finite element calculations and comparison to convergent beam electron-diffraction measurements [J]. Appl.Phys.Lett. 1994, 64(26). 3167-3619.
[21] T Benabbas, P Francois, Y Androussi. Stress relaxation in highly strained InAs/GaAs structures as studied by finite element analysis and transmission electron microscopy [J]. J.Appl.Phys. 1996, 80(5). 2763-2767.
[22] Liu G R, Jerry S S Q. A finite element study of the stress and strain fields of InAs quantum dots embedded in GaAs [J]. Semicond.Sci.Technol. 2002, 17(6). 630-643.
[23] Yeo Y C, Sun J. Finite-element study of strain distribution in transistor with silicon-germanium source and drain Regions. Appl.Phys.Lett. 2005, 83(023103). 1-3
[24] J P Dismukes, L Ekstrom, R J Paff. Thermal and electrical properties of heavily doped Ge-Si alloys up to 1300°K. Journal of Applied Physics. 1964, 35(10). 2899-2907.
[25] Douglas J Paul. Si/SiGe heterostructures: from material and physics to devices and circuits. Semiconductor Science and Technology. 2004, Sept, 19. 75-108.
[26]刘恩科,朱秉升,罗晋生等。半导体物理学,第四版。北京:国防工业出版社,1994.
[27] M V Fischetti, S E Laux. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys [J]. Appl. Phys. 1996, 80(4). 2234-2252.
[28] S E Thompson, G Sun, K Wu, et al. Key differences for process-induced uniaxial vs substrate-induced biaxial stressed Si and Ge channel MOSFETs. IEDM Tech. Dig. 2004. 221–224.
[29] D Nayak. High-mobility p-channel metal-oxide-semiconductor field effect transistor on strained Si. Applied Physics Letters. 1993, 62. 2853
[30]J L Liu. A surfactant-mediated relaxed Si 0.5 Ge0 .5 graded layer with a very low threading dislocation density and smooth surface. Applied Physics Letters. 1999, 75(11). 1586-1588
[31]K K Linden. Reduction of dislocation density in mismatched SiGe/Si using a low-temperature Si buffer layer. Applied Physics Letters. 1997, 70(24). 3224
[32]T Tezuka. Novel fully-depleted Site-on-insulator pMOSFETs with high-mobility Site surface channels. In: IEDM Technical Digest. 2001. 946-948
[33]S E Thompson. A Logic Nanotechnology Featuring Strained-Silicon. IEEE Electron Device Letters. 2004, 25(4). 191-193
[34]Z Y Cheng. Site-on-insulator(SGOI): Substrate preparation and MOSFET fabrication for electron mobility evaluation. IEEE International SOI Conference. 2001. 13-14
[35]N Sugiyama. A novel fabrication technique of ultra-thin and relaxed Site buffer layers with high Ge fraction for sub-100 nm strained silicon-on-insulator MOSFETs. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Solid State Devices and Materials. 2001, 40 (4). 2866-2874
[36]华杰,徐秋霞。应变硅技术。第十四届全国半导体集成电路、硅材料学术会议。2005,11, 52-56。
[37]T Ghani, M Armstrong, C Auth, et al. A 90 nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors[C].Tech Dig IEEE Int Elec Dev Meet. Washington, USA. 2003. 11. 6. 1-11. 6. 3.
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