基于GPP的LTE PUSCH接收实现与优化
摘要
物理层上行共享信道(Physical Uplink Shared Channel, PUSCH)是LTE物理层最重要的信道之一,承载着上行业务数据UL-SCH、上行控制信息(Uplink Control Information, UCI)和解调参考信号。该链路处理流程复杂且各子模块的数据处理各有特点,因此高性能的PUSCH接收链路的设计和实现是LTE系统的关键。随着通用处理器架构数据处理能力的不断增强,以Intel为代表的通用处理器架构以便于移植、可虚拟化、天然的多任务支持等优势在无线通信领域潜力越来越大。因此,在通用处理器架构上进行LTE系统PUSCH接收链路的设计和实现在工程实践和理论积累上均有重大意义。
本文主要专注于PUSCH接收链路基于Intel通用处理器架构的算法设计、实现和优化,在充分把握PUSCH各功能模块数据处理特点的基础上,结合通用处理器架构的执行特点进行算法的设计和执行结构的优化。
本文首先简要分析了LTE系统上行链路的关键技术并概述了Intel通用处理器架构的特点和用于实时信号处理软件开发过程。总结了高吞吐率实时信号处理的算法设计原则,并根据该原则完成PUSCH接收链路关键模块的算法设计。同时,本文提出了Intel通用处理器架构上实现实时信号处理必须解决的程序效率问题,详述了通过SIMD技术、多线程技术、流水线技术、指令并行等充分利用CPU计算能力的优化方法。最后,作者对PUSCH各模块采用程序结构优化、数据结构优化、结合Intel编译器的优化等典型方法进行了高度优化并测试了优化结果,验证了本文提出的基于Intel通用处理器架构的PUSCH接收链路方案设计的正确性和有效性。上述研究成果显著提高了实时信号处理的效率,可降低基站成本,为后续全面实现基于通用处理器架构的多通信制式基站积累了方法和经验,在实际的LTE系统应用中将有很好的实践价值。
PUSCH (Physical Uplink Shared Channel) is one of the most important physical channels of LTE system. It is designed for the transmission of server data UL-SCH, UCI (Uplink Control Information) and demodulation reference signals. The process of PUSCH is complex and each sub-module has its own characteristics, so the design and implementation of high-performance PUSCH receiver is the key of LTE system. The great development of general-purpose processor technology makes the GPP possess the efficiently massive data processing abilities. And GPP has growing potential in wireless communications field for the facilitate transplantation, virtualization and natural multi-tasks support. Therefore, the design and implementation of high-performance PUSCH receiver based on GPP has great significance both in practice and theory.
This paper focuses on the algorithm design, implementation and optimization of PUSCH receiver based on the Intel GPP architecture. Combined the general-purpose processor architecture features with the characteristics of PUSCH sub-module, we make great efforts on the algorithm design and optimization.
This paper begins with a brief analysis of the the LTE uplink key technology and the characteristics of the Intel architecture, provides an overview of software development for real-time signal processing. Then we summarize the rule of high performance algorithms design based on which the key algorithms of PUSCH receiver are developed. In order to improve the efficiency of program execution we propose the methods of making full use of CPU computing resource by taking advantage of SIMD technolgy, multi-threading technology, instruction parallelism and pipeline technology. And each sub-module of PUSCH receiver is fully optimized by code structure optimization, data structure optimization and other typical optimization associated with the Intel compile. Finally, the solution of LTE PUSCH receiver based on Intel GPP architecture verified both in reliability and effectiveness which proves that our implementation can meet the requirement of LTE system.
The above research results significantly improve the efficiency of real-time signal processing based on GPP architecture. It has great significance in the realization of multimode base-station in the future. What's more, it is valuable for the commercial use of the LTE system.
本文主要专注于PUSCH接收链路基于Intel通用处理器架构的算法设计、实现和优化,在充分把握PUSCH各功能模块数据处理特点的基础上,结合通用处理器架构的执行特点进行算法的设计和执行结构的优化。
本文首先简要分析了LTE系统上行链路的关键技术并概述了Intel通用处理器架构的特点和用于实时信号处理软件开发过程。总结了高吞吐率实时信号处理的算法设计原则,并根据该原则完成PUSCH接收链路关键模块的算法设计。同时,本文提出了Intel通用处理器架构上实现实时信号处理必须解决的程序效率问题,详述了通过SIMD技术、多线程技术、流水线技术、指令并行等充分利用CPU计算能力的优化方法。最后,作者对PUSCH各模块采用程序结构优化、数据结构优化、结合Intel编译器的优化等典型方法进行了高度优化并测试了优化结果,验证了本文提出的基于Intel通用处理器架构的PUSCH接收链路方案设计的正确性和有效性。上述研究成果显著提高了实时信号处理的效率,可降低基站成本,为后续全面实现基于通用处理器架构的多通信制式基站积累了方法和经验,在实际的LTE系统应用中将有很好的实践价值。
PUSCH (Physical Uplink Shared Channel) is one of the most important physical channels of LTE system. It is designed for the transmission of server data UL-SCH, UCI (Uplink Control Information) and demodulation reference signals. The process of PUSCH is complex and each sub-module has its own characteristics, so the design and implementation of high-performance PUSCH receiver is the key of LTE system. The great development of general-purpose processor technology makes the GPP possess the efficiently massive data processing abilities. And GPP has growing potential in wireless communications field for the facilitate transplantation, virtualization and natural multi-tasks support. Therefore, the design and implementation of high-performance PUSCH receiver based on GPP has great significance both in practice and theory.
This paper focuses on the algorithm design, implementation and optimization of PUSCH receiver based on the Intel GPP architecture. Combined the general-purpose processor architecture features with the characteristics of PUSCH sub-module, we make great efforts on the algorithm design and optimization.
This paper begins with a brief analysis of the the LTE uplink key technology and the characteristics of the Intel architecture, provides an overview of software development for real-time signal processing. Then we summarize the rule of high performance algorithms design based on which the key algorithms of PUSCH receiver are developed. In order to improve the efficiency of program execution we propose the methods of making full use of CPU computing resource by taking advantage of SIMD technolgy, multi-threading technology, instruction parallelism and pipeline technology. And each sub-module of PUSCH receiver is fully optimized by code structure optimization, data structure optimization and other typical optimization associated with the Intel compile. Finally, the solution of LTE PUSCH receiver based on Intel GPP architecture verified both in reliability and effectiveness which proves that our implementation can meet the requirement of LTE system.
The above research results significantly improve the efficiency of real-time signal processing based on GPP architecture. It has great significance in the realization of multimode base-station in the future. What's more, it is valuable for the commercial use of the LTE system.
引文
[1]沈嘉,索世强等3GPP长期演进(LTE)技术原理与系统设计人民邮电出版社2008年11月
[2]Erik Dahlman, Stefan Parkvall 3GPP EVOLUTION:HSPA AND LTE FOR MOBILE BROADBAND Academic Press 2007
[3]Stefania Sesia, Issam Toufik LTE-The UMTS Long Term Evolution:From Theory to Practice John Wiley & Sons Ltd.2009
[4]赵训威,林辉,张明等3GPP长期演进(LTE)系统架构与技术规范人民邮电出版社
[5]3GPP TS 36.211 V9.1.0 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical Channels and Modulation (Release 9), March,2010
[6]3GPP TS 36.212 V9.3.0 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 9), September,2010
[7]3GPP TS 36.212 V9.3.0 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical layer procedures(Release 9), September,2010
[8]Intel(?) 64 and IA-32 Architecture Software Developer's Manual Volume 2 Intel(、) 64 and IA-32 Architectures Optimization Reference Manual
[9]A. Peleg and U. Weiser, "MMX Technology Extension to Intel Architecture" IEEE Micro, 16(4):42-50,Aug.1996
[10]Peter H.-Y Wu and Stephen M. Pisuk, "Implementation of a Low Complexity, Low Power, Integer-Based Turbo Decoder", IEEE 2001
[11]A.Wiesler, O.Muller, F.Jondral, "MAP-algorithm with fixed point representation for software radios", Proceedings of IEEE VTC'00 Fall, Sept.2000
[12]Y Sun, Y Zhu, M. Goel, and J. R. Cavallaro, "Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards", in IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), July 2008, pp.209-214
[13]G Falcao, V. Silva and L. Sousa "How GPUs Can Outperform ASICs for Fast LDPC Decoding" in ICS09:Proceedings of the 23rd International Conference on Supercomputing pp.390-399
[14]K. Loo, T. Alukaidey and S. Jimaa "High performance parallelised 3GPP turbo decoder" in IEEE Personal Mobile Communications Conference April 2003 pp.337-342
[15]Michael Wu, Yang Sun and Joseph R. Cavallaro "Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU" IEEE 2010
[16]J. Vogt and A. Finger "Improving the max-log-MAP turbo decoder" IEEE lectronics Letters Vol 36 No.23 Nov.2000 pp.1937-1939
[17]M. Shin and I.Park "SIMD processor-based turbo decoder supportingmultiple third-generation wireless standards" IEEE Trans, on VLSI vol.15 pp.801-810 Jun.2007
[18]C.Berrou, A.Glavieux and P.Thitimajshima, "Near Shannon limit error-correcting coding and decoding:Turbo-Codes", IEEE International Conference on Communication, May 1993
[19]Intel Corporation, IA-32 Intel(R)architecture software developer's manual, volume 1: Basic Architecture,2004
[20]Intel Corporation Intel C++ Comliler User and Reference Guides Document number304968-023US 2009
[21]Intel Corporation Intel VTune Amplifier XE 2011 Release Notes for Linux Document number:323591-001 US
[22]Fritz Gerneth, FIR Filter Algorithm Implementation Using Intel(?) SSE Instructions Intel Corporation, March 2010
[2]Erik Dahlman, Stefan Parkvall 3GPP EVOLUTION:HSPA AND LTE FOR MOBILE BROADBAND Academic Press 2007
[3]Stefania Sesia, Issam Toufik LTE-The UMTS Long Term Evolution:From Theory to Practice John Wiley & Sons Ltd.2009
[4]赵训威,林辉,张明等3GPP长期演进(LTE)系统架构与技术规范人民邮电出版社
[5]3GPP TS 36.211 V9.1.0 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical Channels and Modulation (Release 9), March,2010
[6]3GPP TS 36.212 V9.3.0 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 9), September,2010
[7]3GPP TS 36.212 V9.3.0 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical layer procedures(Release 9), September,2010
[8]Intel(?) 64 and IA-32 Architecture Software Developer's Manual Volume 2 Intel(、) 64 and IA-32 Architectures Optimization Reference Manual
[9]A. Peleg and U. Weiser, "MMX Technology Extension to Intel Architecture" IEEE Micro, 16(4):42-50,Aug.1996
[10]Peter H.-Y Wu and Stephen M. Pisuk, "Implementation of a Low Complexity, Low Power, Integer-Based Turbo Decoder", IEEE 2001
[11]A.Wiesler, O.Muller, F.Jondral, "MAP-algorithm with fixed point representation for software radios", Proceedings of IEEE VTC'00 Fall, Sept.2000
[12]Y Sun, Y Zhu, M. Goel, and J. R. Cavallaro, "Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards", in IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), July 2008, pp.209-214
[13]G Falcao, V. Silva and L. Sousa "How GPUs Can Outperform ASICs for Fast LDPC Decoding" in ICS09:Proceedings of the 23rd International Conference on Supercomputing pp.390-399
[14]K. Loo, T. Alukaidey and S. Jimaa "High performance parallelised 3GPP turbo decoder" in IEEE Personal Mobile Communications Conference April 2003 pp.337-342
[15]Michael Wu, Yang Sun and Joseph R. Cavallaro "Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU" IEEE 2010
[16]J. Vogt and A. Finger "Improving the max-log-MAP turbo decoder" IEEE lectronics Letters Vol 36 No.23 Nov.2000 pp.1937-1939
[17]M. Shin and I.Park "SIMD processor-based turbo decoder supportingmultiple third-generation wireless standards" IEEE Trans, on VLSI vol.15 pp.801-810 Jun.2007
[18]C.Berrou, A.Glavieux and P.Thitimajshima, "Near Shannon limit error-correcting coding and decoding:Turbo-Codes", IEEE International Conference on Communication, May 1993
[19]Intel Corporation, IA-32 Intel(R)architecture software developer's manual, volume 1: Basic Architecture,2004
[20]Intel Corporation Intel C++ Comliler User and Reference Guides Document number304968-023US 2009
[21]Intel Corporation Intel VTune Amplifier XE 2011 Release Notes for Linux Document number:323591-001 US
[22]Fritz Gerneth, FIR Filter Algorithm Implementation Using Intel(?) SSE Instructions Intel Corporation, March 2010