JPEG编码器的设计与优化
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摘要
近年来,随着微电子技术,网络通信技术和多媒体技术的高速发展,消费类电子、通信、影视及广播、计算机技术日益紧密地结合起来。数字图像压缩编码技术也逐渐成熟,对于计算机的声音和视频处理能力也提出了更高的要求,实时图像处理在众多领域得到了越来越广泛的应用。图像压缩/解压缩芯片已经成为多媒体技术的重要研究内容,这些芯片的研究成为了信息产业的新热点。
本文主要介绍了JPEG基本模式的编码规范,高速JPEG编码器的整体设计思想、结构和具体实现,并在此基础上针对速度,面积和功耗上进行了一些优化研究。
论文的主要工作如下:
1.对JPEG编码标准进行了分析,采用SystemC语言对JPEG编码器进行系统级建模,并利用完成的事务级模型建立了SystemC/HDL混合语言仿真平台。
2.参考系统级模型的模块划分,采用Top-Down的模块化设计方法,完成了JPEG高速编码器的RTL设计,实现了编码全过程的流水线结构。
3.在色彩空间转换模块的设计中,通过引入共享的固定常数乘法器,并加入优化的控制逻辑,减小电路功耗30%以上。
4.在量化模块的设计中,根据量化和游程编码的特点,将其进行融合,在合理的利用硬件资源的条件下加速编码。
5.搭建RTL级的测试平台,并在FPGA上实现了原形验证。
整个设计可以作为单独的JPEG编码器也可以作为IP核添加到系统中去。能够作为高速JPEG编码器,应用于数码相机、远程医疗、可视电话,手机,桌面视频系统等各种消费类电子产品中。
In recent years, with the development of microelectronic technology, network communications, multimedia and real-time image processing are widely used in electronic consumables. Digital image compression becomes a new hot-point in information industry.
This dissertion mainly introduces the standard of JPEG baseline mode compression, and the architecture, implementation of high speed JPEG encoder, as well as the optimization in speed, area and power consumption. The main work of this dissertion is summarized as follows:
First, this article simply introduce the JPEG standard, implement system level model of JPEG encoder using SystemC language and design the SystemC/HDL co-simulation platform.
Second, the RTL module is implemented, using Top-Down design method and system level model as reference. The RTL design has high compression speed, for the pipeline architecture.
Third, in order to optimize the area and power consumption, the fused constant multiplication and control logic is used in color space convertor. It can save about 30% dynamic power consumption in low sample rate.
Forth, quantization and run-length encode are fused to speed up encoding and reduce area.
Finally, the RTL level testbench and the verification on FPGA are implemented.
The whole design can be used independently and also could be integrated in other system. As JPEG encoder, it can be used in many kinds of electronic consumables such as digital camera, visualphone, cellphone, desktop video, and so on.
本文主要介绍了JPEG基本模式的编码规范,高速JPEG编码器的整体设计思想、结构和具体实现,并在此基础上针对速度,面积和功耗上进行了一些优化研究。
论文的主要工作如下:
1.对JPEG编码标准进行了分析,采用SystemC语言对JPEG编码器进行系统级建模,并利用完成的事务级模型建立了SystemC/HDL混合语言仿真平台。
2.参考系统级模型的模块划分,采用Top-Down的模块化设计方法,完成了JPEG高速编码器的RTL设计,实现了编码全过程的流水线结构。
3.在色彩空间转换模块的设计中,通过引入共享的固定常数乘法器,并加入优化的控制逻辑,减小电路功耗30%以上。
4.在量化模块的设计中,根据量化和游程编码的特点,将其进行融合,在合理的利用硬件资源的条件下加速编码。
5.搭建RTL级的测试平台,并在FPGA上实现了原形验证。
整个设计可以作为单独的JPEG编码器也可以作为IP核添加到系统中去。能够作为高速JPEG编码器,应用于数码相机、远程医疗、可视电话,手机,桌面视频系统等各种消费类电子产品中。
In recent years, with the development of microelectronic technology, network communications, multimedia and real-time image processing are widely used in electronic consumables. Digital image compression becomes a new hot-point in information industry.
This dissertion mainly introduces the standard of JPEG baseline mode compression, and the architecture, implementation of high speed JPEG encoder, as well as the optimization in speed, area and power consumption. The main work of this dissertion is summarized as follows:
First, this article simply introduce the JPEG standard, implement system level model of JPEG encoder using SystemC language and design the SystemC/HDL co-simulation platform.
Second, the RTL module is implemented, using Top-Down design method and system level model as reference. The RTL design has high compression speed, for the pipeline architecture.
Third, in order to optimize the area and power consumption, the fused constant multiplication and control logic is used in color space convertor. It can save about 30% dynamic power consumption in low sample rate.
Forth, quantization and run-length encode are fused to speed up encoding and reduce area.
Finally, the RTL level testbench and the verification on FPGA are implemented.
The whole design can be used independently and also could be integrated in other system. As JPEG encoder, it can be used in many kinds of electronic consumables such as digital camera, visualphone, cellphone, desktop video, and so on.
引文
[1]G.K.Wallace.The JPEG Still Picture Compression Standard.Commun ACM,1991 Vol.34,Page(s):30-44.
[2]Iain E.G.Richardson[著],视频编解码器设计,欧阳合,韩军[译],国防科技大学出版社,2005,P1,20.
[3]石福建,数码相机图像压缩的研究,硕士学位论文,哈尔滨工业大学,2003
[4]朱虹等,数字图像处理基础,科学出版社,2005
[5]C.E.SHANNON,A Mathematical Theory of Communication.Bell SystemTechnical journal.1948,27:379-423
[6]N.Ahmed,T.Natrajan and K.R.Rao,"Discrete cosine transform",IEEE Trans.Computer,January 1974.
[7]ISO/IEC FCD 154444-1,"JPEG2000 Final Committee Draft v1.0",March 2000
[8]ISO/IEC 10918-1/ITU-T Recommendation T.81,"Digital compression and coding of continuostone still image",1992
[9]Eric Hamilton.JPEG File Interchange Format Version 1.02.September 1,1992
[10]R.Rajsuman,System-on-a-chip Design and Test,Artech House,2000
[11]OSCI.SystemC Versioin2.01 User's Guide,http://www.systemc.org/,2002
[12]陈曦,徐宁仪,SystemC片上系统设计.北京:科学出版社,2004
[13]OSCI.SystemC function specification ver2.1 http:/www.systemc.org
[14]M.Pauwels,A.Berna,F.Ozdemir and Y.Vanderperren,Tutorial:Using SystemC for System-on-Chip Modeling and Design,DAK Forum 2001.
[15]Mentor Graphics Corporation,ModelSim SE User's Manual Version 6.0,July,2004
[16]Modeling Systems with SystemC,Kurt Schwartz,SNUG,2001,Boston.
[17]Stuart Swan,SystemC Transaction Level Models And RTL Verification,DAC 2006,July,24-28
[18]Ali Sayinta,Gorkem Canverdi,Marc Pauwels,etc.A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for Syetem on Chip Verification,IEEE Proceedings of the Design,Automation and Test in Europe Conference and Exhibition(DATA'03),1530-1591/03,2003
[19]Massimo Bombana,Francesco Bruschi,SystemC-VHDL co-simulation and synthesis in HW domain,IEEE Proceedings of the Design,Automation and Test in Europe Conference and Exhibition(DATA'03),1530-1591/03,2003
[20]M.Bartkowiak.Optimizations of Color Transformation for Real TimeVideo Decoding[J].Digital Signal Processing for Multimedia Communications and Services:EURASIP ECMCS 2001,Budapest,September 2001.
[21]Iain E.G.Richardson英 著.H.264和MPEG-4视频压缩系统[M].欧阳合 韩军 译.第一版.湖南长沙:国防科技大学出版社,2004 P17.
[22]P.Tummeltshammer,J.C.Hoe,M.Puschel,Time-Multiplexed Multiple-Constant Multiplication[J].Computer-Aided Design of Integrated Circuits and Systems:IEEE Transactions on Volume 26,Issue 9,Sept.2007Page(s):1551-1563
[23]O.Gustafsson,A.G.Dempster,and L.Wanhammar,Extended results for minimum-adder constant integer multipliers[J].Circuits and Systems,2002.ISCAS 2002.IEEE International Symposium on Volume 1,26-29 May 2002Page(s):Ⅰ-73-Ⅰ-76 vol.1
[24]"Spiral website," http://www.spiral.net
[25]Kjell Holm and Oscar Gustafsson.Low-Complexity and Low-Power Color Space Conversion for Digital Video[J].Norchip Conference,2006.24th Nov.2006 Page(s):179-182
[26]Mouzam Khan.Power Optimization in FPGA Designs[J].Synopsys Users.Group-SNUG San Jose,Mar.2006
[27]ALTERA.QuartusⅡ Handbook,Volume3,Altera Corporation May 2007.www.altera.com
[28]B EROL,F Kossentini,H Alnuweiri.Implementation visual of a fast H.263+encoder/decoder[A].Conference Record of the 32nd Asilomar Conference on signals,Systems& Computers[C].1998-09,1:462-466
[29]陈禾,毛志刚,叶以正.DCT快速算法及其VLSI实现.信号处理,1998,14:62-70
[30]W.H.Chen,C.H.Smith and S.C.Fralick,A fast computational algorithm for the discrete cosine transform,IEEE Trans.Commun.,1977,COM-25:1004-1009
[31]P.Soderquist and M.Leeser.Area and performance tradeoffs in floatingpoint divide and square-root implementations.ACM Computing Surveys(CSUR),1996:28(3):518-564
[32]R.Z.Goldschmidt.Applications of Division by Convergence.M aster's thesis,Department of Electrical Engineering,Massachusetts Institute of Technology Cambridge,MA,USA,1964.6
[33] TOCHER K D. Techniques of multiplication and division for automatic binary computers Quarterly J.Mech. Appl. Math., 1958, 11 (3) : 364-384.
[34] http://www.lena.org
[35] http://www.bilsen.com
[2]Iain E.G.Richardson[著],视频编解码器设计,欧阳合,韩军[译],国防科技大学出版社,2005,P1,20.
[3]石福建,数码相机图像压缩的研究,硕士学位论文,哈尔滨工业大学,2003
[4]朱虹等,数字图像处理基础,科学出版社,2005
[5]C.E.SHANNON,A Mathematical Theory of Communication.Bell SystemTechnical journal.1948,27:379-423
[6]N.Ahmed,T.Natrajan and K.R.Rao,"Discrete cosine transform",IEEE Trans.Computer,January 1974.
[7]ISO/IEC FCD 154444-1,"JPEG2000 Final Committee Draft v1.0",March 2000
[8]ISO/IEC 10918-1/ITU-T Recommendation T.81,"Digital compression and coding of continuostone still image",1992
[9]Eric Hamilton.JPEG File Interchange Format Version 1.02.September 1,1992
[10]R.Rajsuman,System-on-a-chip Design and Test,Artech House,2000
[11]OSCI.SystemC Versioin2.01 User's Guide,http://www.systemc.org/,2002
[12]陈曦,徐宁仪,SystemC片上系统设计.北京:科学出版社,2004
[13]OSCI.SystemC function specification ver2.1 http:/www.systemc.org
[14]M.Pauwels,A.Berna,F.Ozdemir and Y.Vanderperren,Tutorial:Using SystemC for System-on-Chip Modeling and Design,DAK Forum 2001.
[15]Mentor Graphics Corporation,ModelSim SE User's Manual Version 6.0,July,2004
[16]Modeling Systems with SystemC,Kurt Schwartz,SNUG,2001,Boston.
[17]Stuart Swan,SystemC Transaction Level Models And RTL Verification,DAC 2006,July,24-28
[18]Ali Sayinta,Gorkem Canverdi,Marc Pauwels,etc.A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for Syetem on Chip Verification,IEEE Proceedings of the Design,Automation and Test in Europe Conference and Exhibition(DATA'03),1530-1591/03,2003
[19]Massimo Bombana,Francesco Bruschi,SystemC-VHDL co-simulation and synthesis in HW domain,IEEE Proceedings of the Design,Automation and Test in Europe Conference and Exhibition(DATA'03),1530-1591/03,2003
[20]M.Bartkowiak.Optimizations of Color Transformation for Real TimeVideo Decoding[J].Digital Signal Processing for Multimedia Communications and Services:EURASIP ECMCS 2001,Budapest,September 2001.
[21]Iain E.G.Richardson英 著.H.264和MPEG-4视频压缩系统[M].欧阳合 韩军 译.第一版.湖南长沙:国防科技大学出版社,2004 P17.
[22]P.Tummeltshammer,J.C.Hoe,M.Puschel,Time-Multiplexed Multiple-Constant Multiplication[J].Computer-Aided Design of Integrated Circuits and Systems:IEEE Transactions on Volume 26,Issue 9,Sept.2007Page(s):1551-1563
[23]O.Gustafsson,A.G.Dempster,and L.Wanhammar,Extended results for minimum-adder constant integer multipliers[J].Circuits and Systems,2002.ISCAS 2002.IEEE International Symposium on Volume 1,26-29 May 2002Page(s):Ⅰ-73-Ⅰ-76 vol.1
[24]"Spiral website," http://www.spiral.net
[25]Kjell Holm and Oscar Gustafsson.Low-Complexity and Low-Power Color Space Conversion for Digital Video[J].Norchip Conference,2006.24th Nov.2006 Page(s):179-182
[26]Mouzam Khan.Power Optimization in FPGA Designs[J].Synopsys Users.Group-SNUG San Jose,Mar.2006
[27]ALTERA.QuartusⅡ Handbook,Volume3,Altera Corporation May 2007.www.altera.com
[28]B EROL,F Kossentini,H Alnuweiri.Implementation visual of a fast H.263+encoder/decoder[A].Conference Record of the 32nd Asilomar Conference on signals,Systems& Computers[C].1998-09,1:462-466
[29]陈禾,毛志刚,叶以正.DCT快速算法及其VLSI实现.信号处理,1998,14:62-70
[30]W.H.Chen,C.H.Smith and S.C.Fralick,A fast computational algorithm for the discrete cosine transform,IEEE Trans.Commun.,1977,COM-25:1004-1009
[31]P.Soderquist and M.Leeser.Area and performance tradeoffs in floatingpoint divide and square-root implementations.ACM Computing Surveys(CSUR),1996:28(3):518-564
[32]R.Z.Goldschmidt.Applications of Division by Convergence.M aster's thesis,Department of Electrical Engineering,Massachusetts Institute of Technology Cambridge,MA,USA,1964.6
[33] TOCHER K D. Techniques of multiplication and division for automatic binary computers Quarterly J.Mech. Appl. Math., 1958, 11 (3) : 364-384.
[34] http://www.lena.org
[35] http://www.bilsen.com