可重构阵列自测试与容错技术研究
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摘要
随着半导体工艺与集成电路的不断发展,数字电子系统的集成度越来越高,它在生命周期中发生故障的可能性也随之增大。因此,数字电子系统的容错能力逐渐受到了人们的重视。可重构阵列具有可重复编程、功能灵活、集成度高、开发周期短与研发成本低等优点,在电子系统设计中已经得到了广泛应用,它的出现为电子系统的容错提供了更为灵活的方法。目前,可重构阵列的自测试与容错技术已经成为研究热点之一。
本文主要研究了可重构阵列的自测试与容错技术,论文的主要研究工作如下:
(1)通过改进设计使可重构阵列有两种工作模式:普通工作模式和故障自测试工作模式。其中,当可重构阵列处于对安全性要求较高的条件下时,可以拉低测试使能信号使其工作在自测试模式。可重构阵列采用在线循环自测试方法,故障测试时并不影响阵列执行正常的逻辑功能。
(2)针对可重构阵列冗余资源利用率低以及时间开销大等问题,本文设计了两层容错机制:1)在测试到故障后,首先在细胞单元内部以空闲的基本逻辑单元为重构对象完成第一层容错,此过程不需要内建容错处理单元的参与,实现自主容错;2)当细胞单元内部没有空闲的基本逻辑单元时,通过调用内建容错处理单元发出控制命令,以距故障细胞单元最近的空闲细胞单元取代故障细胞单元来实现第二层容错。
(3)本文最后以六位并行乘法器和六位并入串出移位寄存器为例实现在阵列上的映射,对其仿真并下板测试,验证了可重构阵列的自测试与容错能力,并和其它可重构阵列容错技术的容错能力、冗余资源利用率和容错时间进行了分析对比,说明本文设计结构具有容错性能好、资源利用率小和时间开销小等方面的优势。
本课题研究工作受国家自然科学基金(60871009)和航空科学基金(2009ZD52045)的资助。
With the continuous development of the semiconductor technology and the integrated circuit, digital electronic system are more integrated, and its possibility of failure in the life cycle is even greater. Therefore, people gradually start to attach importance to the fault-tolerant ability in digital electronic system. The reconfigurable array has the characteristic of a repeatable programming, functional flexibility, high integration, short development cycle and low cost of research. The reconfigurable array has been widely used in the design of electronic system, It also provides a more flexible approach for fault-tolerant electronic system. Currently, self-test and fault-tolerant technology of reconfigurable array has become a research hot spot.
This paper mainly studies the self-test and fault-tolerant technology of reconfigurable array, major research are as follows:
(1) By improving the reconfigurable array, there are two operation modes: normal operation mode and self-test operation mode. When the reconfigurable array is in a higher degree of security conditions required, you can pull down test enable signal to make it work in self-test mode. It uses online circular self-test method, fault self-test doesn’t affect the implementation of normal logic functions.
(2) The reconfigurable array has the low utilization rate of resources and needs more time, this paper designed a two-level fault-tolerant method: 1) When the fault has been tested, first, using the spare BLE to achieve the first-level fault-tolerant, this process doesn’t need the participation of build-in fault-tolerant processing unit; 2) When the cell unit lacks the spare BLE, by calling the build-in fault-tolerant processing unit to issue control commands, the nearest spare cell unit will replace the fault cell unit to achieve the second-level fault tolerance.
(3) This paper exemplifies 6-bits parallel multiplier and 6-bits string out shift register, which are simulated and downloaded to FPGA board, to verify the fault-tolerant ability of reconfigurable array. By analysing and comparing with other reconfigurable arrays in fault-tolerant ability, resource utilization and fault tolerance time, the results show that the structure designed in this paper improves the resource utilization and reduces the time overhead.
The work presented in this paper has been funded by National Natural Science Foundation of China (60871009) and Aeronautical Science Foundation of China (2009ZD52045).
本文主要研究了可重构阵列的自测试与容错技术,论文的主要研究工作如下:
(1)通过改进设计使可重构阵列有两种工作模式:普通工作模式和故障自测试工作模式。其中,当可重构阵列处于对安全性要求较高的条件下时,可以拉低测试使能信号使其工作在自测试模式。可重构阵列采用在线循环自测试方法,故障测试时并不影响阵列执行正常的逻辑功能。
(2)针对可重构阵列冗余资源利用率低以及时间开销大等问题,本文设计了两层容错机制:1)在测试到故障后,首先在细胞单元内部以空闲的基本逻辑单元为重构对象完成第一层容错,此过程不需要内建容错处理单元的参与,实现自主容错;2)当细胞单元内部没有空闲的基本逻辑单元时,通过调用内建容错处理单元发出控制命令,以距故障细胞单元最近的空闲细胞单元取代故障细胞单元来实现第二层容错。
(3)本文最后以六位并行乘法器和六位并入串出移位寄存器为例实现在阵列上的映射,对其仿真并下板测试,验证了可重构阵列的自测试与容错能力,并和其它可重构阵列容错技术的容错能力、冗余资源利用率和容错时间进行了分析对比,说明本文设计结构具有容错性能好、资源利用率小和时间开销小等方面的优势。
本课题研究工作受国家自然科学基金(60871009)和航空科学基金(2009ZD52045)的资助。
With the continuous development of the semiconductor technology and the integrated circuit, digital electronic system are more integrated, and its possibility of failure in the life cycle is even greater. Therefore, people gradually start to attach importance to the fault-tolerant ability in digital electronic system. The reconfigurable array has the characteristic of a repeatable programming, functional flexibility, high integration, short development cycle and low cost of research. The reconfigurable array has been widely used in the design of electronic system, It also provides a more flexible approach for fault-tolerant electronic system. Currently, self-test and fault-tolerant technology of reconfigurable array has become a research hot spot.
This paper mainly studies the self-test and fault-tolerant technology of reconfigurable array, major research are as follows:
(1) By improving the reconfigurable array, there are two operation modes: normal operation mode and self-test operation mode. When the reconfigurable array is in a higher degree of security conditions required, you can pull down test enable signal to make it work in self-test mode. It uses online circular self-test method, fault self-test doesn’t affect the implementation of normal logic functions.
(2) The reconfigurable array has the low utilization rate of resources and needs more time, this paper designed a two-level fault-tolerant method: 1) When the fault has been tested, first, using the spare BLE to achieve the first-level fault-tolerant, this process doesn’t need the participation of build-in fault-tolerant processing unit; 2) When the cell unit lacks the spare BLE, by calling the build-in fault-tolerant processing unit to issue control commands, the nearest spare cell unit will replace the fault cell unit to achieve the second-level fault tolerance.
(3) This paper exemplifies 6-bits parallel multiplier and 6-bits string out shift register, which are simulated and downloaded to FPGA board, to verify the fault-tolerant ability of reconfigurable array. By analysing and comparing with other reconfigurable arrays in fault-tolerant ability, resource utilization and fault tolerance time, the results show that the structure designed in this paper improves the resource utilization and reduces the time overhead.
The work presented in this paper has been funded by National Natural Science Foundation of China (60871009) and Aeronautical Science Foundation of China (2009ZD52045).
引文
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[22]荣昊亮,俞承芳.基于胚胎细胞阵列可容错系统的FPGA验证.复旦学报,2006, 45(1): 127~130.
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[31] Canham R O, Tyrrell A M. A hardware artificial immune system and embryonic array for fault tolerant systems. Genetic Programming and Evolvable Machines, 2003, 4(4): 359~382.
[32]胡谋.计算机容错技术.北京:中国铁道出版社,1995: 10~15.
[33]张媛.面向芯片级自修复的胚胎电子电路设计与实现,[硕士学位论文].南京:南京航空航天大学,2008.
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[2] Dan Fay, Shye A, Bhattacharya S, et al. An adaptive fault-tolerant memory system for FPGA-based architectures in the space environment. 2007 2nd NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, CA, USA, IEEE Computer Society, 2007: 233~240.
[3] Shu Yi Yu. Fault tolerance in adaptive real-time computing systems, [Ph.D. dissertation]. Stanford: Stanford University, 2001.
[4] Hatori, Sakurai, Sawada. Introducing redundancy in field programmable gate arrays. In Proceedings of the IEEE Custom Integrated Circuits Conference, Los Alamitos, CA, USA, IEEE Computer Society, 1993: 711~714.
[5] Hanchek, Dutt. Methodologies for tolerating cell and interconnect faults in FPGAs, IEEE Transactions On Computers, 1998, 47(1): 15~33.
[6] Narasimhan, Nakajima, Rim, et al. Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. IEEE transactions on computer-aided design of integrated circuits and systems, 1994, 13(8): 976~986.
[7] Hanchek, Dutt. Node-covering based defect and fault tolerance methods for increased yield in FPGAs. In Proceedings of the 9th International Conference on VLSI Design, Los Alamitos, CA, IEEE Computer Society, 1996: 225~229.
[8] Emmert M, Stroud C E, Abramovici M. Online fault tolerance for FPGA logic blocks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007, 15(2): 216~226.
[9] Abramovici M, Stroud C E, Emmert M. Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(12): 1284~1294.
[10] Jing Huang, Tahoori M B, Lombardi F. Fault tolerance of switch blocks and switch block arrays in FPGA. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(7): 794~807.
[11] Jing Huang, Tahoori M B, Lombardi F. Routability and fault tolerance of FPGA interconnect architectures. Proceedings of International Test Conference, Piscataway, NJ, USA, IEEEComputer Society, 2004: 479~488.
[12] Mange D, Goeke M, Madon D, et al. Embryonics: a new family of coarse-grained field-programmable gate array with self-repair and self-reproducing properties. IEEE International Symposium on Circuits and Systems, New York, NY, USA, IEEE Computer Society, 1996: 25~28.
[13] Tyrrell A, Hong Sun. A Honeycomb Development Architecture for Robust Fault-Tolerant Design. Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06), Institute of Electrical and Electronics Engineers Computer Society, Piscataway, NJ, USA, IEEE Computer Society, 2006: 281~287.
[14] Mange D, AndréStauffer, Enrico Petraglio, et al. Embryonic Machines That Divide and Differentiate. Proceedings of the 1st International Workshop on Biologically Inspired Approaches to Advanced Information Technology(BioADIT 2004), Berlin, Germany, Springer-Verlag, 2004: 201~216.
[15] Durbeck L J K, Macias N J. Defect-tolerant, fine-grained parallel testing of a cell matrix. Proceedings of the SPIE-The International Society for Optical Engineering, Los Alamitos, CA, USA, SPIE-Int. Soc. Opt. Eng, 2002: 71~85.
[16] Saha R C, Bellis J S, Mathewson A, et al. Performance Enhancement Defect Tolerance in the Cell Matrix Architecture. International Conference on Mircoelectronic, Piscataway, NJ, USA, IEEE Computer Society, 2004: 777~780.
[17]任小西,李仁发,金声震等.基于JBits的一种可重构数据处理系统可靠性研究.计算机研究与发展,2007, 44(4): 722~728.
[18]徐斌,王贞松,陈冰冰等.适用于空间环境下的FPGA容错与重构体系.计算机工程,2007, 33(3): 231~233.
[19]黄影,张春元,刘东.基于FPGA双机容错系统的设计与实现.深圳大学学报,2006, 23(2): 112~116.
[20]刘慧,朱明程.生物启发式容错系统的可靠性分析.半导体技术,2002, 27(2): 36~40.
[21]王宁,刘慧,朱明程.基于SRAM FPGA的MuxTree结构模型的可容错全加器的设计.半导体技术,2003, 28 (5): 61~64.
[22]荣昊亮,俞承芳.基于胚胎细胞阵列可容错系统的FPGA验证.复旦学报,2006, 45(1): 127~130.
[23]赵倩,俞承芳.胚胎电子阵列容错系统中单细胞替换的实现.复旦学报,2006, 45(4): 550~554.
[24]林勇.基于进化型硬件的容错方法研究,[博士学位论文].合肥:中国科学技术大学,2007.
[25]杨孝宗.容错技术与STRATUS容错计算机.哈尔滨:哈尔滨工业大学出版社,1993: 28~30.
[26]邹逢兴.计算机应用系统的故障诊断与可靠性技术基础.北京:高等教育出版社,1999: 75~80.
[27] Chmelar Erik. The test and diagnosis of FPGAs, [Ph.D. dissertation]. Stanford: Stanford University, 2004.
[28] Kyriakoulakos K, Pnevmatikatos D. A novel SRAM based FPGA architecture for efficient TMR fault tolerance support. 2009 International Conference on Field Programmable Logic and Applications (FPL), Piscataway, NJ, USA, IEEE Computer Society, 2009: 193~198.
[29] Xuegong Zhang. Biologically inspired highly reliable electronic systems with self-healing cellular architecture, [Ph.D. dissertation]. Bristol: University of the West of England, 2005.
[30] Bradley W D, Tyrrell A M. Immunotronics-Novel Finite-State-Machine Architectures With Built-In Self-Test Using Self-Nonself Differentiation. IEEE Transactions on Evolutionary Computation, 2002, 6(3): 227~238.
[31] Canham R O, Tyrrell A M. A hardware artificial immune system and embryonic array for fault tolerant systems. Genetic Programming and Evolvable Machines, 2003, 4(4): 359~382.
[32]胡谋.计算机容错技术.北京:中国铁道出版社,1995: 10~15.
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