基于CPLD控制的ESD信号发生器
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摘要
人体在日常生活中通过接触、感应、吸附而带电。当带电的人手碰触电子元器件或者集成电路(IC)时,人体的静电得以释放,其产生的高压脉冲信号可造成电子系统的永久性失效。特别是在集成电路(IC)领域,由于器件的特征尺寸的持续减小,使器件本身的栅极耐压减小,而外界的静电积累却没有减少。所以ESD的影响显得更加突出。研究ESD放电模型,设计符合实际情况的静电放电发生器对我们深入了解放电机理、测试半导体电子产品抗ESD能力以及提出器件和芯片的ESD保护方法具有重要的意义。
本文依据IEEE有关ESD测试的相关标准,利用常见的电子元器件设计并制做了用于ESD测试的高压脉冲发生器。本文的核心工作是利用ALTERA公司CPLD器件作为核心控制单元、一体式行回扫变压器作为直流高压源、串联SCR作为高压开关设计并制作了一种新型的ESD静电脉冲发生器。测试结果表明,这种电压发生器可以最高产生8kV的电压脉冲,整个放电脉冲周期为150ns左右,脉冲上升时间为10-20ns,符合IEEE Std C62,38-1994的ESD人体模型标准。并且本装置可以产生预设最大999次脉冲个数。必要情况下在自动脉冲计数放电时,每次放电的时间间隔也是可调的。因为本装置的大部分原件都是常见的半导体元器件,制作方便成本较小,且易于操作。
In the day-to-day activities, the human body can get the charge through contact, separation, and the friction process.when people use their fingers, which are charged with electrons to touch an electrical device or electrical system, the Electro-Static discharge through the path between human body and electrical device. There are high voltage pulse and high current pulse forced on electrical device when Electro-Static discharge (ESD) happens. These high voltage and current is fatal to the electrical device, which take perpetuity destroys to electrical device. As technology in integrated circuit(IC) continues to scale, the diagnostic size has been decreased significantly. As a result, the gain of MOSFET has lower reverse voltage tolerance. Therefore, ESD becomes more and more important and needs to be handled as a key problem in the IC chips'manufactured and using. As described above, to go deep into the mechanism of ESD, and find new method to protect electrical device from ESD, the study on ESD Model and design of the ESD voltage generator are extraordinarily significant.
In this thesis, a high voltage generator for ESD testing is designed with ordinary electronic device according to IEEE standard. The main work mentioned in this thesis is design of a new Electrostatic Discharge (ESD) generator based on CPLD. The design incorporates a CPLD as the key controller, fly-back transformer as high voltage DC source and serial connection of SCR as high voltage switch. And results show that, the generator expressed in this paper has reached its limited voltage at 8kV. During the whole 200ns discharge circle, setup time is less than 20ns, which accord with IEEE STD C62,38-1994. Additionally, this generator produces high voltage automatically for certain times. These times are less than 999, which depend on the number set by costumer. If it's necessary, every interval between two discharge pulses is alterable. Since the components of this instrument are easy to get, and the price is pretty low, so the entire generator is inexpensive and friendly to operate.
本文依据IEEE有关ESD测试的相关标准,利用常见的电子元器件设计并制做了用于ESD测试的高压脉冲发生器。本文的核心工作是利用ALTERA公司CPLD器件作为核心控制单元、一体式行回扫变压器作为直流高压源、串联SCR作为高压开关设计并制作了一种新型的ESD静电脉冲发生器。测试结果表明,这种电压发生器可以最高产生8kV的电压脉冲,整个放电脉冲周期为150ns左右,脉冲上升时间为10-20ns,符合IEEE Std C62,38-1994的ESD人体模型标准。并且本装置可以产生预设最大999次脉冲个数。必要情况下在自动脉冲计数放电时,每次放电的时间间隔也是可调的。因为本装置的大部分原件都是常见的半导体元器件,制作方便成本较小,且易于操作。
In the day-to-day activities, the human body can get the charge through contact, separation, and the friction process.when people use their fingers, which are charged with electrons to touch an electrical device or electrical system, the Electro-Static discharge through the path between human body and electrical device. There are high voltage pulse and high current pulse forced on electrical device when Electro-Static discharge (ESD) happens. These high voltage and current is fatal to the electrical device, which take perpetuity destroys to electrical device. As technology in integrated circuit(IC) continues to scale, the diagnostic size has been decreased significantly. As a result, the gain of MOSFET has lower reverse voltage tolerance. Therefore, ESD becomes more and more important and needs to be handled as a key problem in the IC chips'manufactured and using. As described above, to go deep into the mechanism of ESD, and find new method to protect electrical device from ESD, the study on ESD Model and design of the ESD voltage generator are extraordinarily significant.
In this thesis, a high voltage generator for ESD testing is designed with ordinary electronic device according to IEEE standard. The main work mentioned in this thesis is design of a new Electrostatic Discharge (ESD) generator based on CPLD. The design incorporates a CPLD as the key controller, fly-back transformer as high voltage DC source and serial connection of SCR as high voltage switch. And results show that, the generator expressed in this paper has reached its limited voltage at 8kV. During the whole 200ns discharge circle, setup time is less than 20ns, which accord with IEEE STD C62,38-1994. Additionally, this generator produces high voltage automatically for certain times. These times are less than 999, which depend on the number set by costumer. If it's necessary, every interval between two discharge pulses is alterable. Since the components of this instrument are easy to get, and the price is pretty low, so the entire generator is inexpensive and friendly to operate.
引文
[1]电子元器件抗ESD技术讲义,信息产业部电子第五研究所元器件可靠性研究分析中心,pp.04-10.
[2]A. Amerasekera and C. Duwury, ESD in silicon integrated circuits, second edition:John Wiley&Sons, Ltd.,2002.
[3]A. Z. H. Wang, On-chip ESD Protection for Integrated Circuits an IC designs perspective: Kluwer Academic 2002.
[4]S. H. Voldman, ESD:Physics and Device, John Wiley&Sons, Ltd,2006.
[5]L. Wen-Yu and K. Ming-Dou, Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing no connected balls IEEE Transactions on Device and Materials Reliability,2004 vol. (4):24-31.
[6]Pee-Ya Tan Indrajit, M. Pian-Hong Li Voldman, RC-triggered PNP and NPN simultaneously switched silicon controlled rectifier ESD networks for sub-0.18 μ m technology, in Physical and Failure Analysis of Integrated Circuits,2005. IPFA 2005. Proceedings of the 12th International Symposium, pp.71-75.
[7]A. Weger, S. Voldman, F. Stellari, Peilin Song, Pia Sanda, and M. McManus, Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup, Reliability Physics Symposium Proceedings,2003.41st Annual.2003 IEEE International,2003, pp.99-104.
[8]J. Dunn, D. Harame, St. Onge, A. Joseph, N. Feilchenfeld, K. Watson, S. Subbanna, G. Freeman, S. Voldman, D. Ahlgren, and R. Johnson, Trends in silicon germanium BiCMOS integration and reliability, Reliability Physics Symposium,2000. Proceedings.38th Annual 2000 IEEE International,2000, pp.237-242.
[9]JEDEC Std A114-A, Electrostatic discharge (ESD) sensitivity testing human body model (HBM), IEEE,1997.
[10]JEDEC Std A115-A, Electrostatic discharge (ESD) sensitivity testing machine model (MM), IEEE,1997.
[11]JEDEC Std JESD22-C101-A, Field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components, IEEE,2000.
[12]K. Ming-Dou, P. Jeng-Jie, and J. Hsin-Chin, ESD test methods on integrated circuits:an overview, Electronics Circuits and Systems,2001. ICECS 2001. The 8th IEEE International conference,2001, vol. (2):1011-1014.
[13]K.Ming-Dou and L.Kun-Hsian, Double snapback characteristics in high-voltage n-MOSFETs and the impact to on-chip ESD protection design" IEEE Electron Device Letters,2004,vol. (25):640-642.
[14]K. Ming-Dou, J. Hsin-Chin, and C. Chyh-Yih, Design on the low-Capacitance bond Pad for high-frequency I/O circuits in CMOS technology. IEEE Transactions on Electron Devices 2001,vol.(48):2953-2956.
[15]H. Hyatt, J. Harris, A. Alanzo, and P. A. B. P. Bellew, TLP measurements for verification of ESD protection device response, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000,2000, pp.111-120.
[16]J. J.Li, Characterization, design, and modeling of on-chip electrostatic discharge protection devices, Ph.D. thesis, University of Illinois at Urbana-Champaign,2004.
[17]陆坚：IC静电放电的测试.《电子与封装》,2004,vol.(1)：37-43.
[18]A. Ortiz-Conde, F. J. Garcia-Sanchez, J. Muci, S. Malobabic, and J. J. Liou, A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs, Electron Devices, IEEE Transactions on,2007,vol. (54):131-140.
[19]R.L. Minear and GA.Dodson, Effects of Electrostatic Discharge on Linear Bipolar Integrated Circuits, Reliability Physics Symposium,1977, pp.138-143.
[20]J. J. Liou, JA. Salcedo, and Z. Liu, Robust ESD Protection Solutions in CMOS/BiCMOS Technologies, Electron Devices and Semiconductor Technology,2007. EDST 2007. Proceeding of 2007 International Workshop,2007, pp.41-45.
[21]秦曾衍,左公宁,王永荣等.高压强脉冲放电及其应用,北京：北京工业大学出版社,2000,pp.10-16.
[22]李网生,夏贤江,云彬.固态开关器件的串联技术.电力电子技术.2004,38(6)：94-96.
[23]邱冠铭.电子装置静电放电测试的模拟与试验.台湾,国立中山大学电机工程学系,2004.
[24]ZHU Chang-qing, LIU Shang-he, WEI Ming,et al. An analysis and calculation on spectrum of ESD current.High Voltage Engineering,2003,29 (8):23-25.
[25]刘畅.固态开关串联型纳秒级上升时间功率脉冲发生技术的研究,硕士学位论文,哈尔滨工业大学,2006.
[26]J. A. Salcedo, J. J. Liu, L Zhiwei, and J. E. Vinson, TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications, Electron Devices, IEEE Transactions on,2007,vol. (54):822-832.
[27]BEN.GSTREETMAN, SANJAY BANERJEE,杨建红译。《固体电子器件》(第五版),兰州大学出版社,2005,pp.386-387.
[28]IEEE Std C62,38-1994, IEEE Guide on Electrostatic Discharge (ESD):ESD Withstand Capability Evaluation Methods (for Electronic Equipment Subassemblies).
[29]ANSI/ESD STM5.1-2001. ESD association standard test method for Electrostatic Discharge sensitivity testing. March 20,2003.
[2]A. Amerasekera and C. Duwury, ESD in silicon integrated circuits, second edition:John Wiley&Sons, Ltd.,2002.
[3]A. Z. H. Wang, On-chip ESD Protection for Integrated Circuits an IC designs perspective: Kluwer Academic 2002.
[4]S. H. Voldman, ESD:Physics and Device, John Wiley&Sons, Ltd,2006.
[5]L. Wen-Yu and K. Ming-Dou, Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing no connected balls IEEE Transactions on Device and Materials Reliability,2004 vol. (4):24-31.
[6]Pee-Ya Tan Indrajit, M. Pian-Hong Li Voldman, RC-triggered PNP and NPN simultaneously switched silicon controlled rectifier ESD networks for sub-0.18 μ m technology, in Physical and Failure Analysis of Integrated Circuits,2005. IPFA 2005. Proceedings of the 12th International Symposium, pp.71-75.
[7]A. Weger, S. Voldman, F. Stellari, Peilin Song, Pia Sanda, and M. McManus, Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup, Reliability Physics Symposium Proceedings,2003.41st Annual.2003 IEEE International,2003, pp.99-104.
[8]J. Dunn, D. Harame, St. Onge, A. Joseph, N. Feilchenfeld, K. Watson, S. Subbanna, G. Freeman, S. Voldman, D. Ahlgren, and R. Johnson, Trends in silicon germanium BiCMOS integration and reliability, Reliability Physics Symposium,2000. Proceedings.38th Annual 2000 IEEE International,2000, pp.237-242.
[9]JEDEC Std A114-A, Electrostatic discharge (ESD) sensitivity testing human body model (HBM), IEEE,1997.
[10]JEDEC Std A115-A, Electrostatic discharge (ESD) sensitivity testing machine model (MM), IEEE,1997.
[11]JEDEC Std JESD22-C101-A, Field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components, IEEE,2000.
[12]K. Ming-Dou, P. Jeng-Jie, and J. Hsin-Chin, ESD test methods on integrated circuits:an overview, Electronics Circuits and Systems,2001. ICECS 2001. The 8th IEEE International conference,2001, vol. (2):1011-1014.
[13]K.Ming-Dou and L.Kun-Hsian, Double snapback characteristics in high-voltage n-MOSFETs and the impact to on-chip ESD protection design" IEEE Electron Device Letters,2004,vol. (25):640-642.
[14]K. Ming-Dou, J. Hsin-Chin, and C. Chyh-Yih, Design on the low-Capacitance bond Pad for high-frequency I/O circuits in CMOS technology. IEEE Transactions on Electron Devices 2001,vol.(48):2953-2956.
[15]H. Hyatt, J. Harris, A. Alanzo, and P. A. B. P. Bellew, TLP measurements for verification of ESD protection device response, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000,2000, pp.111-120.
[16]J. J.Li, Characterization, design, and modeling of on-chip electrostatic discharge protection devices, Ph.D. thesis, University of Illinois at Urbana-Champaign,2004.
[17]陆坚：IC静电放电的测试.《电子与封装》,2004,vol.(1)：37-43.
[18]A. Ortiz-Conde, F. J. Garcia-Sanchez, J. Muci, S. Malobabic, and J. J. Liou, A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs, Electron Devices, IEEE Transactions on,2007,vol. (54):131-140.
[19]R.L. Minear and GA.Dodson, Effects of Electrostatic Discharge on Linear Bipolar Integrated Circuits, Reliability Physics Symposium,1977, pp.138-143.
[20]J. J. Liou, JA. Salcedo, and Z. Liu, Robust ESD Protection Solutions in CMOS/BiCMOS Technologies, Electron Devices and Semiconductor Technology,2007. EDST 2007. Proceeding of 2007 International Workshop,2007, pp.41-45.
[21]秦曾衍,左公宁,王永荣等.高压强脉冲放电及其应用,北京：北京工业大学出版社,2000,pp.10-16.
[22]李网生,夏贤江,云彬.固态开关器件的串联技术.电力电子技术.2004,38(6)：94-96.
[23]邱冠铭.电子装置静电放电测试的模拟与试验.台湾,国立中山大学电机工程学系,2004.
[24]ZHU Chang-qing, LIU Shang-he, WEI Ming,et al. An analysis and calculation on spectrum of ESD current.High Voltage Engineering,2003,29 (8):23-25.
[25]刘畅.固态开关串联型纳秒级上升时间功率脉冲发生技术的研究,硕士学位论文,哈尔滨工业大学,2006.
[26]J. A. Salcedo, J. J. Liu, L Zhiwei, and J. E. Vinson, TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications, Electron Devices, IEEE Transactions on,2007,vol. (54):822-832.
[27]BEN.GSTREETMAN, SANJAY BANERJEE,杨建红译。《固体电子器件》(第五版),兰州大学出版社,2005,pp.386-387.
[28]IEEE Std C62,38-1994, IEEE Guide on Electrostatic Discharge (ESD):ESD Withstand Capability Evaluation Methods (for Electronic Equipment Subassemblies).
[29]ANSI/ESD STM5.1-2001. ESD association standard test method for Electrostatic Discharge sensitivity testing. March 20,2003.