视频处理DSP中外部存储器接口的设计与实现
|
摘要
音视频编/解码技术的实现方法主要有采用专用编/解码芯片和基于DSP的软件编/解码两种技术。后者因其具有较强的灵活性、可扩展性和可控性,逐渐成为主流的编/解码技术之一。视频处理的一大特点在于其高数据流量和高带宽消耗,因此存储接口的性能就成为了影响视频DSP性能的关键因素之一。我校研制的YHFT-Dx高性能DSP处理器具有很强的处理能力,然而其存储访问速度极大的限制了其音视频处理能力。
本文针对YHFT-Dx需进一步提升存储访问速度的需求,设计实现了YHFT-Dx的外部存储器接口,扩展了YHFT-Dx的存储访问能力,使其可以同时支持DDR2 SDRAM存储器和异步存储器。设计中采用了基于异步FIFO的缓冲、固定请求优先级下的令牌轮转、基于Cache行偏移量优先读取、双通道多频率存储控制等设计技术,有效提升了流媒体存储访问速度。论文给出了读写请求派发、读写请求缓冲、DDR2访问控制器、异步访问控制器、控制寄存器组等各部件的详细描述,并进行了详细的模拟验证。通过本文的工作,YHFT-Dx不但能够更好地支持异步存储器,还能够支持速度更快,容量更大的DDR2 SDRAM存储器。
支持DDR2 SDRAM的存储接口的配套实现,使得进一步提高视频DSP的性能和适用范围成为可能,也为今后进一步的研究打下了良好的基础。
The technology for audio/video coding/decoding is mainly implemented by two methods, the specific coder/decoder chips, and the coding/decoding algorithms based on DSPs. The latter becomes the mainstream for video coding/decoding due to its strong flexibility, extendibility and controllability. High data stream and bandwidth requirement is the main characteristic of video processing. Thus, the performance of memory interface is vital to VDSP. The high-performance DSP processor YHFT-Dx designed by our university has strong processing ability, but the low speed of memory access limits its utilization for audio/video coding/decoding.
To improve the speed of memory access of DSPs, an innovative external memory interface for YHFT-Dx is proposed in this thesis, which enhances the interface access ability. The key technologies of this design include the asynchronous FIFOs based on buffers, the fixed request priority based on circling token, first reading based on the cache offset, and memory controlling of double channels and multi-frequency. Furthermore, this thesis gives the detail design of read/write requests dispatching unit, the buffer unit of read/write requests, the memory control unit of DDR2 SDRAM, the memory control unit of asynchronous memories, unit of controlling registers and some other components, and gives the detail function verification for this module. The external memory interface designed for YHFT-Dx can support not only asynchronous memories but also DDR2 SDRAM which have higher operation frequency and larger capacity.
The implementation of memory interface supporting DDR2 SDRAM memories further improves the performance of VDSP, expands its application range, and lays a good foundation for further study.
本文针对YHFT-Dx需进一步提升存储访问速度的需求,设计实现了YHFT-Dx的外部存储器接口,扩展了YHFT-Dx的存储访问能力,使其可以同时支持DDR2 SDRAM存储器和异步存储器。设计中采用了基于异步FIFO的缓冲、固定请求优先级下的令牌轮转、基于Cache行偏移量优先读取、双通道多频率存储控制等设计技术,有效提升了流媒体存储访问速度。论文给出了读写请求派发、读写请求缓冲、DDR2访问控制器、异步访问控制器、控制寄存器组等各部件的详细描述,并进行了详细的模拟验证。通过本文的工作,YHFT-Dx不但能够更好地支持异步存储器,还能够支持速度更快,容量更大的DDR2 SDRAM存储器。
支持DDR2 SDRAM的存储接口的配套实现,使得进一步提高视频DSP的性能和适用范围成为可能,也为今后进一步的研究打下了良好的基础。
The technology for audio/video coding/decoding is mainly implemented by two methods, the specific coder/decoder chips, and the coding/decoding algorithms based on DSPs. The latter becomes the mainstream for video coding/decoding due to its strong flexibility, extendibility and controllability. High data stream and bandwidth requirement is the main characteristic of video processing. Thus, the performance of memory interface is vital to VDSP. The high-performance DSP processor YHFT-Dx designed by our university has strong processing ability, but the low speed of memory access limits its utilization for audio/video coding/decoding.
To improve the speed of memory access of DSPs, an innovative external memory interface for YHFT-Dx is proposed in this thesis, which enhances the interface access ability. The key technologies of this design include the asynchronous FIFOs based on buffers, the fixed request priority based on circling token, first reading based on the cache offset, and memory controlling of double channels and multi-frequency. Furthermore, this thesis gives the detail design of read/write requests dispatching unit, the buffer unit of read/write requests, the memory control unit of DDR2 SDRAM, the memory control unit of asynchronous memories, unit of controlling registers and some other components, and gives the detail function verification for this module. The external memory interface designed for YHFT-Dx can support not only asynchronous memories but also DDR2 SDRAM which have higher operation frequency and larger capacity.
The implementation of memory interface supporting DDR2 SDRAM memories further improves the performance of VDSP, expands its application range, and lays a good foundation for further study.
引文
[1] 李方慧、王飞、何佩琨编著,TMS320C6000 系列 DSPs 原理与应用-2 版,北京:电子工业出版社,2003 年
[2] www.ti.com
[3] TMS320C6000PeripheralsReference Guide.Literature Number:SPRU190D.Texas Instruments.2001
[4] TMS320C6000PeripheralsReference Guide.Literature Number:SPRS088J.Texas Instruments.2004
[5] www.semiconductors.philips.com
[6] Churoo Park, HoeJu Chung, Yun-Sang Lee, Jae-KwanKim,Jae-JunLee.A 512Mbit, 1.6Gbps /pin DDR3 SDRAM Prototype with CIO Minimization and Self-Calibration Techniques. Symposium on VLSI Circuits Digest of Technical Papers .2005
[7] ISO/IEC 13818-2 “Generic Coding Of Moving Pictures And Associated Audio Information --Video”.November 1994
[8] “PNX1300 Series Media Processors Data Book”.Philips.15 February 2002
[9] “PNX15xx Series Data Book”.Philips.17 March 2006
[10] “PNX17xx Series Data Book”.Philips.17 March 2006
[11] “TMS320DM642 digital Media Processor”.TI.SPRS200-July 2002
[12] “TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Data Manual”.TI.SPRS200C-July 2002
[13] 国防科技大学计算机学院.,“银河飞腾” DSP 开发组,“银河飞腾”-D4B使用数据手册,2004
[14] Clifford E. Cummings. Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs.SNUG-2002. San Jose. CA
[15] William J. Dally, John W. Poulton. Digital Systems Engineering. Cambridge. University Press.1998
[16] 史美萍、窦文华,基于 EPLD 的 PCI 总线仲裁器的设计与实现,电子技术应用
[17] JEDEC STANDARD.Double Data Rate(DDR) SDRAM specification. JESD79C
[18] DDR2 SDRAM Registered DIMM. Micron Technology. 2004
[19] JEDEC STANDARD.DoubleData Rate Ⅱ(DDR2) SDRAM SPECI- FICATION. JESD79-2A
[20] JEDEC DDR SDRAM Specification. 64 MEG: x4, x8, x16, Revision 0.9. 1999(7)
[21] 1Gb: x4, x8, x16 DDR2 SDRAM Part Numbers. Micron Technology. 2004
[22] Jeff Janzen. DDR2 Offers New Features and Functionality. Micron Technology. 2003
[23] 512Mb: x4, x8, x16 DDR2 SDRAM Features. Micron Technology. 2004
[24] Terry Lee, Micron, and Bryan Belk. DDR SDRAM signaling Design Notes. Micro Linear Corporation. 1999(4)
[25] Karthi Palanisamy. DDR2 Controller (267 MHz and Above) Using Virtex-4 Devices. XILINX. 2006(2)
[26] Marc Defossez. Interfacing a 64-Bit DDR Memory Bus to a 32-Bit Microprocessor Bus. XILINX. 2006(2)
[27] Olivier Despaux. DDR SDRAM Controller Using Virtex-4 FPGA Devices. XILINX. 2006(3)
[28] Lakshmi Gopalakrishnan. DDR2 Controller Using Virtex-4 Devices. XILINX. 2006(2)
[29] TMS320C6000 EMIF to External Asynchronous SRAM Interface. Texas Instruments Application Report. SPRA542A -August 2001
[30] SYNCHRONOUS DRAM Data Sheet. Micron Technology. Inc. 2002
[31] Robert M. Losee. A Gray Code Based Ordering for Documents on Shelves: Classification for Browsing and Retrieval. Journal of the American Society for Information Science.1998
[32] Hyuagtak Kim,Sangho Kim,Sungsam Lee,Sungho Jang,Ji-hoonKim.70nm DRAM Technolog for DDR-3Application .2005.IEEE
[33] Smith D J. HDL Chip Design-A practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog. Doone Publication.1996
[34] Robert M. Losee. A Gray Code Based Ordering for Documents on Shelves: Classification for Browsing and Retrieval. Journal of the American Society for Information Science. 1998
[35] David Dempster,Michael Stuart .VERIFICATION METHODOLOGY MANUAL Techniques for Verifying HDL Designs.Published by Teamwork International,2002
[36] AndrewPiziali.FUNCTIONALVERIFICATION COVERAGE MEASUREMENT AND ANALYSIS.KLUWER ACADEMIC PUBLISHERS.2004
[37] Lionel Bening , Harry Foster.Principles of Verifiable RTL Design Second Edition.KLUWER ACADEMIC PUBLISHERS.2001
[38] TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor. Texas Instruments Incorporated. 2002
[39] TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port ReferenceGuide. Texas Instruments Incorporated. 2005
[40] 汪东、马剑武、陈书明,基于 Gray 码的异步 FIFO 接口技术及其应用,计算机工程与科学,第 27 卷,第 1 期
[41] 陈宝民、汪东、马剑武、陈书明,一种高性能 SDRAM 控制器的设计及模拟,第八届计算机工程与工艺学术年会,2003.8
[42] 汪东、陈宝民、陈书明,一种可编程嵌入式异步 SRAM 存储控制器的设计与应用,微电子学,2005.5
[43] 李振涛、陈书明、等,“银河飞腾”高性能数字信号处理器研究进展,计算机研究与发展,2004.12
[44] 汪东、马剑武、陈书明、郭阳,高性能 DSP 中外部存储器接口的关键设计技术,中国计算机大会,2005
[45] 杨文华、罗晓沛,专用集成电路的设计验证方法及一种实际的通用微处理器设计的多级验证体系,计算机研究与发展,1999 Vol .6,NO. 6,P.764-768
[46] 邓丽,高带宽低延时的 DDR2 内存控制器的研究与实现,国防科技大学工学硕士论文
[2] www.ti.com
[3] TMS320C6000PeripheralsReference Guide.Literature Number:SPRU190D.Texas Instruments.2001
[4] TMS320C6000PeripheralsReference Guide.Literature Number:SPRS088J.Texas Instruments.2004
[5] www.semiconductors.philips.com
[6] Churoo Park, HoeJu Chung, Yun-Sang Lee, Jae-KwanKim,Jae-JunLee.A 512Mbit, 1.6Gbps /pin DDR3 SDRAM Prototype with CIO Minimization and Self-Calibration Techniques. Symposium on VLSI Circuits Digest of Technical Papers .2005
[7] ISO/IEC 13818-2 “Generic Coding Of Moving Pictures And Associated Audio Information --Video”.November 1994
[8] “PNX1300 Series Media Processors Data Book”.Philips.15 February 2002
[9] “PNX15xx Series Data Book”.Philips.17 March 2006
[10] “PNX17xx Series Data Book”.Philips.17 March 2006
[11] “TMS320DM642 digital Media Processor”.TI.SPRS200-July 2002
[12] “TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Data Manual”.TI.SPRS200C-July 2002
[13] 国防科技大学计算机学院.,“银河飞腾” DSP 开发组,“银河飞腾”-D4B使用数据手册,2004
[14] Clifford E. Cummings. Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs.SNUG-2002. San Jose. CA
[15] William J. Dally, John W. Poulton. Digital Systems Engineering. Cambridge. University Press.1998
[16] 史美萍、窦文华,基于 EPLD 的 PCI 总线仲裁器的设计与实现,电子技术应用
[17] JEDEC STANDARD.Double Data Rate(DDR) SDRAM specification. JESD79C
[18] DDR2 SDRAM Registered DIMM. Micron Technology. 2004
[19] JEDEC STANDARD.DoubleData Rate Ⅱ(DDR2) SDRAM SPECI- FICATION. JESD79-2A
[20] JEDEC DDR SDRAM Specification. 64 MEG: x4, x8, x16, Revision 0.9. 1999(7)
[21] 1Gb: x4, x8, x16 DDR2 SDRAM Part Numbers. Micron Technology. 2004
[22] Jeff Janzen. DDR2 Offers New Features and Functionality. Micron Technology. 2003
[23] 512Mb: x4, x8, x16 DDR2 SDRAM Features. Micron Technology. 2004
[24] Terry Lee, Micron, and Bryan Belk. DDR SDRAM signaling Design Notes. Micro Linear Corporation. 1999(4)
[25] Karthi Palanisamy. DDR2 Controller (267 MHz and Above) Using Virtex-4 Devices. XILINX. 2006(2)
[26] Marc Defossez. Interfacing a 64-Bit DDR Memory Bus to a 32-Bit Microprocessor Bus. XILINX. 2006(2)
[27] Olivier Despaux. DDR SDRAM Controller Using Virtex-4 FPGA Devices. XILINX. 2006(3)
[28] Lakshmi Gopalakrishnan. DDR2 Controller Using Virtex-4 Devices. XILINX. 2006(2)
[29] TMS320C6000 EMIF to External Asynchronous SRAM Interface. Texas Instruments Application Report. SPRA542A -August 2001
[30] SYNCHRONOUS DRAM Data Sheet. Micron Technology. Inc. 2002
[31] Robert M. Losee. A Gray Code Based Ordering for Documents on Shelves: Classification for Browsing and Retrieval. Journal of the American Society for Information Science.1998
[32] Hyuagtak Kim,Sangho Kim,Sungsam Lee,Sungho Jang,Ji-hoonKim.70nm DRAM Technolog for DDR-3Application .2005.IEEE
[33] Smith D J. HDL Chip Design-A practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog. Doone Publication.1996
[34] Robert M. Losee. A Gray Code Based Ordering for Documents on Shelves: Classification for Browsing and Retrieval. Journal of the American Society for Information Science. 1998
[35] David Dempster,Michael Stuart .VERIFICATION METHODOLOGY MANUAL Techniques for Verifying HDL Designs.Published by Teamwork International,2002
[36] AndrewPiziali.FUNCTIONALVERIFICATION COVERAGE MEASUREMENT AND ANALYSIS.KLUWER ACADEMIC PUBLISHERS.2004
[37] Lionel Bening , Harry Foster.Principles of Verifiable RTL Design Second Edition.KLUWER ACADEMIC PUBLISHERS.2001
[38] TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor. Texas Instruments Incorporated. 2002
[39] TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port ReferenceGuide. Texas Instruments Incorporated. 2005
[40] 汪东、马剑武、陈书明,基于 Gray 码的异步 FIFO 接口技术及其应用,计算机工程与科学,第 27 卷,第 1 期
[41] 陈宝民、汪东、马剑武、陈书明,一种高性能 SDRAM 控制器的设计及模拟,第八届计算机工程与工艺学术年会,2003.8
[42] 汪东、陈宝民、陈书明,一种可编程嵌入式异步 SRAM 存储控制器的设计与应用,微电子学,2005.5
[43] 李振涛、陈书明、等,“银河飞腾”高性能数字信号处理器研究进展,计算机研究与发展,2004.12
[44] 汪东、马剑武、陈书明、郭阳,高性能 DSP 中外部存储器接口的关键设计技术,中国计算机大会,2005
[45] 杨文华、罗晓沛,专用集成电路的设计验证方法及一种实际的通用微处理器设计的多级验证体系,计算机研究与发展,1999 Vol .6,NO. 6,P.764-768
[46] 邓丽,高带宽低延时的 DDR2 内存控制器的研究与实现,国防科技大学工学硕士论文