专用处理器及片上通信架构设计研究
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摘要
以视频信息为主的多媒体技术是21世纪最具时代特征和最富有活力的研究与应用领域,同时也是高性能片上系统(System on a Chip,SoC)发挥核心作用的领域。专用处理器及专用SoC可以在通用处理器的可编程、灵活性与专用集成电路(Application-Specific Integrated Circuit,ASIC)的高性能、低功耗之间取得设计折衷,已成为目前的研究热点。本文以最新视频编解码标准H.264/AVC为目标应用,就高性能专用SoC设计中的两个关键技术:专用指令集处理器(Application-Specific InstructionSet Processor,ASIP)设计与专用片上通信架构设计展开论述。
处理器是SoC的核心,承担着系统大部分的运算与控制任务。本文介绍了一款自主研发的面向视频压缩应用的ASIP指令体系及硬件实现。针对视频应用中数据组织操作开销大、内存读写频繁且地址不连续等特点,该指令集采用显式数据组织的指令格式,将数据组织操作内嵌到指令编码中,同时设计了行列交织的内存读写模式。硬件架构为SIMD(Single Instruction Multiple Data)与VLIW(Very Long Instruction Word)的混合结构,采用了RISC(Reduced Instrction Set Computer)类型的流水线结构,其中分布式运算单元支持可变字长的并行计算,而取指单元可完成变长编码指令的取指及下一PC(Program Counter)计算等功能,并设计了指令缓冲区以减少存储器访问。
专用指令的设计空间庞大,手工设计效率不高。本文在专用指令自动提取方面进行了探索,提出了静态数据流图搜索与动态结果筛选相结合的方法,并作为一种重要的补充应用到前述的ASIP指令集设计中。在此基础上,以H.264/AVC的环路去块效应滤波算法为例,叙述了视频压缩算法核心在ASIP上的优化过程。
片上集成部件的增多导致部件之间的数据通信逐渐成为制约系统性能的瓶颈。以目标应用的具体数据通信信息来指导通信架构的设计,可缩短通信消耗时间,提高系统实时性能。为此需要在设计早期对于目标应用中的数据通信部分进行精确的高层建模与仿真。本文在事务级模型(Transaction Level Model,TLM)的基础上提出了一种新的抽象模型CEAM(communication Event Accurate Model)用于系统的通信建模,完成了H.264/AVC的通信建模与仿真。并以此为基础,设计了一种针对应用优化的总线调度策略。实验结果表明,该策略可极大提高总线的利用效率,缩短通信任务完成时间。
High-performance SoC (System on a Chip) have been playing an important role in multimedia applications especially the video compression which is everywhere in human beings' daily life. Application-specific SoCs (ASSoC) can achieve a good tradeoff between the flexibility of general-purpose computing platform and the performance and the efficiency of ASICs (Application-Specific Integrated Circuits). It is now the hotspot of research both in academy and industry. This thesis mainly focuses on design of Application-specific Instruction Set Processors (ASIP) and on-chip communication architectures, which both are critical technique in ASSoCs.
As the core component of AS-SoC, ASIPs provide high computation performance while maintaining the flexibility as a programmable device. A video-oriented ASIP design is introduced in this dissertation. It utilizes the novel hybrid SIMD (Single Instruction Multiple Data) and VLIW (Very Long Instruction Word) architecture with the EDO (Explicit Data Organization) enhancement. Data permutation and re-organization functions are explicitly designated in the instruction encoding instead of extra permutation instructions which can significantly reduce the code size. Design of split ALU (Arighmatic Logic Unit) and the IFU (Instruction Fetch Unit) which supports variable-length instruction encoding are introduced. An instruction buffer is embedded in IFU that can significantly reduce the main instruction memory access.
An application-specific instruction synthesis approach is also proposed in this dissertation. The application is first converted to directed data flow graph and a search algorithm is then applied on it to extract optimized instructions. This approach has been applied in the design of the mentioned ASIP. The instruction and data path optimization targeted at the in-loop filter of H.264/AVC is elaborated with the modification of the reference code for the improvement of parallelism.
As more and more components are integrated into single chip, the data communication between components is now in the critical path of AS-SoC design. To model the communication of the target application accurately, a new abstract level called CEAM (Communication Event Accurate Model) is proposed and the data communication of the H.264/AVC has been modeled and simulated in CEAM. The profiling data is gathered during the simulation and an application-specific bus scheduling scheme is designed based on these data. The results of experiments show that the proposed scheduling scheme has a significant performance improvement against the general-purpose schemes such as RR (Round-Robin) an FP (Fixed Priority).
处理器是SoC的核心,承担着系统大部分的运算与控制任务。本文介绍了一款自主研发的面向视频压缩应用的ASIP指令体系及硬件实现。针对视频应用中数据组织操作开销大、内存读写频繁且地址不连续等特点,该指令集采用显式数据组织的指令格式,将数据组织操作内嵌到指令编码中,同时设计了行列交织的内存读写模式。硬件架构为SIMD(Single Instruction Multiple Data)与VLIW(Very Long Instruction Word)的混合结构,采用了RISC(Reduced Instrction Set Computer)类型的流水线结构,其中分布式运算单元支持可变字长的并行计算,而取指单元可完成变长编码指令的取指及下一PC(Program Counter)计算等功能,并设计了指令缓冲区以减少存储器访问。
专用指令的设计空间庞大,手工设计效率不高。本文在专用指令自动提取方面进行了探索,提出了静态数据流图搜索与动态结果筛选相结合的方法,并作为一种重要的补充应用到前述的ASIP指令集设计中。在此基础上,以H.264/AVC的环路去块效应滤波算法为例,叙述了视频压缩算法核心在ASIP上的优化过程。
片上集成部件的增多导致部件之间的数据通信逐渐成为制约系统性能的瓶颈。以目标应用的具体数据通信信息来指导通信架构的设计,可缩短通信消耗时间,提高系统实时性能。为此需要在设计早期对于目标应用中的数据通信部分进行精确的高层建模与仿真。本文在事务级模型(Transaction Level Model,TLM)的基础上提出了一种新的抽象模型CEAM(communication Event Accurate Model)用于系统的通信建模,完成了H.264/AVC的通信建模与仿真。并以此为基础,设计了一种针对应用优化的总线调度策略。实验结果表明,该策略可极大提高总线的利用效率,缩短通信任务完成时间。
High-performance SoC (System on a Chip) have been playing an important role in multimedia applications especially the video compression which is everywhere in human beings' daily life. Application-specific SoCs (ASSoC) can achieve a good tradeoff between the flexibility of general-purpose computing platform and the performance and the efficiency of ASICs (Application-Specific Integrated Circuits). It is now the hotspot of research both in academy and industry. This thesis mainly focuses on design of Application-specific Instruction Set Processors (ASIP) and on-chip communication architectures, which both are critical technique in ASSoCs.
As the core component of AS-SoC, ASIPs provide high computation performance while maintaining the flexibility as a programmable device. A video-oriented ASIP design is introduced in this dissertation. It utilizes the novel hybrid SIMD (Single Instruction Multiple Data) and VLIW (Very Long Instruction Word) architecture with the EDO (Explicit Data Organization) enhancement. Data permutation and re-organization functions are explicitly designated in the instruction encoding instead of extra permutation instructions which can significantly reduce the code size. Design of split ALU (Arighmatic Logic Unit) and the IFU (Instruction Fetch Unit) which supports variable-length instruction encoding are introduced. An instruction buffer is embedded in IFU that can significantly reduce the main instruction memory access.
An application-specific instruction synthesis approach is also proposed in this dissertation. The application is first converted to directed data flow graph and a search algorithm is then applied on it to extract optimized instructions. This approach has been applied in the design of the mentioned ASIP. The instruction and data path optimization targeted at the in-loop filter of H.264/AVC is elaborated with the modification of the reference code for the improvement of parallelism.
As more and more components are integrated into single chip, the data communication between components is now in the critical path of AS-SoC design. To model the communication of the target application accurately, a new abstract level called CEAM (Communication Event Accurate Model) is proposed and the data communication of the H.264/AVC has been modeled and simulated in CEAM. The profiling data is gathered during the simulation and an application-specific bus scheduling scheme is designed based on these data. The results of experiments show that the proposed scheduling scheme has a significant performance improvement against the general-purpose schemes such as RR (Round-Robin) an FP (Fixed Priority).
引文
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