现代机载雷达I/O接口模块的研究与实现
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摘要
本文描述了在以综合化、实时化和标准化为目标的前提下，一种属于嵌入式系统的机
载雷达I/O接口模块的设计和实现的方法。本接口模快上具有2个RS-232接口、4个RS-422
接口、1个RS-485接口、8路A/D转换接口、8路离散量接口及VME总线接口，同时带有
512K容量的FLASH ROM、256K容量的SRAM和可作为数据共享与信息传输的16K容量
的DPRAM存储器，处理器的工作主频在20MHz以上。依据I/O模块的功能要求和结构体系，
采用功能模块化的方法，运用标准化和优化的手段，尽量应用大规模/超大规模及复杂可编
程逻辑器件，建立了一个的可靠的设计方案。同时深入讨论和分析了异步通信接口码间干扰
理论，并论证了造成ADC系统和VME总线系统功能失效的原因，并给出了其相应的解决
措施，最后，讨论了用CPLD器件实现了一个VME总线接口控制器的方法和过程。
In this paper, we introduce a solution for I/O module in avation radar system bassed on the
goal of integration real-time and standard. The I/O module is also an embedded system. On this
module, there are 2 interefaces of RS-232 ~ 4 interefaces of RS-422 I intereface of RS-485.. 8
channels of A/D comvertion .. 8 kinds of signal interefaces and VMEbus intereface.
By the way ,there are also huge memory of 512K FLASHROM~ 256K SRAM and 16K
DRAM which is used to transfer message and be as an sharing data area. The CPU is at the rate of
20MHz. To realize the functions of the I/O module, we designed a scheme by using LSTI VLSI
IC and standard . optimalization and founction method.
At the same time, this paper talks about the theory of UART lSl(lntemal Signal Interfere) and
researchs the failure reason of the ADC system and VME bus, also it has realized a solution for
overcoming.and improvement. At last, we discuss and research the method of designing a
VMEbus control system on CPLD (coplicated programmable logical devices).
载雷达I/O接口模块的设计和实现的方法。本接口模快上具有2个RS-232接口、4个RS-422
接口、1个RS-485接口、8路A/D转换接口、8路离散量接口及VME总线接口，同时带有
512K容量的FLASH ROM、256K容量的SRAM和可作为数据共享与信息传输的16K容量
的DPRAM存储器，处理器的工作主频在20MHz以上。依据I/O模块的功能要求和结构体系，
采用功能模块化的方法，运用标准化和优化的手段，尽量应用大规模/超大规模及复杂可编
程逻辑器件，建立了一个的可靠的设计方案。同时深入讨论和分析了异步通信接口码间干扰
理论，并论证了造成ADC系统和VME总线系统功能失效的原因，并给出了其相应的解决
措施，最后，讨论了用CPLD器件实现了一个VME总线接口控制器的方法和过程。
In this paper, we introduce a solution for I/O module in avation radar system bassed on the
goal of integration real-time and standard. The I/O module is also an embedded system. On this
module, there are 2 interefaces of RS-232 ~ 4 interefaces of RS-422 I intereface of RS-485.. 8
channels of A/D comvertion .. 8 kinds of signal interefaces and VMEbus intereface.
By the way ,there are also huge memory of 512K FLASHROM~ 256K SRAM and 16K
DRAM which is used to transfer message and be as an sharing data area. The CPU is at the rate of
20MHz. To realize the functions of the I/O module, we designed a scheme by using LSTI VLSI
IC and standard . optimalization and founction method.
At the same time, this paper talks about the theory of UART lSl(lntemal Signal Interfere) and
researchs the failure reason of the ADC system and VME bus, also it has realized a solution for
overcoming.and improvement. At last, we discuss and research the method of designing a
VMEbus control system on CPLD (coplicated programmable logical devices).
引文
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6． N.S.Manju,Nath. The application of DRAM. IDT Company. 1998．
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9． Xilinx product overview.Volume 1,1996．
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11． Walters.G. Processor design and implementation for embedded system. IEEE 17th digital avinonics,1997．
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14． IEEE1104． 1 Standard .IEEE,1993．
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20． Mel ,Friden.Hardware help. EDN, Sept16,1999, pg22．
21． Levy,Markus.Unveriling. the hidden secrets of VME-bus.EDN, Mar27,1997, pg47．
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24． 顾新．VHDL硬件描述语言．西安电子科技大学出版社，1997．
25． 史新福．32位微型计算机原理接口技术及其应用．西北工业大学出版社，2000．
26． 付平．美国国家标准--VME总线．哈尔滨工业大学出版社，1992．
27． Douglas L．Perry,《VHDL电子设计硬件描述语言》，学苑出版社．，1998．
28． 毛法晓主编．数字逻辑．华中理工大学出版社，1998．
29． 严胜刚等．高速信号处理系统的体系结构研究。西北工业大学学报，14(4) ，1996．
30． 周良柱．VLSI与数字信号处理系统设计．长沙，国防科技大学出版社，1990．
31． 严胜刚等．多端口RAM的应用研究．96’鱼雷自导与引信技术研讨会论文集，1996．
32． 宋万杰等．CPLD技术及其应用．西安电子科技大学出版社，2000．
33． 白中英．计算机组成原理．科学出版社，1994．
34． 李参．ADC系统的缓冲器．电子工程专集，P34-35，2000．
35． 刘伟．数字总线中的模拟问题．电子设计技术，1999．
1． The programmable logic.Xinlinx Inc.1998．
2． Mixed signal &analog products designer's guide &reference.Texas Instruments.1996．
3． High performance Logic Designer's Guide .Analog Device Inc. 1996．
4． The Development of Advanced Radar System. Avonics.1998．
5． Spehro,Pephany.The programmable solutions for embedded system.Xilinx Corp. 1999．
6． N.S.Manju,Nath. The application of DRAM. IDT Company. 1998．
7． Huntingdon,PA.Designing UART in PC. Computer science technical.Jan 10, 1999,pg23 .
8． V.K.Govindan,A..P.Character recognition. 1990．
9． Xilinx product overview.Volume 1,1996．
10． IEEE 1076-1987 and IEEE 1076-1993 Standard. IEEE, 1996．
11． Walters.G. Processor design and implementation for embedded system. IEEE 17th digital avinonics,1997．
12． Intel 80186EB User Manual. Intel Company, 1997．
13． 80186EB Integrated System. Intel Company,1998．
14． IEEE1104． 1 Standard .IEEE,1993．
15． Designer's Guide & Data Book. Analog Device Inc,1999．
16． MAXIM integrated products.MAXIM Inc,2000．
17． Application notes and products information.Xilinx Inc,1999．
18． Bill Schweber.Steps of designing embedded system. 1998．
19． Dipert,Brain. The high-end PC looks for a home.EDN, Nov 24,1999, pg145．
20． Mel ,Friden.Hardware help. EDN, Sept16,1999, pg22．
21． Levy,Markus.Unveriling. the hidden secrets of VME-bus.EDN, Mar27,1997, pg47．
22． Wright,Maury.Technology initiatives stimulate. EDN,Jan 12,2000, pg68．
23． Barry Flannaghan.Designing with high speed ADC. Analog Devices Inc,2000．
24． 顾新．VHDL硬件描述语言．西安电子科技大学出版社，1997．
25． 史新福．32位微型计算机原理接口技术及其应用．西北工业大学出版社，2000．
26． 付平．美国国家标准--VME总线．哈尔滨工业大学出版社，1992．
27． Douglas L．Perry,《VHDL电子设计硬件描述语言》，学苑出版社．，1998．
28． 毛法晓主编．数字逻辑．华中理工大学出版社，1998．
29． 严胜刚等．高速信号处理系统的体系结构研究。西北工业大学学报，14(4) ，1996．
30． 周良柱．VLSI与数字信号处理系统设计．长沙，国防科技大学出版社，1990．
31． 严胜刚等．多端口RAM的应用研究．96’鱼雷自导与引信技术研讨会论文集，1996．
32． 宋万杰等．CPLD技术及其应用．西安电子科技大学出版社，2000．
33． 白中英．计算机组成原理．科学出版社，1994．
34． 李参．ADC系统的缓冲器．电子工程专集，P34-35，2000．
35． 刘伟．数字总线中的模拟问题．电子设计技术，1999．