基于GALS NoC的异步片上通信链路技术研究
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摘要
随着集成电路工艺的发展，单个芯片上集成了越来越多的复杂的功能电路。采用同步电路设计的多核SoC和片上网络(network on chip, NoC)面临由全局时钟引起的时钟偏斜、时钟抖动、时钟功耗以及设计复杂度等一系列问题，因而全局异步、局部同步(GALS)的设计思想成为目前高性能片上系统,尤其是片上网络的有效设计方法。GALS NoC可集成同步IP核和异步IP核，异步IP核内各模块的数据处理与传输采用异步流水线设计，而对于同步IP核，则通过异步封装将其产生的同步数据转换为异步数据。此时，芯片上各IP核之间通过异步传输链路进行不同速率下的数据传输。因此，基于不同的异步传输协议设计的异步流水线及片上通信链路将会对GALS NoC的IP核设计和性能产生不同的影响。本文对异步IP核内具有数据处理功能的通信链路即异步流水线，以及各IP核间具有数据传输功能的通信链路进行了研究，主要成果如下：
1.针对四相双轨流水线存在的吞吐量及功耗等性能问题提出了一种并行完备流水线。该流水线以串并结合的工作方式提升吞吐量，同时采用独特的阈值门降低流水线空周期时的静态功耗，可用于异步IP核内具有数据处理功能的通信链路设计。
2.针对异步传输链路的通信冲突问题，本文提出了一种延时无关的异步动态优先级仲裁器。通过比较请求数据包的优先级，可以实现在一个仲裁周期内按优先级高低输出，若优先级相同，则顺序输出，可有效解决片上传输链路中数据包冲突。
3.对异步传输链路的协议转换进行了详细的研究。提出了单通道协议与四相双轨协议、四相捆绑协议以及两相LEDR协议之间的转换电路，以实现两类协议间灵活、方便的使用。
4.针对长距离片上传输链路，提出了一种自应答高速异步双轨推通道。该通道采用独立传输链路，避免了复杂的时序设计，并降低传输链路间的干扰。同时，以提出的协议转换电路和通道单元为基础，设计了两相自应答异步片上传输链路，且只要改变协议转换电路，提出的自应答片上传输链路即可与现有的异步协议接口。与两相LEDR协议传输链路比较结果显示，本论文提出的两相自应答通信链路在吞吐量、功耗、面积各方面具有更好的性能。
5.以优化芯片的面积、功耗及互连资源为目标，提出了可与现有协议接口的自应答串行化传输链路。与自应答并行传输链路相比，具有更小的面积和功耗、更少的互连线数，节省了布线资源，降低了线间串扰，提高了通信可靠性，适合于低功耗的片上通信设计。
With the development of integrated circuit process, more and more complexfunctions can be integrated into one chip. The synchronous MPSoC and NoC face seriesof issues such as clock skew, clock jitter and power consumption caused by the globalclock signal. The global asynchronous and locally synchronous (GALS) design methodhad been proposed and become effective way to design high-performance MPSoC,especially for NoC. The GALS integrate asynchronous IP cores and synchronous IPcores. The modules in asynchronous IP cores use asynchronous pipeline as dataprocessing and transmission link. The synchronous IP cores translate the synchronousdata into asynchronous data via wapper. The IP cores use asynchronous on-chipcommunication link to communicate and exchange data. Thus, the asynchronouspipeline and asynchronous on-chip communication link based on different protocols andways will have an effect on the performance of the GALS NoC. This thesis mainlystudies on-chip communication link with data processing in asynchronous IPcores, anddata transmission on-chip communication link between IP cores. The contributions ofthis dissertation are as follows:
1. The pipeline based on parallel completion is proposed to resolve the throughputand power of four-phase dual-rail pipeline. The series-parallel ways improve thethroughput of the pipeline. Moreover, the static power of the pipeline in NULL cycledeclines as well because of the new threshold gates. The proposed pipeline can be usedto design communication link with data processing function in asynchronous IP.
2. This thesis proposes a delay-independent asynchronous dynamic priority arbiterfor communication conflict. In an arbitration period, by comparing the priority of thedata packets with request signals, the arbiter will output the data packets in the sequenceof descending priority. The packets with equal priority are outputted serially. The arbitercan be used to avoid communication conflict in on-chip communication links.
3. The paper firstly studies protocol interface in communication link, innovativelypropose protocol converters between four-phase dual-rail protocol and dual-railsingle-track protocol, four-phase bundled protocol and dual-rail single-track protocol, aswell as two-phase LEDR protocol and dual-rail single-track protocol, in order toimprove flexible usage of these two types protocol.
4. This paper proposes a novel elf-acknowledgement high-speed asynchronousdual-rail push channel for long-range data transmission on-chip communication link. The asynchronous channel transmits dual-rail data through two independenttransmission link in order to avoid complex timing design, reduce transmission linkinterference. Meanwhile, based on proposed protocol converters and asynchronousself-acknowledgement channel unit, the two-phase self-acknowledgement asynchronouson-chip communication link has been designed. The two-phase self-acknowledgementasynchronous communication link can communicate with traditional asynchronous linkby changing protocol interface. Compared with two-phase LEDR communication link,the two-phase self-acknowledgement asynchronous communication link is superior interms of throught, power dissipation and area.
5. The self-acknowledgement asynchronous serial communication link, which cancommunicate with current asynchronous protocol, has been proposed to optimize area,power dissipation and interconnect resource. Simulation results have shown that theserial communication link has lower power consumption, a smaller die area and fewerinterconnects than the self-acknowledgement bit-parallel link. The serialcommunication link can save interconnect resource, reduce crosstalk and improvecommunication reliability, which can be used in low-power on-chip communication.
1.针对四相双轨流水线存在的吞吐量及功耗等性能问题提出了一种并行完备流水线。该流水线以串并结合的工作方式提升吞吐量，同时采用独特的阈值门降低流水线空周期时的静态功耗，可用于异步IP核内具有数据处理功能的通信链路设计。
2.针对异步传输链路的通信冲突问题，本文提出了一种延时无关的异步动态优先级仲裁器。通过比较请求数据包的优先级，可以实现在一个仲裁周期内按优先级高低输出，若优先级相同，则顺序输出，可有效解决片上传输链路中数据包冲突。
3.对异步传输链路的协议转换进行了详细的研究。提出了单通道协议与四相双轨协议、四相捆绑协议以及两相LEDR协议之间的转换电路，以实现两类协议间灵活、方便的使用。
4.针对长距离片上传输链路，提出了一种自应答高速异步双轨推通道。该通道采用独立传输链路，避免了复杂的时序设计，并降低传输链路间的干扰。同时，以提出的协议转换电路和通道单元为基础，设计了两相自应答异步片上传输链路，且只要改变协议转换电路，提出的自应答片上传输链路即可与现有的异步协议接口。与两相LEDR协议传输链路比较结果显示，本论文提出的两相自应答通信链路在吞吐量、功耗、面积各方面具有更好的性能。
5.以优化芯片的面积、功耗及互连资源为目标，提出了可与现有协议接口的自应答串行化传输链路。与自应答并行传输链路相比，具有更小的面积和功耗、更少的互连线数，节省了布线资源，降低了线间串扰，提高了通信可靠性，适合于低功耗的片上通信设计。
With the development of integrated circuit process, more and more complexfunctions can be integrated into one chip. The synchronous MPSoC and NoC face seriesof issues such as clock skew, clock jitter and power consumption caused by the globalclock signal. The global asynchronous and locally synchronous (GALS) design methodhad been proposed and become effective way to design high-performance MPSoC,especially for NoC. The GALS integrate asynchronous IP cores and synchronous IPcores. The modules in asynchronous IP cores use asynchronous pipeline as dataprocessing and transmission link. The synchronous IP cores translate the synchronousdata into asynchronous data via wapper. The IP cores use asynchronous on-chipcommunication link to communicate and exchange data. Thus, the asynchronouspipeline and asynchronous on-chip communication link based on different protocols andways will have an effect on the performance of the GALS NoC. This thesis mainlystudies on-chip communication link with data processing in asynchronous IPcores, anddata transmission on-chip communication link between IP cores. The contributions ofthis dissertation are as follows:
1. The pipeline based on parallel completion is proposed to resolve the throughputand power of four-phase dual-rail pipeline. The series-parallel ways improve thethroughput of the pipeline. Moreover, the static power of the pipeline in NULL cycledeclines as well because of the new threshold gates. The proposed pipeline can be usedto design communication link with data processing function in asynchronous IP.
2. This thesis proposes a delay-independent asynchronous dynamic priority arbiterfor communication conflict. In an arbitration period, by comparing the priority of thedata packets with request signals, the arbiter will output the data packets in the sequenceof descending priority. The packets with equal priority are outputted serially. The arbitercan be used to avoid communication conflict in on-chip communication links.
3. The paper firstly studies protocol interface in communication link, innovativelypropose protocol converters between four-phase dual-rail protocol and dual-railsingle-track protocol, four-phase bundled protocol and dual-rail single-track protocol, aswell as two-phase LEDR protocol and dual-rail single-track protocol, in order toimprove flexible usage of these two types protocol.
4. This paper proposes a novel elf-acknowledgement high-speed asynchronousdual-rail push channel for long-range data transmission on-chip communication link. The asynchronous channel transmits dual-rail data through two independenttransmission link in order to avoid complex timing design, reduce transmission linkinterference. Meanwhile, based on proposed protocol converters and asynchronousself-acknowledgement channel unit, the two-phase self-acknowledgement asynchronouson-chip communication link has been designed. The two-phase self-acknowledgementasynchronous communication link can communicate with traditional asynchronous linkby changing protocol interface. Compared with two-phase LEDR communication link,the two-phase self-acknowledgement asynchronous communication link is superior interms of throught, power dissipation and area.
5. The self-acknowledgement asynchronous serial communication link, which cancommunicate with current asynchronous protocol, has been proposed to optimize area,power dissipation and interconnect resource. Simulation results have shown that theserial communication link has lower power consumption, a smaller die area and fewerinterconnects than the self-acknowledgement bit-parallel link. The serialcommunication link can save interconnect resource, reduce crosstalk and improvecommunication reliability, which can be used in low-power on-chip communication.
引文
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