基于MCML/TG结构的高速低功耗三值电路设计
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摘要
在VLSI技术领域的关键问题主要集中在芯片面积、开关速度以及功耗方面。传统CMOS电路的功耗主要来源是开关电流产生的动态功耗,因此其功耗在频率较低时会显现优势,然而随着操作频率的不断增加至大于1GHZ以后,传统CMOS电路的功耗急剧上升,其功耗方面的优势愈发减弱。而且传统的CMOS电路有相当大的内部噪声,这也阻碍了SOC中模拟和数字电路的集成。然而,MOS电流模逻辑(MCML)可以同时满足功耗与频率无关,且提供一个模拟友好环境的需求。
目前国内外对MCML电路设计的研究主要集中在二值逻辑的电路特性分析、电路方法设计以及延迟功耗改善等方面,本文从三值逻辑出发进行研究。在深入分析MCML和TG的电路特点后,首先提出将两种结构结合起来进行数字电路设计的思路。该混合结构MCML/TG主要由MCML和TG共同构成,其中MCML结构产生控制信号,TG进行信号的传输。随后,基于该混合结构,论文设计了三值Post代数系统及模代数系统中的各基本电路,并应用所设计的T算子进行全加器的设计。再后,基于该混合结构进行三值D-latch电路的设计；应用所设计的D-latch结构设计主从触发器；进行基于三值时钟的双边沿触发器的设计；分析讨论JKL三值触发器的设计。最后,对所设计的电路进行仿真验证,并利用多值逻辑电路设计的思想来进行二值MCML/TG电路的开关级设计。
通过Hspice软件,采用TSMC 0.18um CMOS工艺,供电电压1.8v,对所设计的电路进行仿真,仿真结果分析表明：电路逻辑功能正确；功耗保持MCML结构的优势,基本与频率无关；输入输出高低电平一致,具有较好的电压兼容性；与传统的CMOS电路相比,取得了较大的延迟优化,且保持了简单的电路结构。
Recently, VLSI technology has considered chip area, operation speed and power consumption. The traditional CMOS logic circuits dissipate the power only when the load is charging and discharging. Therefore, the power consumption of the CMOS logic circuits is generally small at low frequency. However, by the increasing frequency reaching to 1 GHz, the power consumption of traditional CMOS circuits increase rapidly and the advantage on power consumption will be reduced. In addition, the considerable internal noise of the traditional CMOS circuits hinders the SOC integration of sensitive analog and digital circuits. However, MCML can simultaneously satisfy the requirements of power consumption and speed, and provide a friendly mixed environment.
Currently at home and abroad, the researches of MCML circuits mainly focuses on two-valued circuits, such as the analysis of the characteristics of the circuits, circuits designing and improvement of time delay and power consumption, etc. The paper is mainly concentrated on the ternary MCML circuits. Firstly, by analyzing the characteristic of MCML and TG circuits, this paper proposes an idea of designing circuits based on combining the two structures. This mixed structure MCML/TG is mainly composed of MCML and TG, the control signal is produced by MCML and TG is responsible for transmission. Secondly, circuits designing based on the MCML/TG structure in the Post algebraic system and Mode algebraic system is proposed; then using the designed 3-T operator, the paper proposes one kind of full adder. Thirdly, designing of D-latch circuit based on the structure of MCML/TG is proposed and master-slave flip-flop is realized based on the latch; then the paper proposes the double-edge-triggered flip-flop based on ternary clock and discusses the designing of ternary JKL flip-flop analytically. Finally, this paper simulates the designed circuits by Hspice, and using the idea of multi-valued logic designing to conduct the switch-level designing of two-valued MCML/TG circuits.
The proposed logic is validated by simulations of Hspice based on the TSMC 0.18 um MOS technology with 1.8v power supply voltage. The simulation results show the power dissipation of the MCML/TG circuits is almost independent of clock frequency, the input and output voltage is consistent, and the propagation delay is improved greatly compared to the conventional CMOS circuits. Moreover, the structure is symmetrical and simple.
目前国内外对MCML电路设计的研究主要集中在二值逻辑的电路特性分析、电路方法设计以及延迟功耗改善等方面,本文从三值逻辑出发进行研究。在深入分析MCML和TG的电路特点后,首先提出将两种结构结合起来进行数字电路设计的思路。该混合结构MCML/TG主要由MCML和TG共同构成,其中MCML结构产生控制信号,TG进行信号的传输。随后,基于该混合结构,论文设计了三值Post代数系统及模代数系统中的各基本电路,并应用所设计的T算子进行全加器的设计。再后,基于该混合结构进行三值D-latch电路的设计；应用所设计的D-latch结构设计主从触发器；进行基于三值时钟的双边沿触发器的设计；分析讨论JKL三值触发器的设计。最后,对所设计的电路进行仿真验证,并利用多值逻辑电路设计的思想来进行二值MCML/TG电路的开关级设计。
通过Hspice软件,采用TSMC 0.18um CMOS工艺,供电电压1.8v,对所设计的电路进行仿真,仿真结果分析表明：电路逻辑功能正确；功耗保持MCML结构的优势,基本与频率无关；输入输出高低电平一致,具有较好的电压兼容性；与传统的CMOS电路相比,取得了较大的延迟优化,且保持了简单的电路结构。
Recently, VLSI technology has considered chip area, operation speed and power consumption. The traditional CMOS logic circuits dissipate the power only when the load is charging and discharging. Therefore, the power consumption of the CMOS logic circuits is generally small at low frequency. However, by the increasing frequency reaching to 1 GHz, the power consumption of traditional CMOS circuits increase rapidly and the advantage on power consumption will be reduced. In addition, the considerable internal noise of the traditional CMOS circuits hinders the SOC integration of sensitive analog and digital circuits. However, MCML can simultaneously satisfy the requirements of power consumption and speed, and provide a friendly mixed environment.
Currently at home and abroad, the researches of MCML circuits mainly focuses on two-valued circuits, such as the analysis of the characteristics of the circuits, circuits designing and improvement of time delay and power consumption, etc. The paper is mainly concentrated on the ternary MCML circuits. Firstly, by analyzing the characteristic of MCML and TG circuits, this paper proposes an idea of designing circuits based on combining the two structures. This mixed structure MCML/TG is mainly composed of MCML and TG, the control signal is produced by MCML and TG is responsible for transmission. Secondly, circuits designing based on the MCML/TG structure in the Post algebraic system and Mode algebraic system is proposed; then using the designed 3-T operator, the paper proposes one kind of full adder. Thirdly, designing of D-latch circuit based on the structure of MCML/TG is proposed and master-slave flip-flop is realized based on the latch; then the paper proposes the double-edge-triggered flip-flop based on ternary clock and discusses the designing of ternary JKL flip-flop analytically. Finally, this paper simulates the designed circuits by Hspice, and using the idea of multi-valued logic designing to conduct the switch-level designing of two-valued MCML/TG circuits.
The proposed logic is validated by simulations of Hspice based on the TSMC 0.18 um MOS technology with 1.8v power supply voltage. The simulation results show the power dissipation of the MCML/TG circuits is almost independent of clock frequency, the input and output voltage is consistent, and the propagation delay is improved greatly compared to the conventional CMOS circuits. Moreover, the structure is symmetrical and simple.
引文
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[8]刘毅,宫俊,杨银堂等.MCML结构高速低功耗加法器设计.微电子学与计算机,2004,21(11)：161-163.
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[38]蒋征科.低功耗MCML电路和电流型CMOS电路设计研究.浙江大学,2003.
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[43]Salama A, Al-Ali O. Clock-pulse control MOS current mode logic (CPC-MCML):A new low-power high-performance logic style. Journal of Engineering and Applied Science, April 2005, 52(2):343-353.
[44]Tajalli A, Vittoz E, Leblebici Y, et al. Ultra Low Power Sub-threshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept. Proc.33rd European Solid-State Circuits Conference,2007:304-307.
[45]Bui H T, Savaria Y.10 GHz PLL using active Shunt-Peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18μm CMOS. Proc. of the 4th IEEE International Workshop on SoC for Real-Time Applications,2004:115-118.
[46]Kwan W, Shams M. Multi-GHz energy-efficient asynchronous pipelined circuits in MOS current mode logic. Proc. of IEEE International Symposium on Circuits and Systems,2004, 2:645-648.
[47]Sharaf K M, Elmasry M L. An accurate analytical propagation delay model for high-speed CML bipolar circuits. IEEE JSSC,1994,29(1):31-45.
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[2]SUMATHI M, CHEN N. Performance and analysis of CML Logic gates and latches. Proceedings of the 2007 international symposium on microwave, antenna, propagation and EMC technologies for wireless communications, Hangzhou, China,2007:1428-1432.
[3]HASSAN H, ANIS M, ELMASRY M. MOS current mode circuits:analysis, design, and variability. IEEE Trans on VLSI,2005,13(8):885-898.
[4]陈春鸿.CMOS集成电路的功耗分析及低功耗设计技术.浙江工业大学学报,1998,26(3)：189-194.
[5]Yamashina M and Yamada H. An MOS current mode logic (MCML) circuit for low-power sub-GHz processors. IEICE Trans. Electron.,1992,75(10):1181-1187.
[6]Cannillo F, Toumazou C, Lande T S. Nanopower subthreshold MCML in submicrometer CMOS technology. IEEE Trans on Circuits and Systems I,2009,56(8):1598-1611.
[7]Delican Y, Morgul A. High Performance 16-Bit MCML Multiplier. European Conference on Circuit Theory and Design, Istanbul, Turkey,2009:157-160.
[8]刘毅,宫俊,杨银堂等.MCML结构高速低功耗加法器设计.微电子学与计算机,2004,21(11)：161-163.
[9]Kong B, Choi J, Lee S, Lee K. Charge recycling differential logic CRDL for low power application. IEEE JSSC,1996,31(9):1267-1276.
[10]Allstot D J, Chee S H, Kiaei S, and Shrivastawa M. Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs. IEEE Trans. Circuits Syst. Ⅰ,1993,40(9):553-563.
[11]CMOS的优点. http://bbs.ednchina.com/view_comments.jspa?entry_id=35005&from=RSS.
[12]Veendrick Harry J M. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE J. of Solid-State Circuits,1984,19(4):468-473.
[13]Kahumu M, Kinugawa M. Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI. IEEE Trans Electron Devices,1990,37(8):1902-1908.
[14]Chandrakasan A P, Sheng S, Brodersen R W. Low-Power CMOS digital design. IEEE J. of Solid-State Circuits,1992,27(4):473-484.
[15]Borah M, Owens R M, Irwin M J. Transistor sizing for low power CMOS circuits.IEEE Trans Computer-Aided Design of Integrated Circuits and System,1996,15(6):665-671.
[16]Monteiro J, Devadas S, Ghosh A. Retiming Sequential circuits for low power. In Proc IEEE International Conference on Computer-Aided Design,1993:398-402.
[17]Rang S M, Leblebici Y. CMOS digital integrated circuits:analysis and design.America: McGraw Hill Companys,2009:372-373.
[18]ITRS Roadmap [Online]. Available:http://public.itrs.net.
[19]Tsui C Y, Pedram M, Despain A M. Power efficient technology decomposition and mapping under an extended power consumption model. IEEE Trans Computer-Aided Design of Integrated Circuit and Systems,1994,13(9):1110-1122.
[20]Vaishnav H, Pedram M. PCUBE:A performance driven placement algorithm for low power designs. In Proc European Design Automation Conference,1993:72-77.
[21]Cong J, Koh C, Leung K. Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans VLSI Systems,1994,2(4):408-425.
[22]Cong J, Koh C. Minimum-cost bounded-skew clock routing. In Proc the International Symposium on Circuits and Systems,1995:215-218.
[23]甘学温,莫邦燹.低功耗CMOS逻辑电路设计综述.微电子学,2000,30(4)：264-267.
[24]Burr J, Shott J. A 200mV self-testing encoder/decoder using standford ultra-low power CMOS. IEEE ISSCC,1994:84-85.
[25]1997 Electronic Market Data Book. Washington D.C. Electronic Industries Association,1997.
[26]Yano K, Yamanaka T, Nishida T, et al. A 3.8ns CMOS 16×16b multiplier using complementary pass-transistor logic. IEEE J. of Solid State Circuits,1990,25(2):388-395.
[27]Shahidi G G. A room temperature 0.1 um CMOS on SOI. IEEE Symp VLSI Tech,1993: 27-28.
[28]Horiguchi M, Sakata T, Itoh K. Switched source impedance CMOS circuits for standby subthreshold current giga-scale LSI's. IEEE J. of Solid State Circuits,1993,28(11):1130-1135.
[29]Yang I Y, Vieri C, Chandrakasan A P, et al. Back-gated CMOS on SOI for dynamic threshold voltage control. IEEE Trans Elec Dev,1997,44(5):822.
[30]Mutch S, Douseki T, Matsuya Y, et al.1V Power supply high-speed digital circuit technology with multi-threshold-voltage CMOS. IEEE J. of Solid State Circuits,1995,30(8):847-853.
[31]Chandrakasan A P, Brodersen R W. Low power digital CMOS design. Boston:Kluwer Academic Publishers,1995.
[32]Yamashina M, Yamada H. MOS current mode logic MCML circuit for low-power GHz processors. NEC Research 6 Development,1995,36(1):54-63.
[33]Mizuno M, Yamashina M, Furuta K, et al. A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE Journal of Solid-State Circuits,1996,31(6):784-791.
[34]Alioto M, Palumbo G. Power-aware design techniques for nanometer MOS current-mode logic gates:A design framework. IEEE Circuits and Systems Magazine,2006,6(4):42-61.
[35]Hassan H, Anis M, Elmasry M. Low-power multi-threshold MCML:Analysis, design, and variability. Microelectronics Journal,2006,37(10):1097-1104.
[36]Cao J, Green M, Momtaz A, et al. OC-192 transmitter and receiver in standard 0.18μm CMOS. IEEE JSSC, Dec 2002,37(2):1768-1780.
[37]Tanabe A, Umetani M, Fujiwara I, et al.0.18-μm CMOS 10Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. IEEE JSSC, Jun 2001, 36(6):988-996.
[38]蒋征科.低功耗MCML电路和电流型CMOS电路设计研究.浙江大学,2003.
[39]Agarwal T, Sawhney A, Kureshi A, et al. Performance comparison of static CMOS and MCML gates in sub-threshold region of operation for 32nm CMOS Technology. Proc. of International Conference on Computer and Communication Engineering,2008:284-287.
[40]Kim J B. Low-Power MCML circuit with Sleep-Transistor. The 8th IEEE International Conference on ASIC, Changsha, China,2009:25-28.
[41]Anis M, Elmasry M. Self-timed MOS Current Mode Logic for Digital Applications. Proc. of IEEE International Symposium on Circuits and Systems, May 2002,5:113-116.
[42]Anis M, Elmasry M. Power reduction via an MTCMOS implementation of MOS current mode logic. Proc. of IEEE International ASIC/SOC Conference,2002:193-197.
[43]Salama A, Al-Ali O. Clock-pulse control MOS current mode logic (CPC-MCML):A new low-power high-performance logic style. Journal of Engineering and Applied Science, April 2005, 52(2):343-353.
[44]Tajalli A, Vittoz E, Leblebici Y, et al. Ultra Low Power Sub-threshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept. Proc.33rd European Solid-State Circuits Conference,2007:304-307.
[45]Bui H T, Savaria Y.10 GHz PLL using active Shunt-Peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18μm CMOS. Proc. of the 4th IEEE International Workshop on SoC for Real-Time Applications,2004:115-118.
[46]Kwan W, Shams M. Multi-GHz energy-efficient asynchronous pipelined circuits in MOS current mode logic. Proc. of IEEE International Symposium on Circuits and Systems,2004, 2:645-648.
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