高速串行RapidIO接口数据接收器设计
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摘要
RapidIO属于系统级的互连技术,主要面向高性能数字信号处理系统以及嵌入式系统的互连通信。它提供以交换互连而非总线为基础的传输数据的标准方法,采用高性能接口技术,可以在4对差分线上实现10Gbps的有效传输速率,而且具有比万兆以太网、PCI Express更高的传输效率。RapidIO在路由、交换、容错纠错、使用方便性上有较完善的考虑,可以实现基于硬件的高性能可靠数据传输。
本文首先研究了串行RapidIO物理层规范对接口设计的基本要求;然后基于高速信号传输理论的研究,分析了传输线的行为特性和影响信号完整性的各种非理想因素;最后设计了高速串行RapidIO传输系统数据接收器的电路和版图。它包括可编程均衡器、灵敏放大器采样电路、差分转单端电路和串行转并行模块。
均衡器是本文设计的核心,因为信号经过传输线之后,高频分量衰减比较严重,使得接收端收到的信号上升/下降时间变长,极易引起码间干扰,导致误码率升高。均衡器能够对接收到的信号进行高频分量补偿,增加信号中高频分量的成分,恢复信号的质量,所以它的性能关系到整个接收器是否能正确识别接收到的信号。数据采样在整体结构上采用了多重相位数据提取技术,用四个相位的时钟(从CDR恢复出来)来采样串行数据,这样就可以用低的时钟速率采样高速的串行数据流。其中的灵敏放大器采样电路也是经过仔细设计的,尤其是电路中晶体管的尺寸参数要不断优化和调整,版图上也要特别注意器件的匹配,减小工艺误差。差分转单端电路采用SR触发器结构,使用交叉耦合的与非门实现。串行转并行使用移位寄存器来实现,串行数据在位时钟的控制下,逐位移入串行连接的D触发器中进行保存,然后这些数据在五分频得到的字时钟控制下同步输出到并行的输出寄存器,完成串行到并行的转换。
As system-level interconnect, RapidIO is mainly designed for the communications of high-performance digital signal processing systems or embedded systems interconnect. It adopts the standard method of data transferring based on switching rather than bus interconnects, and can implement that the effective data transfer rate of 10Gbps, on four pairs of differential lines with high-performance interface. There is higher transmission efficiency than 10-Gigabit Ethernet and PCI Express. RapidIO is perfect in routing, switching, fault-tolerant and error correction. It can realize the reliable data transfer based on hardware.
This paper studied the basic requirements of interface design of Serial RapidIO Physical Layer specification; Then, analyzed the behavioral characteristics of transmission line and various non-ideal factors that impact the signal integrity, based on high-speed signal transmission theory; Finally, designed the circuits and layout of data receiver in the high-speed serial RapidIO transmit system. It included programmable equalizer, sense amplifier sample circuit, differential signals to single-ended circuit and serial to parallel module.
Equalizer is the core of this design. Because the high frequency components of signals is attenuated seriously, after passed the transmission line. This will make the rise and fall time of signals longer at receiver, resulting in inter-symbol interference and high bit error rate. Equalizer can compensate the high-frequency components of the signal received by receiver, through increasing the proportion of high-frequency components of the signal to restore the signal quality. So its performance decides whether the entire receiver is able to correctly identify the signal. In the entire structure, we choose multiphase data extraction technology to sample data. By using four-phase clock (from CDR) to sample the serial data, we can sample a high-speed serial data stream at a lower clock speed. The sense amplifier sample circuit is also designed carefully, especially the size of the transistor circuit need to be optimized and adjusted continuously. We should also pay more attention to match the device and reduce process errors in layout. The circuit of differential signals to single-ended is imple- -mented by SR flip-flop structure, which is composed of the cross-coupled NAND gate. Shift registers are used to realize the serial to parallel circuit. Serial data is shifted into the serial D flip-flops under the control of the bit clock, and then the data can be obtained synchronously in the parallel output registers, under the control of the word clock derived from 1/5 frequency divider. The conversion of serial to parallel is completed.
本文首先研究了串行RapidIO物理层规范对接口设计的基本要求;然后基于高速信号传输理论的研究,分析了传输线的行为特性和影响信号完整性的各种非理想因素;最后设计了高速串行RapidIO传输系统数据接收器的电路和版图。它包括可编程均衡器、灵敏放大器采样电路、差分转单端电路和串行转并行模块。
均衡器是本文设计的核心,因为信号经过传输线之后,高频分量衰减比较严重,使得接收端收到的信号上升/下降时间变长,极易引起码间干扰,导致误码率升高。均衡器能够对接收到的信号进行高频分量补偿,增加信号中高频分量的成分,恢复信号的质量,所以它的性能关系到整个接收器是否能正确识别接收到的信号。数据采样在整体结构上采用了多重相位数据提取技术,用四个相位的时钟(从CDR恢复出来)来采样串行数据,这样就可以用低的时钟速率采样高速的串行数据流。其中的灵敏放大器采样电路也是经过仔细设计的,尤其是电路中晶体管的尺寸参数要不断优化和调整,版图上也要特别注意器件的匹配,减小工艺误差。差分转单端电路采用SR触发器结构,使用交叉耦合的与非门实现。串行转并行使用移位寄存器来实现,串行数据在位时钟的控制下,逐位移入串行连接的D触发器中进行保存,然后这些数据在五分频得到的字时钟控制下同步输出到并行的输出寄存器,完成串行到并行的转换。
As system-level interconnect, RapidIO is mainly designed for the communications of high-performance digital signal processing systems or embedded systems interconnect. It adopts the standard method of data transferring based on switching rather than bus interconnects, and can implement that the effective data transfer rate of 10Gbps, on four pairs of differential lines with high-performance interface. There is higher transmission efficiency than 10-Gigabit Ethernet and PCI Express. RapidIO is perfect in routing, switching, fault-tolerant and error correction. It can realize the reliable data transfer based on hardware.
This paper studied the basic requirements of interface design of Serial RapidIO Physical Layer specification; Then, analyzed the behavioral characteristics of transmission line and various non-ideal factors that impact the signal integrity, based on high-speed signal transmission theory; Finally, designed the circuits and layout of data receiver in the high-speed serial RapidIO transmit system. It included programmable equalizer, sense amplifier sample circuit, differential signals to single-ended circuit and serial to parallel module.
Equalizer is the core of this design. Because the high frequency components of signals is attenuated seriously, after passed the transmission line. This will make the rise and fall time of signals longer at receiver, resulting in inter-symbol interference and high bit error rate. Equalizer can compensate the high-frequency components of the signal received by receiver, through increasing the proportion of high-frequency components of the signal to restore the signal quality. So its performance decides whether the entire receiver is able to correctly identify the signal. In the entire structure, we choose multiphase data extraction technology to sample data. By using four-phase clock (from CDR) to sample the serial data, we can sample a high-speed serial data stream at a lower clock speed. The sense amplifier sample circuit is also designed carefully, especially the size of the transistor circuit need to be optimized and adjusted continuously. We should also pay more attention to match the device and reduce process errors in layout. The circuit of differential signals to single-ended is imple- -mented by SR flip-flop structure, which is composed of the cross-coupled NAND gate. Shift registers are used to realize the serial to parallel circuit. Serial data is shifted into the serial D flip-flops under the control of the bit clock, and then the data can be obtained synchronously in the parallel output registers, under the control of the word clock derived from 1/5 frequency divider. The conversion of serial to parallel is completed.
引文
[1]马春江,牛文生,孙靖国.几种串行总线互连技术分析.航空计算技术, 2007, 09(5):127-130
[2] Sam Fuller, Greg Shippen. RapidIO互连解决高性能嵌入式系统的可靠性和互连性挑战. http://www.rapidio.org
[3] RapidIO嵌入式系统互连总线概述. http://www.rte-sky.com
[4] RapidIO Trade Association. RapidIOTM Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification, Rev. 2.0, 2007.8
[5] Serial RapidIO 2.1 IP Core. http://www.lattice.com
[6]冯华亮.串行RapidIO:高性能嵌入式互连技术.今日电子, 2009, 9(9): 78-80
[7] Sam Fuller等著,王勇等译. RapidIO嵌入式系统互连.北京:电子工业出版社, 2006.6
[8] RapidIO Trade Association. RapidIOTM Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification, Rev. 1.3, 2005.6
[9]张玉敏.高速接口的设计和实现.复旦大学硕士学位论文, 2004.11
[10]龚海峰.基于信号完整性分析的高速数字PCB设计方法.上海交通大学硕士学位论文, 2002.6
[11] Johnson, Howard, Graham, Martin. High-Speed Digital Design,A Handbook of Black Magic, USA, Wiley-Interscience, 2000.8
[12] Eric Bogatin著,李玉山,李丽平等译.信号完整性分析.北京:电子工业出版社, 2005.4
[13]黄林.CMOS高速串行数据接收器的研究和设计.复旦大学博士学位论文, 2005.4
[14] Jan M. Rabaey, Anantha Chandrakasan等著,周润德等译.数字集成电路——电路、系统与设计.北京:电子工业出版社, 2006.8
[15]理解和检定定时抖动. http://www.tektronix.com/jitter
[16] Abhijit Athavale, Carl Christensen. High-Speed Serial I/O Made Sample, A Designers’Guide, with FPGA Applications, Edition 1.0, 2005.8
[17] Star-Hspice Manual Release 2000.2, Avant Corporation, 2000.5
[18]陈学峰.四通道3.125-Gbps CMOS发接器的系统研究与集成.复旦大学硕士学位论文, 2003.06
[19] David R. Stauffer, Jeanne Trinko Mechler, Kent Dramstad. High Speed Serdes Devices and Applications. Springer Science+Business Media, LLC, 2008.4
[20] Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. http://www.xilinx.com
[21]雷建武.高速LVDS I/O接口电路的全定制设计与实现.国防科学技术大学硕士学位论文, 2006.3
[22]高长平.CML高速串行接口电路的设计与实现.国防科学技术大学硕士学位论文, 2007.11
[23] LVDS、ECL、CML逻辑电平电路的特点及应用. http://www.symcukf.com
[24] Guangyu Evelina Zhang, Michael M. Green. A 10Gb/s BiCMOS Adaptive Cable Equalizer. IEEE J. Solid -State Circuits, 2005,40(11):2132-2140
[25] Jian-Hao Lu. Chi-Lun Luo. and Shen-Iuan Liu. An Adaptive 3.125Gbps Coaxial Cable Equalizer. IEEE J. Solid -State Circuits, 2006,41(12):386-389
[26]谢詹奇,戴庆元.均衡器技术研究.微处理机, 2009,6(3):23-26
[27] Charles E. Berndt, Tad Kwansniewski. A Review of Common Receive-End Adaptive Equalization Schemes and Aglorithms for a High-Speed Serial Backplane. Proceeding of the 9th international Database Engineering&Application Symposium. 2005.10
[28] M. Q. LEE, P. J. Hurst, J. P. Keane. An Adaptive Analog Noise-Predictive Decision Feedback Equalizer. IEEE J. Solid -State Circuits, 2002,37(2):105-113
[29] G. Balamurugan, et al. Reciever Adaptation and System Characterization of An 8Gbps Source-Synchronous I/O Link Using On-die Circuits in 0.13μm CMOS. IEEE Symposium on VLSI, 2004(6):356-359
[30] B. Razavi. Prospects of CMOS Technology for High-Speed Optical Communication Circuits. IEEE J. Solid-State Circuits, 2002,9(37):1135-1145
[31] Riccardo Badalone. John D’Ambrosia. 10Gb/s Receive Equalization for High Loss Backplanes. DesignCon. 2005.9
[32] Patrik Larsson. High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler. IEEE J. Solid-State Circuits, 1996,31(5):744-748
[33]欧雨华,严利民.高速CMOS可编程分频器的研究与设计.微计算机信息,2006, 5(12): 57-63
[34]唐李红.5Gbps高速串行接口电路的研究与设计.国防科学技术大学硕士学位论文, 2009.3
[35]王建军.高速串行接口电路的研究与设计.国防科学技术大学硕士学位论文, 2006.10
[36] Christopher Saint, Judy Jaint著.周润德,金申美译.集成电路掩模设计—基础版图技术.北京:清华大学出版社, 2006.1
[37] Behzad Razavi著.陈贵灿等译.模拟CMOS集成电路设计.西安交通大学出版社, 2002.12
[38] Alan Hastings著.张为等译.模拟电路版图的艺术.北京:电子工业出版社,2007.4
[39] Steven H. Voldman. ESD Circuits and Devices. USA, John Wiley & Sons, Ltd, 2006.8
[40] L. Baker, R. Currence, S. Law, M. Lee, S. T. Lin, M. Teene. A Waffle Layout Technique Strengthens the ESD Hardness of the NMOS Output Transistor. Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, 1989; 175-181
[41] D. F. Beigel, E. L. Wolfe and W. A. Krieger. Integrated Circuit with Diode- -Connected Transistor for Reducing ESD Damage. U. S. Patent No. 5,637,901, 1997.06
[42] M. D. Ker, T. S. Wu, K. F. Wang. N-Sides Polygonal Cell Layout for Multiple Cell Transistor. U. S. Patent No. 5,852,315, 1998.12
[2] Sam Fuller, Greg Shippen. RapidIO互连解决高性能嵌入式系统的可靠性和互连性挑战. http://www.rapidio.org
[3] RapidIO嵌入式系统互连总线概述. http://www.rte-sky.com
[4] RapidIO Trade Association. RapidIOTM Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification, Rev. 2.0, 2007.8
[5] Serial RapidIO 2.1 IP Core. http://www.lattice.com
[6]冯华亮.串行RapidIO:高性能嵌入式互连技术.今日电子, 2009, 9(9): 78-80
[7] Sam Fuller等著,王勇等译. RapidIO嵌入式系统互连.北京:电子工业出版社, 2006.6
[8] RapidIO Trade Association. RapidIOTM Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification, Rev. 1.3, 2005.6
[9]张玉敏.高速接口的设计和实现.复旦大学硕士学位论文, 2004.11
[10]龚海峰.基于信号完整性分析的高速数字PCB设计方法.上海交通大学硕士学位论文, 2002.6
[11] Johnson, Howard, Graham, Martin. High-Speed Digital Design,A Handbook of Black Magic, USA, Wiley-Interscience, 2000.8
[12] Eric Bogatin著,李玉山,李丽平等译.信号完整性分析.北京:电子工业出版社, 2005.4
[13]黄林.CMOS高速串行数据接收器的研究和设计.复旦大学博士学位论文, 2005.4
[14] Jan M. Rabaey, Anantha Chandrakasan等著,周润德等译.数字集成电路——电路、系统与设计.北京:电子工业出版社, 2006.8
[15]理解和检定定时抖动. http://www.tektronix.com/jitter
[16] Abhijit Athavale, Carl Christensen. High-Speed Serial I/O Made Sample, A Designers’Guide, with FPGA Applications, Edition 1.0, 2005.8
[17] Star-Hspice Manual Release 2000.2, Avant Corporation, 2000.5
[18]陈学峰.四通道3.125-Gbps CMOS发接器的系统研究与集成.复旦大学硕士学位论文, 2003.06
[19] David R. Stauffer, Jeanne Trinko Mechler, Kent Dramstad. High Speed Serdes Devices and Applications. Springer Science+Business Media, LLC, 2008.4
[20] Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. http://www.xilinx.com
[21]雷建武.高速LVDS I/O接口电路的全定制设计与实现.国防科学技术大学硕士学位论文, 2006.3
[22]高长平.CML高速串行接口电路的设计与实现.国防科学技术大学硕士学位论文, 2007.11
[23] LVDS、ECL、CML逻辑电平电路的特点及应用. http://www.symcukf.com
[24] Guangyu Evelina Zhang, Michael M. Green. A 10Gb/s BiCMOS Adaptive Cable Equalizer. IEEE J. Solid -State Circuits, 2005,40(11):2132-2140
[25] Jian-Hao Lu. Chi-Lun Luo. and Shen-Iuan Liu. An Adaptive 3.125Gbps Coaxial Cable Equalizer. IEEE J. Solid -State Circuits, 2006,41(12):386-389
[26]谢詹奇,戴庆元.均衡器技术研究.微处理机, 2009,6(3):23-26
[27] Charles E. Berndt, Tad Kwansniewski. A Review of Common Receive-End Adaptive Equalization Schemes and Aglorithms for a High-Speed Serial Backplane. Proceeding of the 9th international Database Engineering&Application Symposium. 2005.10
[28] M. Q. LEE, P. J. Hurst, J. P. Keane. An Adaptive Analog Noise-Predictive Decision Feedback Equalizer. IEEE J. Solid -State Circuits, 2002,37(2):105-113
[29] G. Balamurugan, et al. Reciever Adaptation and System Characterization of An 8Gbps Source-Synchronous I/O Link Using On-die Circuits in 0.13μm CMOS. IEEE Symposium on VLSI, 2004(6):356-359
[30] B. Razavi. Prospects of CMOS Technology for High-Speed Optical Communication Circuits. IEEE J. Solid-State Circuits, 2002,9(37):1135-1145
[31] Riccardo Badalone. John D’Ambrosia. 10Gb/s Receive Equalization for High Loss Backplanes. DesignCon. 2005.9
[32] Patrik Larsson. High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler. IEEE J. Solid-State Circuits, 1996,31(5):744-748
[33]欧雨华,严利民.高速CMOS可编程分频器的研究与设计.微计算机信息,2006, 5(12): 57-63
[34]唐李红.5Gbps高速串行接口电路的研究与设计.国防科学技术大学硕士学位论文, 2009.3
[35]王建军.高速串行接口电路的研究与设计.国防科学技术大学硕士学位论文, 2006.10
[36] Christopher Saint, Judy Jaint著.周润德,金申美译.集成电路掩模设计—基础版图技术.北京:清华大学出版社, 2006.1
[37] Behzad Razavi著.陈贵灿等译.模拟CMOS集成电路设计.西安交通大学出版社, 2002.12
[38] Alan Hastings著.张为等译.模拟电路版图的艺术.北京:电子工业出版社,2007.4
[39] Steven H. Voldman. ESD Circuits and Devices. USA, John Wiley & Sons, Ltd, 2006.8
[40] L. Baker, R. Currence, S. Law, M. Lee, S. T. Lin, M. Teene. A Waffle Layout Technique Strengthens the ESD Hardness of the NMOS Output Transistor. Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, 1989; 175-181
[41] D. F. Beigel, E. L. Wolfe and W. A. Krieger. Integrated Circuit with Diode- -Connected Transistor for Reducing ESD Damage. U. S. Patent No. 5,637,901, 1997.06
[42] M. D. Ker, T. S. Wu, K. F. Wang. N-Sides Polygonal Cell Layout for Multiple Cell Transistor. U. S. Patent No. 5,852,315, 1998.12