超深亚微米LDD MOSFET器件模型及热载流子可靠性研究
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摘要
轻掺杂漏(LDD)工艺已经成为亚微米、超深亚微米MOS器件能够有效地抑止热载流子(HC)效应的标准工艺之一，但它同时也带来了在小尺寸器件模型和热载流子退化机理方面与常规结构器件的差异。本文针对超深亚微米漏工程器件的模型及可靠性的研究，建立了适用于超深亚微米LDD NMOSFET器件的Ⅰ-Ⅴ简捷模型并改善了衬底电流模型的描述。对实验数据的参数提取方法也进行了修正，使提取出的参数更符合实际情况。对热载流子的特殊退化机理从实验和理论两方面进行了详细研究，证实了超深亚微米LDD NMOSFET器件的两阶段退化机理。对低工作电压下的碰撞电离机理进行了较深入的分析，并且验证了在0.18微米CMOS工艺中EES效应和晶格温度升高带来的碰撞电离热助效应的存在，提出了在低电压下器件最坏热载流子应力条件转换的微观机理，并阐述了它们与器件热载流子寿命的关系。主要研究结果如下：
首先通过分析总结典型的短沟MOS器件模型的建模原理和适用范围，建立了适用于深亚微米、超深亚微米LDD NMOSFET的简捷器件模型(Compact model)。模型采用了双曲正切函数的经验描述方法，包括了对反型状态和亚阈状态的描述，结合短沟器件载流子速度饱和理论，充分考虑了各种短沟效应的影响因素。广泛采用理论分析和实验数据相结合的方法，对器件的阈值电压、输出特性、跨导特性、衬底电流等进行了解析分析，使模型的计算简便，且保证一定的精度。
重点分析了衬底电流的机理，在Ⅰ-Ⅴ特性模型的基础上建立了适用于LDD NMOSFET的短沟衬底电流半经验—半解析模型，其中对特征长度l这一非常重要的参数做了改进描述，使之更适合分析薄栅深亚微米器件的衬底电流特性，该模型被用于从亚微米到超深亚微米的LDD NMOSFET的性能描述，得到了与实验数据相一致的模拟结果。
设计并采用0.18微米CMOS工艺制造了LDD NMOSFET器件样品，对传统的参数提取方法进行了改进，提取出了与栅偏压和器件尺寸相关的参数，如阈值电压、源漏串联电阻、有效迁移率、有效沟道长度等等，这些参数的变化规律符合LDD器件的特殊工作机理，并应用到已经建立的器件模型中进行了验证分析，结果显示器件的输出电流特性、跨导特性、转移特性和衬底电流特性等的模拟与测试数据达到了很好的一致性，证明了参数的精确提取对器件建模的重要作用。
通过对自主设计的0.18微米CMOS器件工艺的LDD NMOSFET管芯进行的大量不同的HC应力测试，根据其阈值电压的漂移特点和线性漏电流的退化特性以及饱和趋势，证明了此阶段大多数界面损伤发生在质量较差的侧墙中，随后有更多的负电荷累积在栅—漏重叠区(亚扩散区)及沟道区，进一步证实了热载流子两阶
博十论文:超深亚微米LDD MOSFET器件模型及热载流子可靠性研究
段退化理论模型。得到具有氧化物侧墙的LDD NMOSFET器件所呈现的两个不同
退化阶段的不同机理:第一阶段，侧墙下LDD区漏串联电阻的增加;第二阶段，
主要是沟道中迁移率的减小。提出可靠性评估标准。
通过实验的方法验证了超深亚微米LDD NMOSFET的最坏热载流子应力条件
的转变，分析了沟道长度、漏电压和温度在决定最坏热载流子应力条件中的作用。
研究表明，最坏热载流子应力条件，是器件沟道长度、漏电压以及温度的函数。
随着超深亚微米NMOSFET器件尺寸的缩小和电源电压的降低，EES效应和自热
效应这样的能量获得机制，对其HC退化的影响越来越大，是出现非幸运电子模型
效应的根本原因。
对影响最坏热载流子应力条件的因素进行了深入分析，得出沟长的减小和温
度的降低均会促使最坏热载流子的栅压应力条件转变。最坏栅压应力条件从
IsuB，MAx(D AHC)转变为Vds=Vgs(C HC)，使加速热载流子应力下的器件寿命预测
理论需要重新修正。对于某些沟长的器件，栅压应力IsuB，~(DAHC)和Vds二Vgs
(C HC)下的器件寿命曲线有交叉现象，因此对于器件的最坏应力条件的评估，不能
只在每个应力条件下仅仅考察一个漏偏置电压。
分析了EES效应对低工作电压下的碰撞电离的增强作用。研究表明，电子能
量分布(EED)中的高能尾的存在，使EES效应对碰撞电离率M的影响在低温下
更明显。栅压vG的增大，使EES比率增加，引起M的增大。在MOSFET中，电
子的大部分能量是从高场区获得，因此，高能尾中的电子总数不仅依赖于电子的
密度，而且还与器件高场区的电场强度有关。在特定VD下随着LG的减小，漏端
的电场增强，EES效应增强。因此，对于低工作电压下抑止热载流子效应的超深
亚微米器件的设计，特别是应用于低温环境中的器件设计，EES效应的影响是不
可忽视的。
分析了晶格温度对超深亚微米LDD NMOSFET低工作电压下的碰撞电离的增
强作用。晶格温度引起的碰撞电离热助效应的研究表明，电子能量分布中的热尾
与晶格温度的关系，使低漏电压下的碰撞电离率对于温度的增加更加敏感，晶格
温度升高效应增强。随着电源电压等比例降至1 .2V以下，碰撞电离的产生因素从
电场转变为晶格温度，自热效应会促使这个问题更加严重。而栅偏压较高时，低
漏压下的碰撞电离热助特性可以被EES效应所掩盖。
这些在建立适用于深亚微米、超深亚微米LDD NMOSFET的器件模?
Hot carrier effect has a significant impact on submicron and deep-submicron scaling down MOSFET. The lightly-doped-drain (LDD) is an efficient process to improve hot carrier immunity of MOSFET. However, the parasitic series resistance and parasitic capacitance caused by the lightly doped region in the source/drain can reduce the drain current drive and the high frequency performance. The features such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), velocity saturation, etc, are of some difference from the features in conventional short channel devices, thus increasing the complexity of the MOSFET modeling.In this work, one emphasis is put on the nonlinear modeling of LDD MOSFET, wherein the drain current Ids is the key of the MOS equivalent circuit. A semi-empirical model of DC I-V characteristics for ultra-deep submicron LDD MOSFET is proposed by employing empirical hyperbolic tangent description and theory of carrier saturated-velocity under high electric field. The model deals with the I-V characteristics in either strong inversion or subthreshold region. Also the smooth transition between linear and saturation region is guaranteed by th(x) description, avoiding the discontinuity of drain conductance. The parasitic resistance due to the lightly doped region is treated as an external parameter. Because the substrate current in LDD MOSFET still demonstrates an unique characteristics different from the conventional MOSFET, particularly in the very short gate length devices, and it is very sensitive to the hot carrier degradation, a novel substrate current model which is different from that for conventional S/D device is proposed for submicron and deep-submicron lightly-doped-drain (LDD) n-MOSFET, with the emphasis on the description of an important parameter - characteristics length l, which takes into account the effects of channel length and bias. The maximum lateral electric field Em, the length of velocity saturation region ld which are very sensitive to drain current and substrate current are significantly affected by this parameter. The substrate current model can be easily embedded in the model to match the related device measurement and explore the hot carrier degradation of the deep submicron devices. The modeling of the device is based on the methodology for the physical model and the empirical model, thus decreasing the computation consumption, maintaining the accuracy, and clarifying the mechanism of devices. The comparison between simulations and measurements for submicron and deep submicron LDD MOSFETs shows an excellent agreements.Further more, the accuracy of some parameters, such as the threshold voltage,
drain-source parasitic resistance, the effective channel length, and the effective mobility, etc., is of great importance in the device's model. So we propose a novel parameters extraction method suitable for short channel length LDD MOSFET's. By subsection of the total gate bias range, the linear regression yields the gate bias independent parameters Rds, △L and μeff in a very small gate bias range. The repeat extraction operations in different subsections obtain the accurately gate bias dependent parameters in the total bias range. The method avoids the gate bias range optimization, retains the accuracy and simplicity of the linear regression extraction. The parameters are extracted from the measurements of the different gate lengths LDD NMOSFETs fabricated on 0.18μm CMOS technology, and as validity, are implemented in the compact I-V model. The excellent agreements between simulations and measurements indicate the effectivity of this technique.Another emphasis is on the different degradation behavior of ultra-deep submicron LDD NMOSFET from the conventional devices. Under the different stress conditions , including channel hot-carrier (CHC) stress and drain avalanche hot-carrier (DAHC) stress, the output drain current, the threshold voltage, the transconductance, the substrate current, the lifetime, etc., show the self-limiting time-dependent HC degradation, suitable
首先通过分析总结典型的短沟MOS器件模型的建模原理和适用范围，建立了适用于深亚微米、超深亚微米LDD NMOSFET的简捷器件模型(Compact model)。模型采用了双曲正切函数的经验描述方法，包括了对反型状态和亚阈状态的描述，结合短沟器件载流子速度饱和理论，充分考虑了各种短沟效应的影响因素。广泛采用理论分析和实验数据相结合的方法，对器件的阈值电压、输出特性、跨导特性、衬底电流等进行了解析分析，使模型的计算简便，且保证一定的精度。
重点分析了衬底电流的机理，在Ⅰ-Ⅴ特性模型的基础上建立了适用于LDD NMOSFET的短沟衬底电流半经验—半解析模型，其中对特征长度l这一非常重要的参数做了改进描述，使之更适合分析薄栅深亚微米器件的衬底电流特性，该模型被用于从亚微米到超深亚微米的LDD NMOSFET的性能描述，得到了与实验数据相一致的模拟结果。
设计并采用0.18微米CMOS工艺制造了LDD NMOSFET器件样品，对传统的参数提取方法进行了改进，提取出了与栅偏压和器件尺寸相关的参数，如阈值电压、源漏串联电阻、有效迁移率、有效沟道长度等等，这些参数的变化规律符合LDD器件的特殊工作机理，并应用到已经建立的器件模型中进行了验证分析，结果显示器件的输出电流特性、跨导特性、转移特性和衬底电流特性等的模拟与测试数据达到了很好的一致性，证明了参数的精确提取对器件建模的重要作用。
通过对自主设计的0.18微米CMOS器件工艺的LDD NMOSFET管芯进行的大量不同的HC应力测试，根据其阈值电压的漂移特点和线性漏电流的退化特性以及饱和趋势，证明了此阶段大多数界面损伤发生在质量较差的侧墙中，随后有更多的负电荷累积在栅—漏重叠区(亚扩散区)及沟道区，进一步证实了热载流子两阶
博十论文:超深亚微米LDD MOSFET器件模型及热载流子可靠性研究
段退化理论模型。得到具有氧化物侧墙的LDD NMOSFET器件所呈现的两个不同
退化阶段的不同机理:第一阶段，侧墙下LDD区漏串联电阻的增加;第二阶段，
主要是沟道中迁移率的减小。提出可靠性评估标准。
通过实验的方法验证了超深亚微米LDD NMOSFET的最坏热载流子应力条件
的转变，分析了沟道长度、漏电压和温度在决定最坏热载流子应力条件中的作用。
研究表明，最坏热载流子应力条件，是器件沟道长度、漏电压以及温度的函数。
随着超深亚微米NMOSFET器件尺寸的缩小和电源电压的降低，EES效应和自热
效应这样的能量获得机制，对其HC退化的影响越来越大，是出现非幸运电子模型
效应的根本原因。
对影响最坏热载流子应力条件的因素进行了深入分析，得出沟长的减小和温
度的降低均会促使最坏热载流子的栅压应力条件转变。最坏栅压应力条件从
IsuB，MAx(D AHC)转变为Vds=Vgs(C HC)，使加速热载流子应力下的器件寿命预测
理论需要重新修正。对于某些沟长的器件，栅压应力IsuB，~(DAHC)和Vds二Vgs
(C HC)下的器件寿命曲线有交叉现象，因此对于器件的最坏应力条件的评估，不能
只在每个应力条件下仅仅考察一个漏偏置电压。
分析了EES效应对低工作电压下的碰撞电离的增强作用。研究表明，电子能
量分布(EED)中的高能尾的存在，使EES效应对碰撞电离率M的影响在低温下
更明显。栅压vG的增大，使EES比率增加，引起M的增大。在MOSFET中，电
子的大部分能量是从高场区获得，因此，高能尾中的电子总数不仅依赖于电子的
密度，而且还与器件高场区的电场强度有关。在特定VD下随着LG的减小，漏端
的电场增强，EES效应增强。因此，对于低工作电压下抑止热载流子效应的超深
亚微米器件的设计，特别是应用于低温环境中的器件设计，EES效应的影响是不
可忽视的。
分析了晶格温度对超深亚微米LDD NMOSFET低工作电压下的碰撞电离的增
强作用。晶格温度引起的碰撞电离热助效应的研究表明，电子能量分布中的热尾
与晶格温度的关系，使低漏电压下的碰撞电离率对于温度的增加更加敏感，晶格
温度升高效应增强。随着电源电压等比例降至1 .2V以下，碰撞电离的产生因素从
电场转变为晶格温度，自热效应会促使这个问题更加严重。而栅偏压较高时，低
漏压下的碰撞电离热助特性可以被EES效应所掩盖。
这些在建立适用于深亚微米、超深亚微米LDD NMOSFET的器件模?
Hot carrier effect has a significant impact on submicron and deep-submicron scaling down MOSFET. The lightly-doped-drain (LDD) is an efficient process to improve hot carrier immunity of MOSFET. However, the parasitic series resistance and parasitic capacitance caused by the lightly doped region in the source/drain can reduce the drain current drive and the high frequency performance. The features such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), velocity saturation, etc, are of some difference from the features in conventional short channel devices, thus increasing the complexity of the MOSFET modeling.In this work, one emphasis is put on the nonlinear modeling of LDD MOSFET, wherein the drain current Ids is the key of the MOS equivalent circuit. A semi-empirical model of DC I-V characteristics for ultra-deep submicron LDD MOSFET is proposed by employing empirical hyperbolic tangent description and theory of carrier saturated-velocity under high electric field. The model deals with the I-V characteristics in either strong inversion or subthreshold region. Also the smooth transition between linear and saturation region is guaranteed by th(x) description, avoiding the discontinuity of drain conductance. The parasitic resistance due to the lightly doped region is treated as an external parameter. Because the substrate current in LDD MOSFET still demonstrates an unique characteristics different from the conventional MOSFET, particularly in the very short gate length devices, and it is very sensitive to the hot carrier degradation, a novel substrate current model which is different from that for conventional S/D device is proposed for submicron and deep-submicron lightly-doped-drain (LDD) n-MOSFET, with the emphasis on the description of an important parameter - characteristics length l, which takes into account the effects of channel length and bias. The maximum lateral electric field Em, the length of velocity saturation region ld which are very sensitive to drain current and substrate current are significantly affected by this parameter. The substrate current model can be easily embedded in the model to match the related device measurement and explore the hot carrier degradation of the deep submicron devices. The modeling of the device is based on the methodology for the physical model and the empirical model, thus decreasing the computation consumption, maintaining the accuracy, and clarifying the mechanism of devices. The comparison between simulations and measurements for submicron and deep submicron LDD MOSFETs shows an excellent agreements.Further more, the accuracy of some parameters, such as the threshold voltage,
drain-source parasitic resistance, the effective channel length, and the effective mobility, etc., is of great importance in the device's model. So we propose a novel parameters extraction method suitable for short channel length LDD MOSFET's. By subsection of the total gate bias range, the linear regression yields the gate bias independent parameters Rds, △L and μeff in a very small gate bias range. The repeat extraction operations in different subsections obtain the accurately gate bias dependent parameters in the total bias range. The method avoids the gate bias range optimization, retains the accuracy and simplicity of the linear regression extraction. The parameters are extracted from the measurements of the different gate lengths LDD NMOSFETs fabricated on 0.18μm CMOS technology, and as validity, are implemented in the compact I-V model. The excellent agreements between simulations and measurements indicate the effectivity of this technique.Another emphasis is on the different degradation behavior of ultra-deep submicron LDD NMOSFET from the conventional devices. Under the different stress conditions , including channel hot-carrier (CHC) stress and drain avalanche hot-carrier (DAHC) stress, the output drain current, the threshold voltage, the transconductance, the substrate current, the lifetime, etc., show the self-limiting time-dependent HC degradation, suitable
引文
[1] Chan M, Xi X.M., He J., et al. Practical compact modeling approaches and options for sub-0.1μm CMOS technologies. Microelectronics Reliability, 2003; 43: 399-404.
[2] Curtice W.R., Ettenberg M.. A nonlinear GaAs FET model for use in the design of output circuits for power amplifiers. IEEE Trans. Microwave Theory and Techniques, 1985; 33 (12):1383- 1394.
[3] Parker A.E., Skellern D.J.. A Realistic Large-Signal MESFET Model for SPICE. IEEE Trans. MTT, 1997; 45(9): 1563-1571.
[4] Angolov I., Rorsman N., Stenarson J., et al. An Empirical Table Based FET Model. IEEE MTT-S Digest, 1999, 525-528.
[5] Angelov I., Zirath H., Rorsman N., A New Empirical Nonlinear Model for HEMT and MESFET Devices. IEEE Trans. MTT, 1992; 40(12):2258-2266.
[6] Taur Y., MOSFET channel length: Extraction and interpretation. IEEE Transactions Electron Devices 2000; 47(l):160-170.
[7] Lim KY, Zhou X. A physically-based semi-empirical series resistance model for deep-submicron MOSFET I-V modeling. IEEE Transactions Electron Devices 2000; 47:1300-1302.
[8] Biesemans S, Hendriks M, Kubicek S, Meyer KD. Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFETs. IEEE Transactions Electron Devices 1998; 45(6): 1310-1316.
[9] Lou C-L, Chim W K, Chan D S, Pan Y. A novel single device DC method for extraction of the effective mobility and source-drain resistance of fresh and hot-carrier degraded drain-engineered MOSFETs. IEEE Transactions Electron Devices 1998; 45(6): 1317-1323.
[10] Jen SH-H, Enz CC, Pehlke DR, Schroter M, Sheu BJ. Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz. IEEE Transactions Electron Devices 1999; 46(11):2217-2227.
[11] Lim GM, Kim YC, Park YW, Kim DJ, Kim DM. Additional resistance method for extraction of separated nonlinear parasitic resistances and effective mobility in MOSFETs. Electron Letter 2000;36:1233-1234.
[12] Niu G.F., Cressler J.D., Mathew S.J., et al. A channel resistance derivative Method for effective channel length extraction in LDD MOSFETs. IEEE Transactions Electron Devices 2000; 47(3):648-650.
[13] Lee S. H. and. Yu H.K. A new technique to extraction channel mobility in submicron MOSFETs using inversion charge slope obtained from measured S-parameters. IEEE Transactions Electron Devices 2001; 48(4): 784-788.
[14] Katto H. Device parameters extraction in the linear region of MOSFET by comparing with the exact gradual channel model. Solid-State Electronics 2000; 44:969-976.
[15] Liang C, Gaw H, Cheng P. An analytical model for self-limiting behavior of hot-carrier degradation in 0.25-mm n-MOSFET's. IEEE Electron Device Letters 1992; 13:569.
[16] Hu C, Tam SC, Hsu FC, Ko PK, Chan TY, Terrill KW. Hot-electron-induced MOSFET degradation- model, monitor, and improvement. IEEE Transactions Electron Devices 1985;ED-32:375.
[17] Wang Q, Krautschneider WH, Brox M, Weber W. Time dependence of hot-carrier degradation in LDD nMOSFETs. In: Proceedings of Insulating Films on Semiconductors Conference. 1991: 441.
[18] Hsu FC, Grinolds HR. Structure-enhanced MOSFET degradation due to hot-electron injection. IEEE Electron Device Letters 1984;EDL-5:71.
[19] Hsu FC, Chiu KY. Evaluation of LDD MOSFET's based on hot-electron-induced degradation. IEEE Electron Device Letters 1984;EDL-5:162.
[20] Chan VH, Chung JE. Two-stage hot-carrier degradation and its impact on submicrometer LDD NMOSFET life-time prediction. IEEE Transactions Electron Devices 1995; 42:957.
[21] Raychaudhuri A, Deen MJ, Kwan WS, King MIH. Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFET's. IEEE Transactions Electron Devices 1996; 43:1114.
[22] Ang DS, Ling CH. A new assessment of the self-limiting hot-carrier degradation in LDD NMOSFET's by charge pumping measurement. IEEE Electron Device Letters 1997; 18(6):299.
[23] Ang DS, Ling CH. A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET's. IEEE Transactions Electron Devices 1998; 45:149.
[24] Okhonin S, Hessler T, Dutoit M. Kinetics of hot-carrier degradation of submicron n-channel LDD MOSFET's. Proceedings of the European Solid State Device Research Conference. 1996: 855.
[25] Kinugawa M., Kakuma M., Yokogawa S., and Hashimoto K. Submicron MLDD NMOSFET for 5 V operation, in Symp. VLSI Technol., Tech. Dig., 1985, pp. 116-117.
[26] Huang TY, Yao WW, Martin A, Lewis AG, Koyanagi M, Chen JY. A new LDD Transistor with inverse-T gate structure. IEEE Electron Device Letters 1987; EDL-8:151.
[27] Izawa R, Kure T, Takeda E. Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI. IEEE Transactions Electron Devices 1988; 35(12):2088.
[28] Bellens R, Vandenbosch G, et al. Performance and reliability aspects of FOND :a new deep submicron CMOS device concept. IEEE Transactions Electron Devices 1996; 43(9):1407-1415.
[29] Hori T, Kurimoto K, Yabu T, Fuse G. A new submicron MOSFET with LATID (large-tilt-angle implanted drain) structure, in Symp. VLSI Technol., Tech. Dig., 1988. p. 15-16.
[30] Nakamura K, Murakami E, et al. Impact of ultrashallow junction on hot carrier degradation of sub-0.25-um nMOSFETs. IEEE Electron Device Letters 2000; 21(1):27.
[31] Nishida A., Murakami E., and Kimura S. Characteristics of low-energy BF2 or as-implanted layers and their effect on the electrical performance of 0.1 Sum MOSFET's. IEEE Transactions Electron Devices 1998; 45:701-709.
[32] Matsuoka F, Kasai K, Oyamatsu H, Kinugawa M, Maeguchi K. Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET. IEEE Transactions Electron Devices 1994;41(3):420.
[33] Bryant A, Elkareh B, et al. A fundamental performance limit of optimized 3.3V sub-quarter micrometer fully overlapped LDD MODFETs. IEEE Transactions Electron Devices 1992; 39:1208.
[34] Chung SS, Yang JJ. A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's. IEEE Transactions Electron Devices 1999; 46(7): 1371.
[1] Pao H.C. and Sah C.T., Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors, Solid-State Electron., Vol.9, 1966: 927-937.
[2] Brews J.R., A charge sheet model of the MOSFET, Solid-State Electron. Vol.21, 1978: 345-355.
[3] Sah C.T., Characteristics of the MOS transistors, IEEE trans, ED, ED-11,1964:324-345.
[4] Schichman H., and Hodges D.A., Modeling and simulation of insulated-gate field-effect transistor switching circuits, IEEE J. Solid-State Circuit, SC-3, 1968: 285-289.
[5] Ihantola H.K.J., Moll J.L., Design theory of a surface field-effect transistor, Solid State Electron., Vol.7, 1964:423-430.
[6] Vladimirscu A. and Liu S., The simulation of MOS integrated circuits using SPICE2, UC Berkeley, October 1980.
[7] Yang P. and Chatterjee P.K., SPICE modeling for small geometry MOSFET circuits, IEEE Trans. CAD,Vol.CAD-l, 1982: 169-182.
[8] Duvvury C, Guide to short-channel effects in MOSFETs, IEEE Circuit and Device Mag., 1986: 6-10.
[9] Wright G.T., Physical and CAD model for the implanted-channel VLSI MOSFET, IEEE Trans. ED,ED-34, 1987:823-833.
[10] Silburt A.L., Foss R.C. and Petrie W.F., An efficient MOS transistor model for CAD, IEEE Trans. CAD, CAD-3, 1984: 104-110.
[11] Graaff H.C. and Klaassen F.M., Compact Transistor Modeling for Circuit Design, Springer-Verlag, Wien-New York, 1990.
[12] Huang C.L. and Gildenblat G. Sh., Measurements and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60-300K, IEEE Trans. ED.ED-37, 1990: 1289-1300.
[13] Lou C. L., Chim W. K., Chan S.H., et al. A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot carrier degraded drain-engineered MOSFET's. IEEE Trans. ED, Vol.45, No.6, 1998: 1317-1323.
[14] Tanizawa M., et al. A complete substrate current model including band-to-band tunneling current for circuit simulation. 1EEE Trans. CAD of IC systems, Vol. 12, No. 11, 1993:1749-1757.
[15] Li W., Yuan J.S. An improved substrate current model for deep submicron CMOS transistors. IEEE IRW Final Report, 2000: 146-148.
[16] Baum G. and beneking H., Drift velocity saturation in MOS transistor, IEEE Trans. ED, ED-17, 1970: 481-482.
[17] Frohman-Bentchkowsky D. and Grove A.S., Conductance of MOS transistors in saturation, IEEE Trans. ED, ED-17, 1965: 108-113.
[18] Banna M.E. and Nokali M.E., A pseudo-two-dimensional analysis of short channel MOSFETs, Solid-State Electron., Vol.31, 1988: 269-274.
[19] Liang M.S., Choi J.Y., Ko P.K., and Hu C.M., Inversion-layer capacitance and mobility of very thin gate oxide MOSFETs, IEEE Trans. ED, ED-33, 1986: 409-413.
[20] Arora N. D. and Gildenbalt G. Sh., A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation, IEEE Trans. ED, ED-34, 1987: 89-93.
[21] Wang P.P., Device characteristics of short-channel and narrow-width MOSFETs, IEEE Trans. ED, ED-25, 1978: 779-786.
[22] Risch L., Electron mobility in short-channel MOSFETs with series resistance, IEEE Trans., ED, ED-30, 1983: 959-961.
[23] N．Arora著，张兴等译，用于VLSI模拟的小尺寸MOS器件模型：理论与实践．科学出版社，北京，1999．
[1] Meyer J.E., MOS models and circuit simulation. RCA Review, Vol.32, 1971:42-63
[2] Pao H.C., Sah C.T., Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electronics, Vol. 9, 1966: 927-937
[3] Enz C.C., Krummenacher F., Vittoz E.A., An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage design and simulation. Low-Voltage Low-Power Devices, Vol.8, 1995: 83-114
[4] Lim K.M, Zhou X. A physically-based semi-empirical series resistance model for deep-submicron MOSFET Ⅰ-Ⅴ modeling. IEEE Trans. ED, Vol.47, No.6, 2000: 1300-1302.
[5] Mountain D. Application of electrical effective channel length and external resistance measurement techniques to a submicrometer CMOS process. 1EEE Trans. ED, Vol.36, No.11, 1989: 2499-2505.
[6] Zhou X., Lim. K.Y., and Lim D. A general approach to compact threshold voltage formulation based on 2-D numerical simulation and experimental correlation for deep-submicron ULSI technology development. IEEE Trans. ED, Vol.47, No. 1, 2000: 214-220.
[7] Biesemans S., Hendriks M., Kubicek S., et al. Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFET's. IEEE Trans. ED, Vol.45, No.6, 1998: 1310-1316.
[8] Chung S.S, Lee J.S. A new approach to determine the drain-and source series resistance of LDD MOSFET's. IEEE Trans. ED, Vol.40, No.9, 1993: 1709-1711.
[9] Niu G.F, Mathew S.J., Cressler J.D, et al. A novel channel resistance ratio method for effective channel length and series resistance extraction in MOSFETs. Solid State Electronics, (44), No.7, 2000:1187-1189.
[10] Taur Y., Zicherman D. S., Lombardi D. R., et al. A new "Shift and Ratio" method for MOSFET channel-length extraction, IEEE Electron Devices Lett., vol. 13, No.5,1992:267-269.
[11] Takeuchi K., Kasai N., Kunio T., and Terada K.. An effective channel length determination method for LDD MOSFET's, IEEE Trans Electron Devices, vol. 43, No.4, 1996:580-587.
[12] Niu G., Cressler J. D., Mathew S. J., and Subbanna S.. A total resistance slope-based effective channel mobility extraction method for deep submicrometer CMOS technology, IEEE Trans. Electron Devices, vol. 46, No.9, 1999:1912-1914.
[13] Lee S., and Yu H.K. A New Technique to Extract Channel Mobility in Submicron MOSFETs Using Inversion Charge Slope Obtained from Measured S-Parameters. IEEE Trans. Electron Devices, vol. 48, No.4, 2001:784-788.
[14] Curtice W.R., Ettenberg M.. A nonlinear GaAs FET model for use in the design of output circuits for power amplifiers. IEEE Trans. Microwave Theory and Techniques, 1985 , 33 (12):1383-1394
[15] Parker A.E., Skellern D.J.. A Realistic Large-Signal MESFET Model for SPICE. IEEE Trans. MTT, Vol.45, No.9, Sep. 1997:1563-1571
[16] Angolov I., Rorsman N., Stenarson J., et al. An Empirical Table Based FET Model. IEEE MTT-S Digest, 1999, 525-528
[17] Angelov I., Zirath H., Rorsman N., A New Empirical Nonlinear Model for HEMT and MESFET Devices. IEEE Trans. MTT, Vol.40, No. 12, Dec. 1992:2258-2266
[18] Zhou X., Lim. K.Y. Unified MOSFET compact I-V model formulation through physics-based effective transformation. IEEE Trans. ED, Vol.48, No.5, 2001: 887-896.
[19] Liu Z.H., Hu C.M., Huang J.H., et al. Threshold model for deep-submicron MOSFET's. IEEE Trans. ED, Vol.40, No.1, 1993: 86-95.
[20] Lou C.L., Chim W.K., Chan S.H., et al. A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot carrier degraded drain-engineered MOSFET's. IEEE Trans. ED, Vol.45, No.6, 1998: 1317-1323.
[21] Wright G.T.. physical and CAD model for the implanted-channel VLSI MOSFET, IEEE Trans. ED, Vol.34, 1987:823-833.
[22] Jang S.L., Liu S.S., and Sheu C.J.. A compact LDD MOSFET I-V model based on nonpinned surface potential. IEEE Trans. ED, Vol.45, No. 12, 1998: 2489-2498.
[23] Chan T.P., Ko P.K., Hu C.M.. Dependence of channel electric field on device scaling. IEEE EDL, Vol.EDL-6, No. 10, 1985: 551-554.
[24] Hu Y., Booth R.V.H., and white M.H.. An analytical model for the lateral channel electric field in LDD structures. IEEE Trans. ED, Vol.37, No. 12, 1990: 2254-2263.
[1] Chan T., Ko P., Hu C. A simple method to characterize substrate current in MOSFET's. IEEE EDL, Vol.EDL-5, No. 12, 1984: 505-507.
[2] Chan T.Y., Ko P.K., Hu C.M.. Dependence of channel electric field on device scaling. IEEE EDL, Vol.EDL-6, No. 10, 1985: 551-554.
[3] Arora N D and Sharma M S. MOSFET substrate current model for circuit simulation. IEEE Trans. ED, 38, No.6, 1991:1392-1398
[4] Tanizawa M., et al. A complete substrate current model including band-to-band tunneling current for circuit simulation. IEEE Trans. CAD of IC systems, Vol. 12, No. 11, 1993:1749-1757.
[5] Ramaswarny S., Amerasekera A Chang M. C. A unified substrate current model for weak and strong impact ionization in sub-0.25um NMOS devices. IEDM Tech. Dig., 1997:885-886.
[6] Li W., Yuan J.S. An improved substrate current model for deep submicron CMOS transistors. IEEE IRW Final Report, 2000:146-148.
[7] Liu Z.H., Hu C.M., Huang J.H., et al. Threshold model for deep-submicron MOSFET's. IEEE Trans. ED, Vol.40, No.1, 1993: 86-95.
[8] Chung J., Jeng M.C., May G., et al. Hot-electron currents in deep-submicrometer MOSFETs. IEEE IEDM-88, 1988:200-203.
[9] Huang G S and Wu C Y. An analytical saturation model for drain and substrate current of conventional and LDD MOSFET's. 1990 IEEE Trans. ED, 37, No.7, 1667-1677
[10] Yang J J, Chung S S, and Chou P C, et al. A New Approach to modeling the substrate current of Pre-stressed and Post-stressed MOSFET's. 1995 IEEE Trans. ED, 42, No.6, 1113-1119
[11] Hu Y, Booth R V H, and white M H. An analytical model for the lateral channel electric field in LDD structures. 1990 IEEE Trans. ED, 37, No. 10, 2254-2263
[12] Liu S S, Jang S L, and Chyau C G. Compact LDD nMOSFET Degradation Model. 1998 IEEE Trans .ED, 45,N0.7, 1538-547
[13] Jang S.L., Liu S.S., and Sheu C.J.. A compact LDD MOSFET I-V model based on nonpinned surface potential. IEEE Trans. ED, Vol.45, No.12, 1998: 2489-2498.
[1] Liu Z.H., Hu C.M., Huang J.H., et al. Threshold model for deep-submicron MOSFET's. IEEE Trans. ED, Vol.40, No.1, 1993: 86-95.
[2] A.Ortiz-Conde et al. New approach for defining the threshold voltage of MOSFETs. IEEE Trans. ED, Vol.48, No.4, 2001: 809-813.
[3] X. Zhou, K. Y. Lim, and D. Lim. A Simple and Unambiguous Definition of Threshold Voltage and Its Implications in Deep-Submicron MOS Device Modeling. IEEE Trans. ED, VOL. 46, NO. 4, 1999: 807-809
[4] Tsuno.M et al. Physically-based threshold voltage determination for MOSFETs of all gate lengths. IEEE ED, Vol.46, No.12, 1999: 1429-1434.
[5] Terada K. et al. Comparison of MOSFET-threshold-voltage extraction methods. Solid-State Electronics Vol.45, No.1, 2001: 35-40.
[6] Taur Y., MOSFET channel length: Extraction and interpretation, IEEE Trans. ED, Vol. 47, No.1, 2000:160-170.
[7] Hu GJ, Chang C, Chia Y-T. Gate-voltage-dependent effective channel length and series resistance of LDD MOSFETs. IEEE Trans Electron Dev 1987;34:2469-75.
[8] Lim KY, Zhou X. A physically-based semi-empirical series resistance model for deep-submicron MOSFET I-V modeling. IEEE Trans Electron Dev 2000;47:1300-2.
[9] Biesemans S, Hendriks M, Kubicek S, Meyer KD. Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFETs. IEEE Trans Electron Dev 1998;45(6): 1310-6.
[10] Lou C-L, Chim WK, Chan DDS, Pan Y. A novel single device DC method for extraction of the effective mobility and source-drain resistance of fresh and hot-carrier degraded drain-engineered MOSFETs. IEEE Trans Electron Dev 1998;45(6): 1317-23.
[11] Guo JC, Chung SS-S, Hsu CC-H. A new approach to determine the effective channel length and drain-and source series resistance of miniaturized MOSFETs. IEEE Trans Electron Dev 1987;41(10):1811-8.
[12] Ortiz-Conde A, Liou JJ, Wong W, Garcia Sanchez FJ. Simple method for extracting the difference between the drain and source series resistances in MOSFETs. Electron Letter 1994;30(6):1013-5.
[13] Raychaudhuri A, Kolk J, Deen MJ, King MIH. A simple method to extract the asymmetry in parasitic source and drain resistances from measurements on a MOS transistor. IEEE Trans Electron Dev 1995;42:1388-90.
[14] Jen SH-H, Enz CC, Pehlke DR, Schroter M, Sheu BJ. Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz. IEEE Trans Electron Dev 1999;46(11):2217-27.
[15] Lee S, Yu HK, Kim CS, Koo JG, Nam KS. A novel approach to extract small-signal model parameters of silicon MOSFETs. IEEE Microwave Guided Wave Letter 1997; 7(3):75-7.
[16] Lim GM, Kim YC, Park YW, Kim DJ, Kim DM. Additional resistance method for extraction of separated nonlinear parasitic resistances and effective mobility in MOSFETs. Electron Letter 2000;36:1233-4.
[17] Niu G.F., Cressler J.D., Mathew S.J., et al. A channel resistance derivative Method for effective channel length extraction in LDD MOSFETs. IEEE ED, Vol.47, NO.3, 2000:648-650.
[18] Lee S. H. and. Yu H.K, "A new technique to extraction channel mobility in submicron MOSFETs using inversion charge slope obtained from measured S-parameters", IEEE Trans. Electron Devices, Vol.48, pp.784-788, Apr. 2001
[19] Katto H., "Device parameters extraction in the linear region of MOSFET by comparing with the exact gradual channel model", Solid-State Electronics, Vol.44, pp.969-976, 2000
[1] Gesch H, Leburton JP, Dorda GE. Generation of inter-face states by hot hole injection in MOSFETs. IEEE Transactions Electron Devices 1982;ED-29:913.
[2] Ng KK, Taylor GW. Effects of hot-carrier trapping in n-and p-channel MOSFET's. IEEE Transactions Electron Devices 1983;ED-30:871.
[3] Takeda E, Suzuki N. An empirical model for device degradation due to hot-carrier injection. IEEE Electron Device Letters 1983;EDL-4:111.
[4] Takeda E, Shimizu A, Hagiwara T. Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFET's. IEEE Electron Device Letters 1983;EDL-4:329.
[5] Hu C, Tam SC, Hsu FC, Ko PK, Chan TY, Terrill KW. Hot-electron-induced MOSFET degradation- model, monitor, and improvement. IEEE Transactions Electron Devices 1985;ED-32:375.
[6] Tsuchiya T, Kobayashi T, Nakajima S. Hot-carrier-injected oxide region and hot-electron trapping as the main cause in Si nMOSFET degradation. IEEE Transactions Electron Devices 1987;ED-34:386.
[7] Schwerin A, Hansch W, Weber W. The relationship between oxide charge and device degradation: a comparative study of n- and p-channel MOSFET's. IEEE Transactions Electron Devices 1987;ED-34:2493.
[8] Heremans P, Bellens R, Groeseneken G, Maes HE. Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's. IEEE Transactions Electron Devices 1988;35:2194.
[9] Ogura S, et al. Design and characteristics of the lightly-doped drain-source (LDD) insulated gate FET. IEEE Transactions Electron Devices 1980;ED-27:1359.
[10] Tsang PJ, et al. Fabrication of high-performance LDD FETs with oxide sidewall spacer technology. IEEE Transactions Electron Devices 1982;ED-29:590.
[11] Huang TY, Yao WW, Martin A, Lewis AG, Koyanagi M, Chen JY. A new LDD Transistor with inverse-T gate structure. IEEE Electron Device Letters 1987.EDL-8:151.
[12] Izawa R, Kure T, Takeda E. Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI. IEEE Transactions Electron Devices 1988;35:2088.
[13] Hori T, Kurimoto K, Yabu T, Fuse G. A new submicron MOSFET with LATID (large-tilt-angle implanted drain) structure. In: Proceedings of VLSI Technology Symposium. 1988. p. 15.
[14] Matsuoka F, Kasai K, Oyamatsu H, Kinugawa M, Maeguchi K. Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET. IEEE Transactions Electron Devices 1994 ;41:420.
[15] Hsu FC, Grinolds HR. Structure-enhanced MOSFET degradation due to hot-electron injection. IEEE Electron Device Letters 1984;EDL-5:71.
[16] Hsu FC, Chiu KY. Evaluation of LDD MOSFET's based on hot-electron-induced degradation. IEEE Electron Device Letters 1984;EDL-5:162.
[17] Chung JE, Ko PK, and Hu C. A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation. IEEE Trans. Electron Devices 1991; 38: 1362.
[18] Cham K, Hui J, Voorde PV, Fu H. Self-limiting behavior of hot carrier degradation and its implication on the validity of lifetime extraction by accelerated stress. In: Proceedings of international Reliability Physics Symposium. 1987. p. 191.
[19] Sun SW, Orlowski M, Fu KY. Parameter correlation and modeling of the power-law relationship in MOSFET hot-carrier degradation. IEEE Electron Device Letters 1990; 11:297.
[20] Wang Q, Krautschneider WH, Brox M, Weber W. Time dependence of hot-carrier degradation in LDD nMOSFETs. Proceedings of Insulating Films on Semiconductors Conference. 1991: 441.
[21] Liang C, Gaw H, Cheng P. An analytical model for self-limiting behavior of hot-carrier degradation in 0.25-mm n-MOSFET's. IEEE Electron Device Letters1992; 13:569.
[22] Chan VH, Chung JE. Two-stage hot-carrier degradation and its impact on submicrometer LDD NMOSFET life-time prediction. IEEE Transactions Electron Devices 1995;42:957.
[23] Raychaudhuri A, Deen MJ, Kwan WS, King MIH. Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFET's. IEEE Transactions Electron Devices 1996;43:1114.
[24] Okhonin S, Hessler T, Dutoit M. Kinetics of hot-carrier degradation of submicron n-channel LDD MOSFET's. Proceedings of the European Solid State Device Research Conference. 1996:855.
[25] Ang DS, Ling CH. A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET's. IEEE Transactions Electron Devices 1998;45:149.
[26] Ang DS, Ling CH. A new assessment of the self-limiting hot-carrier degradation in LDD NMOSFET's by charge pumping measurement. IEEE Electron Device Letters 1997; 18(6):299.
[27] Goo JS, Shin H, Hwang H, Kang DG, Ju DH. Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain n-channel metal-oxide-semiconductor field effect transistors. Japanese Journal of Applied Physics 1994;33(1):606.
[28] Groeseneken G, Maes HE, Beltran N, Keersmaecker RF. A reliable approach to charge pumping measurement in MOS transistors. IEEE Transactions Electron Devices 1984;ED-31:42.
[29] Chen W, Balasinski A, Ma TP. Lateral profiling of oxide charge and interface traps near MOSFET junctions. IEEE Transactions Electron Devices 1993;40:187.
[30] Heremans P, Witters J, Groeseneken G, Maes HE. Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation. IEEE Transactions Electron Devices 1989;36:1318.
[31] Tsuchiaki M, Hara H, Morimoto T, Iwai H. A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFET's. IEEE Transactions Electron Devices 1993;40:1768.
[32] Ling CH, Tan SE, Ang DS. A study of hot-carrier degradation in NMOSFET's by gate capacitance and charge pumping current. IEEE Transactions Electron Devices 1995 ;42(7): 1321.
[33] Heremans P, Bellens R, Groeseneken G, Maes HE. Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's. IEEE Transactions Electron Devices 1998;35:2194.
[34] Doyle BS, Bourcerie M, Bergonzoni C, et al. The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot carrier stressing of NMOS transistors. IEEE Transactions Electron Devices 1990;37:1869.
[35] Mahapatra S, Parikh CD, Rao VR, et al. A comprehensive study of hot-carrier induced interface and oxide trap distribution in MOSFET's using a novel charge pumping technique. IEEE Transactions Electron Devices 2000;47:171.
[36] Lou CL, Chim WK, Chan DS H, Pan Y. A novel single device method for extraction of the effective mobility and source-drain resistance of fresh and hot-carrier degraded drain-engineered MOSFETs. IEEE Transactions Electron Devices 1998;45:1317.
[37] Chim WK, Leang SE, Chan DS H. Extraction of metal-oxide-semiconductor field-effect-transistor interface state and trapped charge spatial distribution using a physics-based algorithm. J Appl Phys 1997;81(4): 1992.
[38] Cheng SM, Yih CM, Yeh JC, et al. A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions. IEEE Transactions Electron Devices 1997;44(11):1908.
[39] Yeow YT, Ling CH, and Ah LK. Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement. IEEE Electron Device Lett 1991;12: 366.
[40] Ling CH, Yeow YT, and Ah LK. Characterization of charge trapping in submicrometer NMOSFET's by gate capacitance measurement. IEEE Electron Device Lett. 1992 ; 13: 587.
[41] Lee RGH, Su JS, and Chung SS. A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's. IEEE Trans. Electron Devices 1996; 43: 81.
[42] Chen W and Ma TP. A new technique for measuring lateral distribution of oxide charge and interface traps near MOSFET junctions. IEEE Electron Device Lett. 1991; 7: 393.
[43] Okhonin S, Hessler T, and Dutoit M. Comparison of gate-induced drain leakage and charge pumping measurements for determining lateral interface trap profiles in electrically stressed MOSFET's. IEEE Trans. Electron Devices 1996 ; 43: 605.
[44] Manhas SK, Sehkar DC, Oates AS, et al. Characterisation of series resistance degradation through charge pumping technique. Microelectronics reliab. 2003;43:617-624.
[45] Manchanda L, Storz RH, Yan RH, Lee KF, Westerwick EH. Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 lm Si MOSFETs. In: IEDM Tech Dig, 1992. p.994-996.
[46] Anil KG, Mahapatra S, Eisel I. Role of inversion layer quantization on sub-bandgap impact ionization in deepsubmicron n-channel MOSFETs. In: IEDM Tech Dig, 2000. p. 675-678.
[47] Saraya T, Takamiya M, Duyet TN, Tanaka T, Ishikuro H, Hiramoto T, et al. Floating body effects in 0.15 um partially depleted SOI MOSFETs below 1 V. Proc IEEE Int SOI Conf, 1996:70-71.
[48] Abramo A, Brunetti R, Jacaboni C, Venturi F, Sangiorgi E. A multiband Monte Carlo approach to Coulomb interaction for device analysis. J Appl Phys 1994;76(10): 5786-5794.
[49] Fischetti MV, Laux SE. Monte Carlo study of sub-bandgap impact ionization in small silicon field-effect transistors. In: IEDM Tech Dig, 1995. p. 305-308.
[50] Ghetti A, Selmi L, Bez R. Low-voltage hot electrons and soft-programming lifetime prediction in nonvolatile memory cells. IEEE Trans Electron Device 1999;46(4):696-702.
[51] Fischetti MV, Laux SE, Crabbe E. Understanding hotelectron transport in silicon devices: Is there a shortcut? J Appl Phys 1995;78(2): 1058-1086.
[52] Mietzner T, Jakumeit J, Ravaioli U. Local iterative Monte Carlo analysis of electron-electron interaction in shortchannel Si-MOSFETs. IEEE Trans Electron Device 2001; 48(10):2323-2330.
[53] King EE, Lacoe RC and Wang RJ. The role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices. International Reliability Physics Proceedings, 2000. p. 83-92.
[54] Ratkovic J W, Lacoe RC, Macwilliams KP, et al. New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures. International Reliability Physics Proceedings, 1997. p. 312-319.
[55] Su P, Goto K, Sugii T, and Hu C. Enhanced substrate current in SOI MOSFETs. IEEE Electron Device Lett. 2002; 23(5):282-284.
[56] Eitan B, Frohman-Bentchkowsky D, and Shappir J. Impact ionization at very low voltages in silicon. J. Appl. Phys. 1982; 53(2): 1244-1247.
[57] Esseni D, Selmi L, Sangiorgi E, Bez R, and Ricco B. Temperature dependence of gate and substrate currents in the CHE crossover regime. IEEE Electron Device Lett 1995; 16(11): 506-508.
[58] Sze S M. Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
[59] Taur Y and Ning T H. Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
[60] Fischetti M and Laux S. Monte Carlo study of sub-band-gap impact ionization in small silicon field-effect transistors, in IEDM Tech. Dig ,1995. p. 305-308.
[61] Sano N, Tomizawa M, and Yoshii A. Temperature dependence of hot carrier effects in short-channel Si-MOSFETs. IEEE Trans. Electron Devices, 1995;42(12): 2211-2211.
[62] Mastrapasqua M, Bude J, Pinto M, Manchanda L, and Lee K. Temperature and channel length dependence of impact ionization in P-channel MOSFETs. in Symp. VLSI Technol., 1994. p. 125-126.
[63] Tam S, Ko PK and Hu C. Lucky-electron model of channel hot electron injection in MOSFETs. IEEE Trans. Electron Devices, 1984, 31 (6): 1116
[64] Rauch S, Guarin F, and LaRosa G. Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs. IEEE Electron Device Lett., 1998;19(12): 463-465.
[65] Childs P and Leung C. A one-dimensional solution of the Boltzmann transport equation including electron-electron interactions. J. Appl. Phys., 1996;79(1):222-227.
[66] Chung J, Jeng MC, Moon J, Ko PK, and Hu C. Low-voltage hot electron currents and degradation in deep-submicrometer MOSFET's. IEEE Trans. Electron Devices, 1990;37(7):1651.
[67] Aur S. Low-voltage hot-carrier effects and stress methodology. Proc. Int. Symp. VLSI Technol., 1995:277
[68] Mizuno T, Toriumi A, Iwase M, et al. Hot-carrier effects in 0.1-μm gate length CMOS devices. IEDM Tech. Dig., 1992: 695
[69] Ellis-Monaghan J. J., Hulfachor R. B., Kim K. W., et al. Ensemble Monte Carlo study of interface-state generation in low voltage scaled silicon MOS devices. IEEE Trans. Electron Devices, 1996, 43(6): 1123
[70] Abramo A., Fiegna C, and Venturi F.. Hot-carrier effects in short MOSFETs at low applied voltages. IEDM Tech. Dig., 1995:301
[71] Bude J., Iizuka T., and Kamakura Y.. Determination of threshold energy for hot electron interface state generation. IEDM Tech. Dig., 1996: 865
[72] Childs P. and Leung C. New mechanism of hot-carrier generation in very short channel MOSFETs. Electron. Lett., 1995, 31(2): 139
[73] Lee S, Hwang JM, and Lee HD. Experimental evidence for nonlucky electron model effect in 0.15μm NMOSFETs. IEEE Trans. Electron Device,2002,49(11):1876
[74] Anil KG, Mahapatra S, Eisele I. Experimental verification of the high energy tail in the electron energy distribution in n-channel MOSFETs. IEEE Electron Device Lett 2001; 22(10):478-480.
[75] Anil KG, Mahapatra S, Eisele I. Electron-electron interaction signature peak in the substrate current vs gate voltage characteristics of n-channel silicon MOSFETs. IEEE Trans Electron Device 2002;49(7): 1283-1288.
[76] Anil KG, Mahapatra S, Eisele I. A detailed experimental investigation of impact ionization in n-channel metal -oxide-semiconductor field-effect-transistors at very low drain voltages. Solid-State Electronics 2003;47(6):995-1001.
[77] Su P, Goto KI, Sugii T, Hu C. A thermal activation view of low voltage impact ionization in MOSFETs. IEEE Electron Device Lett 2002; 23(9):550-552.
[78] Chen Z. et al. On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing. IEEE Electron Device Lett.,2000,21(1):24.
[79] Ang DS and Ling CH. On the Dominant interface trap generation process during hot-carrier stressing. Int. Reliability Physics Symp. Proa, 2001:412.
[80] Raychaudhuri A, Deen MJ, et al. A simple method to qualify the LDD structure against the early mode of hot-carrier degradation. IEEE Trans Electron Device 1996;43(1):110-115.
[2] Curtice W.R., Ettenberg M.. A nonlinear GaAs FET model for use in the design of output circuits for power amplifiers. IEEE Trans. Microwave Theory and Techniques, 1985; 33 (12):1383- 1394.
[3] Parker A.E., Skellern D.J.. A Realistic Large-Signal MESFET Model for SPICE. IEEE Trans. MTT, 1997; 45(9): 1563-1571.
[4] Angolov I., Rorsman N., Stenarson J., et al. An Empirical Table Based FET Model. IEEE MTT-S Digest, 1999, 525-528.
[5] Angelov I., Zirath H., Rorsman N., A New Empirical Nonlinear Model for HEMT and MESFET Devices. IEEE Trans. MTT, 1992; 40(12):2258-2266.
[6] Taur Y., MOSFET channel length: Extraction and interpretation. IEEE Transactions Electron Devices 2000; 47(l):160-170.
[7] Lim KY, Zhou X. A physically-based semi-empirical series resistance model for deep-submicron MOSFET I-V modeling. IEEE Transactions Electron Devices 2000; 47:1300-1302.
[8] Biesemans S, Hendriks M, Kubicek S, Meyer KD. Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFETs. IEEE Transactions Electron Devices 1998; 45(6): 1310-1316.
[9] Lou C-L, Chim W K, Chan D S, Pan Y. A novel single device DC method for extraction of the effective mobility and source-drain resistance of fresh and hot-carrier degraded drain-engineered MOSFETs. IEEE Transactions Electron Devices 1998; 45(6): 1317-1323.
[10] Jen SH-H, Enz CC, Pehlke DR, Schroter M, Sheu BJ. Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz. IEEE Transactions Electron Devices 1999; 46(11):2217-2227.
[11] Lim GM, Kim YC, Park YW, Kim DJ, Kim DM. Additional resistance method for extraction of separated nonlinear parasitic resistances and effective mobility in MOSFETs. Electron Letter 2000;36:1233-1234.
[12] Niu G.F., Cressler J.D., Mathew S.J., et al. A channel resistance derivative Method for effective channel length extraction in LDD MOSFETs. IEEE Transactions Electron Devices 2000; 47(3):648-650.
[13] Lee S. H. and. Yu H.K. A new technique to extraction channel mobility in submicron MOSFETs using inversion charge slope obtained from measured S-parameters. IEEE Transactions Electron Devices 2001; 48(4): 784-788.
[14] Katto H. Device parameters extraction in the linear region of MOSFET by comparing with the exact gradual channel model. Solid-State Electronics 2000; 44:969-976.
[15] Liang C, Gaw H, Cheng P. An analytical model for self-limiting behavior of hot-carrier degradation in 0.25-mm n-MOSFET's. IEEE Electron Device Letters 1992; 13:569.
[16] Hu C, Tam SC, Hsu FC, Ko PK, Chan TY, Terrill KW. Hot-electron-induced MOSFET degradation- model, monitor, and improvement. IEEE Transactions Electron Devices 1985;ED-32:375.
[17] Wang Q, Krautschneider WH, Brox M, Weber W. Time dependence of hot-carrier degradation in LDD nMOSFETs. In: Proceedings of Insulating Films on Semiconductors Conference. 1991: 441.
[18] Hsu FC, Grinolds HR. Structure-enhanced MOSFET degradation due to hot-electron injection. IEEE Electron Device Letters 1984;EDL-5:71.
[19] Hsu FC, Chiu KY. Evaluation of LDD MOSFET's based on hot-electron-induced degradation. IEEE Electron Device Letters 1984;EDL-5:162.
[20] Chan VH, Chung JE. Two-stage hot-carrier degradation and its impact on submicrometer LDD NMOSFET life-time prediction. IEEE Transactions Electron Devices 1995; 42:957.
[21] Raychaudhuri A, Deen MJ, Kwan WS, King MIH. Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFET's. IEEE Transactions Electron Devices 1996; 43:1114.
[22] Ang DS, Ling CH. A new assessment of the self-limiting hot-carrier degradation in LDD NMOSFET's by charge pumping measurement. IEEE Electron Device Letters 1997; 18(6):299.
[23] Ang DS, Ling CH. A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET's. IEEE Transactions Electron Devices 1998; 45:149.
[24] Okhonin S, Hessler T, Dutoit M. Kinetics of hot-carrier degradation of submicron n-channel LDD MOSFET's. Proceedings of the European Solid State Device Research Conference. 1996: 855.
[25] Kinugawa M., Kakuma M., Yokogawa S., and Hashimoto K. Submicron MLDD NMOSFET for 5 V operation, in Symp. VLSI Technol., Tech. Dig., 1985, pp. 116-117.
[26] Huang TY, Yao WW, Martin A, Lewis AG, Koyanagi M, Chen JY. A new LDD Transistor with inverse-T gate structure. IEEE Electron Device Letters 1987; EDL-8:151.
[27] Izawa R, Kure T, Takeda E. Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI. IEEE Transactions Electron Devices 1988; 35(12):2088.
[28] Bellens R, Vandenbosch G, et al. Performance and reliability aspects of FOND :a new deep submicron CMOS device concept. IEEE Transactions Electron Devices 1996; 43(9):1407-1415.
[29] Hori T, Kurimoto K, Yabu T, Fuse G. A new submicron MOSFET with LATID (large-tilt-angle implanted drain) structure, in Symp. VLSI Technol., Tech. Dig., 1988. p. 15-16.
[30] Nakamura K, Murakami E, et al. Impact of ultrashallow junction on hot carrier degradation of sub-0.25-um nMOSFETs. IEEE Electron Device Letters 2000; 21(1):27.
[31] Nishida A., Murakami E., and Kimura S. Characteristics of low-energy BF2 or as-implanted layers and their effect on the electrical performance of 0.1 Sum MOSFET's. IEEE Transactions Electron Devices 1998; 45:701-709.
[32] Matsuoka F, Kasai K, Oyamatsu H, Kinugawa M, Maeguchi K. Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET. IEEE Transactions Electron Devices 1994;41(3):420.
[33] Bryant A, Elkareh B, et al. A fundamental performance limit of optimized 3.3V sub-quarter micrometer fully overlapped LDD MODFETs. IEEE Transactions Electron Devices 1992; 39:1208.
[34] Chung SS, Yang JJ. A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's. IEEE Transactions Electron Devices 1999; 46(7): 1371.
[1] Pao H.C. and Sah C.T., Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors, Solid-State Electron., Vol.9, 1966: 927-937.
[2] Brews J.R., A charge sheet model of the MOSFET, Solid-State Electron. Vol.21, 1978: 345-355.
[3] Sah C.T., Characteristics of the MOS transistors, IEEE trans, ED, ED-11,1964:324-345.
[4] Schichman H., and Hodges D.A., Modeling and simulation of insulated-gate field-effect transistor switching circuits, IEEE J. Solid-State Circuit, SC-3, 1968: 285-289.
[5] Ihantola H.K.J., Moll J.L., Design theory of a surface field-effect transistor, Solid State Electron., Vol.7, 1964:423-430.
[6] Vladimirscu A. and Liu S., The simulation of MOS integrated circuits using SPICE2, UC Berkeley, October 1980.
[7] Yang P. and Chatterjee P.K., SPICE modeling for small geometry MOSFET circuits, IEEE Trans. CAD,Vol.CAD-l, 1982: 169-182.
[8] Duvvury C, Guide to short-channel effects in MOSFETs, IEEE Circuit and Device Mag., 1986: 6-10.
[9] Wright G.T., Physical and CAD model for the implanted-channel VLSI MOSFET, IEEE Trans. ED,ED-34, 1987:823-833.
[10] Silburt A.L., Foss R.C. and Petrie W.F., An efficient MOS transistor model for CAD, IEEE Trans. CAD, CAD-3, 1984: 104-110.
[11] Graaff H.C. and Klaassen F.M., Compact Transistor Modeling for Circuit Design, Springer-Verlag, Wien-New York, 1990.
[12] Huang C.L. and Gildenblat G. Sh., Measurements and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60-300K, IEEE Trans. ED.ED-37, 1990: 1289-1300.
[13] Lou C. L., Chim W. K., Chan S.H., et al. A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot carrier degraded drain-engineered MOSFET's. IEEE Trans. ED, Vol.45, No.6, 1998: 1317-1323.
[14] Tanizawa M., et al. A complete substrate current model including band-to-band tunneling current for circuit simulation. 1EEE Trans. CAD of IC systems, Vol. 12, No. 11, 1993:1749-1757.
[15] Li W., Yuan J.S. An improved substrate current model for deep submicron CMOS transistors. IEEE IRW Final Report, 2000: 146-148.
[16] Baum G. and beneking H., Drift velocity saturation in MOS transistor, IEEE Trans. ED, ED-17, 1970: 481-482.
[17] Frohman-Bentchkowsky D. and Grove A.S., Conductance of MOS transistors in saturation, IEEE Trans. ED, ED-17, 1965: 108-113.
[18] Banna M.E. and Nokali M.E., A pseudo-two-dimensional analysis of short channel MOSFETs, Solid-State Electron., Vol.31, 1988: 269-274.
[19] Liang M.S., Choi J.Y., Ko P.K., and Hu C.M., Inversion-layer capacitance and mobility of very thin gate oxide MOSFETs, IEEE Trans. ED, ED-33, 1986: 409-413.
[20] Arora N. D. and Gildenbalt G. Sh., A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation, IEEE Trans. ED, ED-34, 1987: 89-93.
[21] Wang P.P., Device characteristics of short-channel and narrow-width MOSFETs, IEEE Trans. ED, ED-25, 1978: 779-786.
[22] Risch L., Electron mobility in short-channel MOSFETs with series resistance, IEEE Trans., ED, ED-30, 1983: 959-961.
[23] N．Arora著，张兴等译，用于VLSI模拟的小尺寸MOS器件模型：理论与实践．科学出版社，北京，1999．
[1] Meyer J.E., MOS models and circuit simulation. RCA Review, Vol.32, 1971:42-63
[2] Pao H.C., Sah C.T., Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electronics, Vol. 9, 1966: 927-937
[3] Enz C.C., Krummenacher F., Vittoz E.A., An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage design and simulation. Low-Voltage Low-Power Devices, Vol.8, 1995: 83-114
[4] Lim K.M, Zhou X. A physically-based semi-empirical series resistance model for deep-submicron MOSFET Ⅰ-Ⅴ modeling. IEEE Trans. ED, Vol.47, No.6, 2000: 1300-1302.
[5] Mountain D. Application of electrical effective channel length and external resistance measurement techniques to a submicrometer CMOS process. 1EEE Trans. ED, Vol.36, No.11, 1989: 2499-2505.
[6] Zhou X., Lim. K.Y., and Lim D. A general approach to compact threshold voltage formulation based on 2-D numerical simulation and experimental correlation for deep-submicron ULSI technology development. IEEE Trans. ED, Vol.47, No. 1, 2000: 214-220.
[7] Biesemans S., Hendriks M., Kubicek S., et al. Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFET's. IEEE Trans. ED, Vol.45, No.6, 1998: 1310-1316.
[8] Chung S.S, Lee J.S. A new approach to determine the drain-and source series resistance of LDD MOSFET's. IEEE Trans. ED, Vol.40, No.9, 1993: 1709-1711.
[9] Niu G.F, Mathew S.J., Cressler J.D, et al. A novel channel resistance ratio method for effective channel length and series resistance extraction in MOSFETs. Solid State Electronics, (44), No.7, 2000:1187-1189.
[10] Taur Y., Zicherman D. S., Lombardi D. R., et al. A new "Shift and Ratio" method for MOSFET channel-length extraction, IEEE Electron Devices Lett., vol. 13, No.5,1992:267-269.
[11] Takeuchi K., Kasai N., Kunio T., and Terada K.. An effective channel length determination method for LDD MOSFET's, IEEE Trans Electron Devices, vol. 43, No.4, 1996:580-587.
[12] Niu G., Cressler J. D., Mathew S. J., and Subbanna S.. A total resistance slope-based effective channel mobility extraction method for deep submicrometer CMOS technology, IEEE Trans. Electron Devices, vol. 46, No.9, 1999:1912-1914.
[13] Lee S., and Yu H.K. A New Technique to Extract Channel Mobility in Submicron MOSFETs Using Inversion Charge Slope Obtained from Measured S-Parameters. IEEE Trans. Electron Devices, vol. 48, No.4, 2001:784-788.
[14] Curtice W.R., Ettenberg M.. A nonlinear GaAs FET model for use in the design of output circuits for power amplifiers. IEEE Trans. Microwave Theory and Techniques, 1985 , 33 (12):1383-1394
[15] Parker A.E., Skellern D.J.. A Realistic Large-Signal MESFET Model for SPICE. IEEE Trans. MTT, Vol.45, No.9, Sep. 1997:1563-1571
[16] Angolov I., Rorsman N., Stenarson J., et al. An Empirical Table Based FET Model. IEEE MTT-S Digest, 1999, 525-528
[17] Angelov I., Zirath H., Rorsman N., A New Empirical Nonlinear Model for HEMT and MESFET Devices. IEEE Trans. MTT, Vol.40, No. 12, Dec. 1992:2258-2266
[18] Zhou X., Lim. K.Y. Unified MOSFET compact I-V model formulation through physics-based effective transformation. IEEE Trans. ED, Vol.48, No.5, 2001: 887-896.
[19] Liu Z.H., Hu C.M., Huang J.H., et al. Threshold model for deep-submicron MOSFET's. IEEE Trans. ED, Vol.40, No.1, 1993: 86-95.
[20] Lou C.L., Chim W.K., Chan S.H., et al. A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot carrier degraded drain-engineered MOSFET's. IEEE Trans. ED, Vol.45, No.6, 1998: 1317-1323.
[21] Wright G.T.. physical and CAD model for the implanted-channel VLSI MOSFET, IEEE Trans. ED, Vol.34, 1987:823-833.
[22] Jang S.L., Liu S.S., and Sheu C.J.. A compact LDD MOSFET I-V model based on nonpinned surface potential. IEEE Trans. ED, Vol.45, No. 12, 1998: 2489-2498.
[23] Chan T.P., Ko P.K., Hu C.M.. Dependence of channel electric field on device scaling. IEEE EDL, Vol.EDL-6, No. 10, 1985: 551-554.
[24] Hu Y., Booth R.V.H., and white M.H.. An analytical model for the lateral channel electric field in LDD structures. IEEE Trans. ED, Vol.37, No. 12, 1990: 2254-2263.
[1] Chan T., Ko P., Hu C. A simple method to characterize substrate current in MOSFET's. IEEE EDL, Vol.EDL-5, No. 12, 1984: 505-507.
[2] Chan T.Y., Ko P.K., Hu C.M.. Dependence of channel electric field on device scaling. IEEE EDL, Vol.EDL-6, No. 10, 1985: 551-554.
[3] Arora N D and Sharma M S. MOSFET substrate current model for circuit simulation. IEEE Trans. ED, 38, No.6, 1991:1392-1398
[4] Tanizawa M., et al. A complete substrate current model including band-to-band tunneling current for circuit simulation. IEEE Trans. CAD of IC systems, Vol. 12, No. 11, 1993:1749-1757.
[5] Ramaswarny S., Amerasekera A Chang M. C. A unified substrate current model for weak and strong impact ionization in sub-0.25um NMOS devices. IEDM Tech. Dig., 1997:885-886.
[6] Li W., Yuan J.S. An improved substrate current model for deep submicron CMOS transistors. IEEE IRW Final Report, 2000:146-148.
[7] Liu Z.H., Hu C.M., Huang J.H., et al. Threshold model for deep-submicron MOSFET's. IEEE Trans. ED, Vol.40, No.1, 1993: 86-95.
[8] Chung J., Jeng M.C., May G., et al. Hot-electron currents in deep-submicrometer MOSFETs. IEEE IEDM-88, 1988:200-203.
[9] Huang G S and Wu C Y. An analytical saturation model for drain and substrate current of conventional and LDD MOSFET's. 1990 IEEE Trans. ED, 37, No.7, 1667-1677
[10] Yang J J, Chung S S, and Chou P C, et al. A New Approach to modeling the substrate current of Pre-stressed and Post-stressed MOSFET's. 1995 IEEE Trans. ED, 42, No.6, 1113-1119
[11] Hu Y, Booth R V H, and white M H. An analytical model for the lateral channel electric field in LDD structures. 1990 IEEE Trans. ED, 37, No. 10, 2254-2263
[12] Liu S S, Jang S L, and Chyau C G. Compact LDD nMOSFET Degradation Model. 1998 IEEE Trans .ED, 45,N0.7, 1538-547
[13] Jang S.L., Liu S.S., and Sheu C.J.. A compact LDD MOSFET I-V model based on nonpinned surface potential. IEEE Trans. ED, Vol.45, No.12, 1998: 2489-2498.
[1] Liu Z.H., Hu C.M., Huang J.H., et al. Threshold model for deep-submicron MOSFET's. IEEE Trans. ED, Vol.40, No.1, 1993: 86-95.
[2] A.Ortiz-Conde et al. New approach for defining the threshold voltage of MOSFETs. IEEE Trans. ED, Vol.48, No.4, 2001: 809-813.
[3] X. Zhou, K. Y. Lim, and D. Lim. A Simple and Unambiguous Definition of Threshold Voltage and Its Implications in Deep-Submicron MOS Device Modeling. IEEE Trans. ED, VOL. 46, NO. 4, 1999: 807-809
[4] Tsuno.M et al. Physically-based threshold voltage determination for MOSFETs of all gate lengths. IEEE ED, Vol.46, No.12, 1999: 1429-1434.
[5] Terada K. et al. Comparison of MOSFET-threshold-voltage extraction methods. Solid-State Electronics Vol.45, No.1, 2001: 35-40.
[6] Taur Y., MOSFET channel length: Extraction and interpretation, IEEE Trans. ED, Vol. 47, No.1, 2000:160-170.
[7] Hu GJ, Chang C, Chia Y-T. Gate-voltage-dependent effective channel length and series resistance of LDD MOSFETs. IEEE Trans Electron Dev 1987;34:2469-75.
[8] Lim KY, Zhou X. A physically-based semi-empirical series resistance model for deep-submicron MOSFET I-V modeling. IEEE Trans Electron Dev 2000;47:1300-2.
[9] Biesemans S, Hendriks M, Kubicek S, Meyer KD. Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFETs. IEEE Trans Electron Dev 1998;45(6): 1310-6.
[10] Lou C-L, Chim WK, Chan DDS, Pan Y. A novel single device DC method for extraction of the effective mobility and source-drain resistance of fresh and hot-carrier degraded drain-engineered MOSFETs. IEEE Trans Electron Dev 1998;45(6): 1317-23.
[11] Guo JC, Chung SS-S, Hsu CC-H. A new approach to determine the effective channel length and drain-and source series resistance of miniaturized MOSFETs. IEEE Trans Electron Dev 1987;41(10):1811-8.
[12] Ortiz-Conde A, Liou JJ, Wong W, Garcia Sanchez FJ. Simple method for extracting the difference between the drain and source series resistances in MOSFETs. Electron Letter 1994;30(6):1013-5.
[13] Raychaudhuri A, Kolk J, Deen MJ, King MIH. A simple method to extract the asymmetry in parasitic source and drain resistances from measurements on a MOS transistor. IEEE Trans Electron Dev 1995;42:1388-90.
[14] Jen SH-H, Enz CC, Pehlke DR, Schroter M, Sheu BJ. Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz. IEEE Trans Electron Dev 1999;46(11):2217-27.
[15] Lee S, Yu HK, Kim CS, Koo JG, Nam KS. A novel approach to extract small-signal model parameters of silicon MOSFETs. IEEE Microwave Guided Wave Letter 1997; 7(3):75-7.
[16] Lim GM, Kim YC, Park YW, Kim DJ, Kim DM. Additional resistance method for extraction of separated nonlinear parasitic resistances and effective mobility in MOSFETs. Electron Letter 2000;36:1233-4.
[17] Niu G.F., Cressler J.D., Mathew S.J., et al. A channel resistance derivative Method for effective channel length extraction in LDD MOSFETs. IEEE ED, Vol.47, NO.3, 2000:648-650.
[18] Lee S. H. and. Yu H.K, "A new technique to extraction channel mobility in submicron MOSFETs using inversion charge slope obtained from measured S-parameters", IEEE Trans. Electron Devices, Vol.48, pp.784-788, Apr. 2001
[19] Katto H., "Device parameters extraction in the linear region of MOSFET by comparing with the exact gradual channel model", Solid-State Electronics, Vol.44, pp.969-976, 2000
[1] Gesch H, Leburton JP, Dorda GE. Generation of inter-face states by hot hole injection in MOSFETs. IEEE Transactions Electron Devices 1982;ED-29:913.
[2] Ng KK, Taylor GW. Effects of hot-carrier trapping in n-and p-channel MOSFET's. IEEE Transactions Electron Devices 1983;ED-30:871.
[3] Takeda E, Suzuki N. An empirical model for device degradation due to hot-carrier injection. IEEE Electron Device Letters 1983;EDL-4:111.
[4] Takeda E, Shimizu A, Hagiwara T. Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFET's. IEEE Electron Device Letters 1983;EDL-4:329.
[5] Hu C, Tam SC, Hsu FC, Ko PK, Chan TY, Terrill KW. Hot-electron-induced MOSFET degradation- model, monitor, and improvement. IEEE Transactions Electron Devices 1985;ED-32:375.
[6] Tsuchiya T, Kobayashi T, Nakajima S. Hot-carrier-injected oxide region and hot-electron trapping as the main cause in Si nMOSFET degradation. IEEE Transactions Electron Devices 1987;ED-34:386.
[7] Schwerin A, Hansch W, Weber W. The relationship between oxide charge and device degradation: a comparative study of n- and p-channel MOSFET's. IEEE Transactions Electron Devices 1987;ED-34:2493.
[8] Heremans P, Bellens R, Groeseneken G, Maes HE. Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's. IEEE Transactions Electron Devices 1988;35:2194.
[9] Ogura S, et al. Design and characteristics of the lightly-doped drain-source (LDD) insulated gate FET. IEEE Transactions Electron Devices 1980;ED-27:1359.
[10] Tsang PJ, et al. Fabrication of high-performance LDD FETs with oxide sidewall spacer technology. IEEE Transactions Electron Devices 1982;ED-29:590.
[11] Huang TY, Yao WW, Martin A, Lewis AG, Koyanagi M, Chen JY. A new LDD Transistor with inverse-T gate structure. IEEE Electron Device Letters 1987.EDL-8:151.
[12] Izawa R, Kure T, Takeda E. Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI. IEEE Transactions Electron Devices 1988;35:2088.
[13] Hori T, Kurimoto K, Yabu T, Fuse G. A new submicron MOSFET with LATID (large-tilt-angle implanted drain) structure. In: Proceedings of VLSI Technology Symposium. 1988. p. 15.
[14] Matsuoka F, Kasai K, Oyamatsu H, Kinugawa M, Maeguchi K. Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET. IEEE Transactions Electron Devices 1994 ;41:420.
[15] Hsu FC, Grinolds HR. Structure-enhanced MOSFET degradation due to hot-electron injection. IEEE Electron Device Letters 1984;EDL-5:71.
[16] Hsu FC, Chiu KY. Evaluation of LDD MOSFET's based on hot-electron-induced degradation. IEEE Electron Device Letters 1984;EDL-5:162.
[17] Chung JE, Ko PK, and Hu C. A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation. IEEE Trans. Electron Devices 1991; 38: 1362.
[18] Cham K, Hui J, Voorde PV, Fu H. Self-limiting behavior of hot carrier degradation and its implication on the validity of lifetime extraction by accelerated stress. In: Proceedings of international Reliability Physics Symposium. 1987. p. 191.
[19] Sun SW, Orlowski M, Fu KY. Parameter correlation and modeling of the power-law relationship in MOSFET hot-carrier degradation. IEEE Electron Device Letters 1990; 11:297.
[20] Wang Q, Krautschneider WH, Brox M, Weber W. Time dependence of hot-carrier degradation in LDD nMOSFETs. Proceedings of Insulating Films on Semiconductors Conference. 1991: 441.
[21] Liang C, Gaw H, Cheng P. An analytical model for self-limiting behavior of hot-carrier degradation in 0.25-mm n-MOSFET's. IEEE Electron Device Letters1992; 13:569.
[22] Chan VH, Chung JE. Two-stage hot-carrier degradation and its impact on submicrometer LDD NMOSFET life-time prediction. IEEE Transactions Electron Devices 1995;42:957.
[23] Raychaudhuri A, Deen MJ, Kwan WS, King MIH. Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFET's. IEEE Transactions Electron Devices 1996;43:1114.
[24] Okhonin S, Hessler T, Dutoit M. Kinetics of hot-carrier degradation of submicron n-channel LDD MOSFET's. Proceedings of the European Solid State Device Research Conference. 1996:855.
[25] Ang DS, Ling CH. A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET's. IEEE Transactions Electron Devices 1998;45:149.
[26] Ang DS, Ling CH. A new assessment of the self-limiting hot-carrier degradation in LDD NMOSFET's by charge pumping measurement. IEEE Electron Device Letters 1997; 18(6):299.
[27] Goo JS, Shin H, Hwang H, Kang DG, Ju DH. Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain n-channel metal-oxide-semiconductor field effect transistors. Japanese Journal of Applied Physics 1994;33(1):606.
[28] Groeseneken G, Maes HE, Beltran N, Keersmaecker RF. A reliable approach to charge pumping measurement in MOS transistors. IEEE Transactions Electron Devices 1984;ED-31:42.
[29] Chen W, Balasinski A, Ma TP. Lateral profiling of oxide charge and interface traps near MOSFET junctions. IEEE Transactions Electron Devices 1993;40:187.
[30] Heremans P, Witters J, Groeseneken G, Maes HE. Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation. IEEE Transactions Electron Devices 1989;36:1318.
[31] Tsuchiaki M, Hara H, Morimoto T, Iwai H. A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFET's. IEEE Transactions Electron Devices 1993;40:1768.
[32] Ling CH, Tan SE, Ang DS. A study of hot-carrier degradation in NMOSFET's by gate capacitance and charge pumping current. IEEE Transactions Electron Devices 1995 ;42(7): 1321.
[33] Heremans P, Bellens R, Groeseneken G, Maes HE. Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's. IEEE Transactions Electron Devices 1998;35:2194.
[34] Doyle BS, Bourcerie M, Bergonzoni C, et al. The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot carrier stressing of NMOS transistors. IEEE Transactions Electron Devices 1990;37:1869.
[35] Mahapatra S, Parikh CD, Rao VR, et al. A comprehensive study of hot-carrier induced interface and oxide trap distribution in MOSFET's using a novel charge pumping technique. IEEE Transactions Electron Devices 2000;47:171.
[36] Lou CL, Chim WK, Chan DS H, Pan Y. A novel single device method for extraction of the effective mobility and source-drain resistance of fresh and hot-carrier degraded drain-engineered MOSFETs. IEEE Transactions Electron Devices 1998;45:1317.
[37] Chim WK, Leang SE, Chan DS H. Extraction of metal-oxide-semiconductor field-effect-transistor interface state and trapped charge spatial distribution using a physics-based algorithm. J Appl Phys 1997;81(4): 1992.
[38] Cheng SM, Yih CM, Yeh JC, et al. A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions. IEEE Transactions Electron Devices 1997;44(11):1908.
[39] Yeow YT, Ling CH, and Ah LK. Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement. IEEE Electron Device Lett 1991;12: 366.
[40] Ling CH, Yeow YT, and Ah LK. Characterization of charge trapping in submicrometer NMOSFET's by gate capacitance measurement. IEEE Electron Device Lett. 1992 ; 13: 587.
[41] Lee RGH, Su JS, and Chung SS. A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's. IEEE Trans. Electron Devices 1996; 43: 81.
[42] Chen W and Ma TP. A new technique for measuring lateral distribution of oxide charge and interface traps near MOSFET junctions. IEEE Electron Device Lett. 1991; 7: 393.
[43] Okhonin S, Hessler T, and Dutoit M. Comparison of gate-induced drain leakage and charge pumping measurements for determining lateral interface trap profiles in electrically stressed MOSFET's. IEEE Trans. Electron Devices 1996 ; 43: 605.
[44] Manhas SK, Sehkar DC, Oates AS, et al. Characterisation of series resistance degradation through charge pumping technique. Microelectronics reliab. 2003;43:617-624.
[45] Manchanda L, Storz RH, Yan RH, Lee KF, Westerwick EH. Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 lm Si MOSFETs. In: IEDM Tech Dig, 1992. p.994-996.
[46] Anil KG, Mahapatra S, Eisel I. Role of inversion layer quantization on sub-bandgap impact ionization in deepsubmicron n-channel MOSFETs. In: IEDM Tech Dig, 2000. p. 675-678.
[47] Saraya T, Takamiya M, Duyet TN, Tanaka T, Ishikuro H, Hiramoto T, et al. Floating body effects in 0.15 um partially depleted SOI MOSFETs below 1 V. Proc IEEE Int SOI Conf, 1996:70-71.
[48] Abramo A, Brunetti R, Jacaboni C, Venturi F, Sangiorgi E. A multiband Monte Carlo approach to Coulomb interaction for device analysis. J Appl Phys 1994;76(10): 5786-5794.
[49] Fischetti MV, Laux SE. Monte Carlo study of sub-bandgap impact ionization in small silicon field-effect transistors. In: IEDM Tech Dig, 1995. p. 305-308.
[50] Ghetti A, Selmi L, Bez R. Low-voltage hot electrons and soft-programming lifetime prediction in nonvolatile memory cells. IEEE Trans Electron Device 1999;46(4):696-702.
[51] Fischetti MV, Laux SE, Crabbe E. Understanding hotelectron transport in silicon devices: Is there a shortcut? J Appl Phys 1995;78(2): 1058-1086.
[52] Mietzner T, Jakumeit J, Ravaioli U. Local iterative Monte Carlo analysis of electron-electron interaction in shortchannel Si-MOSFETs. IEEE Trans Electron Device 2001; 48(10):2323-2330.
[53] King EE, Lacoe RC and Wang RJ. The role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices. International Reliability Physics Proceedings, 2000. p. 83-92.
[54] Ratkovic J W, Lacoe RC, Macwilliams KP, et al. New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures. International Reliability Physics Proceedings, 1997. p. 312-319.
[55] Su P, Goto K, Sugii T, and Hu C. Enhanced substrate current in SOI MOSFETs. IEEE Electron Device Lett. 2002; 23(5):282-284.
[56] Eitan B, Frohman-Bentchkowsky D, and Shappir J. Impact ionization at very low voltages in silicon. J. Appl. Phys. 1982; 53(2): 1244-1247.
[57] Esseni D, Selmi L, Sangiorgi E, Bez R, and Ricco B. Temperature dependence of gate and substrate currents in the CHE crossover regime. IEEE Electron Device Lett 1995; 16(11): 506-508.
[58] Sze S M. Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
[59] Taur Y and Ning T H. Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
[60] Fischetti M and Laux S. Monte Carlo study of sub-band-gap impact ionization in small silicon field-effect transistors, in IEDM Tech. Dig ,1995. p. 305-308.
[61] Sano N, Tomizawa M, and Yoshii A. Temperature dependence of hot carrier effects in short-channel Si-MOSFETs. IEEE Trans. Electron Devices, 1995;42(12): 2211-2211.
[62] Mastrapasqua M, Bude J, Pinto M, Manchanda L, and Lee K. Temperature and channel length dependence of impact ionization in P-channel MOSFETs. in Symp. VLSI Technol., 1994. p. 125-126.
[63] Tam S, Ko PK and Hu C. Lucky-electron model of channel hot electron injection in MOSFETs. IEEE Trans. Electron Devices, 1984, 31 (6): 1116
[64] Rauch S, Guarin F, and LaRosa G. Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs. IEEE Electron Device Lett., 1998;19(12): 463-465.
[65] Childs P and Leung C. A one-dimensional solution of the Boltzmann transport equation including electron-electron interactions. J. Appl. Phys., 1996;79(1):222-227.
[66] Chung J, Jeng MC, Moon J, Ko PK, and Hu C. Low-voltage hot electron currents and degradation in deep-submicrometer MOSFET's. IEEE Trans. Electron Devices, 1990;37(7):1651.
[67] Aur S. Low-voltage hot-carrier effects and stress methodology. Proc. Int. Symp. VLSI Technol., 1995:277
[68] Mizuno T, Toriumi A, Iwase M, et al. Hot-carrier effects in 0.1-μm gate length CMOS devices. IEDM Tech. Dig., 1992: 695
[69] Ellis-Monaghan J. J., Hulfachor R. B., Kim K. W., et al. Ensemble Monte Carlo study of interface-state generation in low voltage scaled silicon MOS devices. IEEE Trans. Electron Devices, 1996, 43(6): 1123
[70] Abramo A., Fiegna C, and Venturi F.. Hot-carrier effects in short MOSFETs at low applied voltages. IEDM Tech. Dig., 1995:301
[71] Bude J., Iizuka T., and Kamakura Y.. Determination of threshold energy for hot electron interface state generation. IEDM Tech. Dig., 1996: 865
[72] Childs P. and Leung C. New mechanism of hot-carrier generation in very short channel MOSFETs. Electron. Lett., 1995, 31(2): 139
[73] Lee S, Hwang JM, and Lee HD. Experimental evidence for nonlucky electron model effect in 0.15μm NMOSFETs. IEEE Trans. Electron Device,2002,49(11):1876
[74] Anil KG, Mahapatra S, Eisele I. Experimental verification of the high energy tail in the electron energy distribution in n-channel MOSFETs. IEEE Electron Device Lett 2001; 22(10):478-480.
[75] Anil KG, Mahapatra S, Eisele I. Electron-electron interaction signature peak in the substrate current vs gate voltage characteristics of n-channel silicon MOSFETs. IEEE Trans Electron Device 2002;49(7): 1283-1288.
[76] Anil KG, Mahapatra S, Eisele I. A detailed experimental investigation of impact ionization in n-channel metal -oxide-semiconductor field-effect-transistors at very low drain voltages. Solid-State Electronics 2003;47(6):995-1001.
[77] Su P, Goto KI, Sugii T, Hu C. A thermal activation view of low voltage impact ionization in MOSFETs. IEEE Electron Device Lett 2002; 23(9):550-552.
[78] Chen Z. et al. On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing. IEEE Electron Device Lett.,2000,21(1):24.
[79] Ang DS and Ling CH. On the Dominant interface trap generation process during hot-carrier stressing. Int. Reliability Physics Symp. Proa, 2001:412.
[80] Raychaudhuri A, Deen MJ, et al. A simple method to qualify the LDD structure against the early mode of hot-carrier degradation. IEEE Trans Electron Device 1996;43(1):110-115.