数字视频监控系统中信道编码系统的研究与设计
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摘要
当今通信应用领域,如何提高数据传输的速率和可靠性成为了越来越重要的研究方向。信道编码是指在信号传输过程中,通过使被传输信号更有效地承受各种各样的信道减损带来的影响,从而提高通信系统的性能。数字视频监控系统通常由摄像机等前端设备、传输系统和主控显示记录设备三大部分组成,随着电子和多媒体技术的发展,数字视频监控系统设备综合性能不断提高。本文介绍欧洲DVB标准的信道编码方案,同时设计了基于DVB-S的数字视音频监控系统。
本文首先详细介绍了数字电视的相关背景知识和标准。接着对截短信道外码RS码和内码卷积码的数学理论以及编解码的原理进行了详尽的分析。在编码输入块长度相同的前提下,RS码与其他线性码相比能获得最优的码距。卷积码被广泛运用于通信系统中,以提高数据在有噪信道中的传输可靠性。维特比于1967年发明了Viterbi译码器,作为卷积码的主要译码策略,Viterbi算法通常运用于卷积码译码。卷积码以其优异的性能,近年来广泛运用于深空通信以及无线通信中。WCDMA采用卷积码编码器将音频和MPEG-4视频信号进行编码,最大的编码速度为2Mbps。
最后提出了依据DVB-S标准的数字通信系统的设计,基于全集成压控振荡器(VCO) ADF4360-1芯片的本振源信号发生模块为系统中频发射机提供稳定的2.33GHz信号。本文利用QuartusⅡ开发工具和硬件描述语言Verilog,以Altera公司EP1C12Q240C8 FPGA芯片为载体,设计了基于改进BM算法的RS(204,188)译码器和基于Viterber最大似然译码算法的卷积码译码器。仿真结果表明模块的性能高效,频率可达50MHz,并且充分利用了FPGA硬件资源,功能和性能均达到了系统的要求。
Improving both the rate and the reliability of a data transfer is becoming more and more important issue in today's telecommunication applications. Channel coding refers to the class of signal transformations designed to improve communication performance by enabling the transmitted signals to better withstand the effects of various channel impairments.With the development of electronic and muti-media technology, the over-all performance of digital video monitoring system which is usually composed of front equipment transmission system and the main-control display device is enhanced. This paper introduces the channel coding scheme which is based on European DVB (Digital Video Broadcasting) standard and designs the digital video and audio monitor system.
In this thesis, the background and standards in detail of DTV(Digital Television) are firstly introduced. Secondly, the paper deals with shorten RS code which is the channel outer code of the DVB-S standard and convolutional code's encoding/decoding principle. Reed-Solomon codes achieve the largest possible code minimum distance for any linear code with the same encode input and output block length. Convolutional codes are widely used in telecommunication applications to improve the data transmission reliability over noisy channels. To decode convolutional codes, Andrew Viterbi invented the Viterbi Decoder(VD) in 1967, the main decoding strategy for convolutional codes, based on the Viterbi Algorithm, is used to decode convolutional codes. Convolutional coding is a coding scheme often employed in deep space communications and recently in digital wireless communications. WCDMA employs convolutional encoding to encode voice and MPEG4 applications in the base band transmitter at a maximum frequency of 2Mbps.
Finally, a design of digital communication system in accordance with DVB-S standard is proposed. The steady 2.33GHz local oscillator signal generator circuit module based on fully integrated voltage-controlled oscillator ADF4360-1 is applied to the system of intermediate frequency (IF). With the Quartus II development tool and Verilog hardware description language, the design of RS(204,188) decoder based on the improved BM algorithm and Viterbi Maximum Likelihood Decoding decoder are verified in EP1C12Q240C8 FPGA of Altera Corporation. The compiler result shows that the system is efficient, the frequency can reach to 50MHz, so function and performance of model meet the requirements of the system.
本文首先详细介绍了数字电视的相关背景知识和标准。接着对截短信道外码RS码和内码卷积码的数学理论以及编解码的原理进行了详尽的分析。在编码输入块长度相同的前提下,RS码与其他线性码相比能获得最优的码距。卷积码被广泛运用于通信系统中,以提高数据在有噪信道中的传输可靠性。维特比于1967年发明了Viterbi译码器,作为卷积码的主要译码策略,Viterbi算法通常运用于卷积码译码。卷积码以其优异的性能,近年来广泛运用于深空通信以及无线通信中。WCDMA采用卷积码编码器将音频和MPEG-4视频信号进行编码,最大的编码速度为2Mbps。
最后提出了依据DVB-S标准的数字通信系统的设计,基于全集成压控振荡器(VCO) ADF4360-1芯片的本振源信号发生模块为系统中频发射机提供稳定的2.33GHz信号。本文利用QuartusⅡ开发工具和硬件描述语言Verilog,以Altera公司EP1C12Q240C8 FPGA芯片为载体,设计了基于改进BM算法的RS(204,188)译码器和基于Viterber最大似然译码算法的卷积码译码器。仿真结果表明模块的性能高效,频率可达50MHz,并且充分利用了FPGA硬件资源,功能和性能均达到了系统的要求。
Improving both the rate and the reliability of a data transfer is becoming more and more important issue in today's telecommunication applications. Channel coding refers to the class of signal transformations designed to improve communication performance by enabling the transmitted signals to better withstand the effects of various channel impairments.With the development of electronic and muti-media technology, the over-all performance of digital video monitoring system which is usually composed of front equipment transmission system and the main-control display device is enhanced. This paper introduces the channel coding scheme which is based on European DVB (Digital Video Broadcasting) standard and designs the digital video and audio monitor system.
In this thesis, the background and standards in detail of DTV(Digital Television) are firstly introduced. Secondly, the paper deals with shorten RS code which is the channel outer code of the DVB-S standard and convolutional code's encoding/decoding principle. Reed-Solomon codes achieve the largest possible code minimum distance for any linear code with the same encode input and output block length. Convolutional codes are widely used in telecommunication applications to improve the data transmission reliability over noisy channels. To decode convolutional codes, Andrew Viterbi invented the Viterbi Decoder(VD) in 1967, the main decoding strategy for convolutional codes, based on the Viterbi Algorithm, is used to decode convolutional codes. Convolutional coding is a coding scheme often employed in deep space communications and recently in digital wireless communications. WCDMA employs convolutional encoding to encode voice and MPEG4 applications in the base band transmitter at a maximum frequency of 2Mbps.
Finally, a design of digital communication system in accordance with DVB-S standard is proposed. The steady 2.33GHz local oscillator signal generator circuit module based on fully integrated voltage-controlled oscillator ADF4360-1 is applied to the system of intermediate frequency (IF). With the Quartus II development tool and Verilog hardware description language, the design of RS(204,188) decoder based on the improved BM algorithm and Viterbi Maximum Likelihood Decoding decoder are verified in EP1C12Q240C8 FPGA of Altera Corporation. The compiler result shows that the system is efficient, the frequency can reach to 50MHz, so function and performance of model meet the requirements of the system.
引文
[1]余兆明,余智.数字电视基础[M].西安：西安电子科技大学出版社,2009：38-39
[2]鲁业频.数字电视原理[M].北京：电子工业出版社,2002：5-10
[3]赵坚勇,周琼鉴.数字电视技术[M].西安：西安电子科技大学出版社,2005：122-152.
[4]ETSI. Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television[J]. ETSI EN 300744 vl.4.1,2001:9-12
[5]Lajos Hanzo, Peter J. Cherriman and Jurgen Streit. Wireless Video Communications: Second to Third Generation System and Beyond[J]. USA New York:IEEE Press,2001.
[6]王育民,梁传甲.信息与编码理论[M].西北电讯工程学院,1986.
[7]C. E. Shannon, Mathematical Theory of Communication[J]. B. S. T. J. Vol.27 Part I: July 1948, Part II:Oct.1948:379-423
[8]D. J. Costello, Jr. J. Hagenaeur, H. Imai,and S. B. Wicker. Applications of error-control coding[J]. IEEE Trans. Inform. Theory. Oct.1998,44(6):2531-2560
[9]R.W.Hamming. Error detecting and error correcting codes[J]. Bell Syst. Tech. J.1950,26(2):147-150
[10]C. Berrou, A. Glavieux, and P. Thitimajshima. Near Shannon limit error-correcting coding and decoding:Turbo codes[J]. in Proc.1993 IEEE Int. Communications Conf. (Geneva, Switzerl and, May 1993)May.1993:1064-1070
[11]C.Berrou and A.Glavieux. Near Optimum Error Correcting Coding and Decoding: Turbo-Codes[J]. IEEE Trans. On Communications, October 1996,44(10):1261-1271
[12]曹志刚,钱亚生.现代通信原理[M].北京：清华大学出版社,1992：322-325
[13]ISO/EC 13818-1. INFORMATIOAN TECHNOLOGY GENERIC CODING OF MOVING PICTURES AND ASSOCIATED AUDIO:SYSTEM,1994[Z].
[14]ETSI:Digital Video Broadcasting(DVB); Framing structure, channel coding and modulation for 11/12 GHz satellite services 1997-08[Z].
[15]井小沛,武斌,张青春.基于FPGA的卷积码的编/译码器设计[J].电子测量技术,2008,31(2)：116-118.
[16](美)Jerry Whitaker数字电视接收技术[M].北京：电子工业出版社,2003：150-164
[17]张宗橙.纠错编码原理和应用[M].北京：电子工业出版社,2005：37-38.
[18]P.Elias, "Coding for noisy channels" [J].IREConv. Rec., pt. IV, pp.37-46,1955.
[19]王新梅,肖国镇.纠错码-原理与方法[M].西安：西安电子科技大学出版社,2003：410-411.
[20]Mason and H. Zimmermann, Electronic Circuits, Signals, and Systems[J]. Wiley, New York,1960.
[21]Conan, "The weight spectra of some short low-rate convolutional codes", IEEE Trans[J]. On Commun, No.9, pp.1984:1050-1053
[22]J. M. Wozencraft. Sequential decoding for reliable communications[J]. IRE National Convention Record,1957,5(2):11-25.
[23]R. M. Fano. A heuristic discussion of probabilistic decoding[J]. IEEE T-IT, 1963,9:No.4,64-74.
[24]Forney, G. D., Jr., and Bower, E. K., "A High Speed sequential decoder:prototype design and test" [J]. IEEE Trans. Commun. Technol., vol. COM19, no.5, Oct.1971, pp.821-835.
[25]A. J. Viterbi. Error bounds for convolutional codes and a asymptotically optimum decoding algorithm[J]. IEEE Trans. on Commun.,1967,13:No.2,260-269
[26]STEL-2020 datasheet[Z]. www.alldatasheet.com
[27]刘东华.Turbo码原理与应用技术[M].北京：电子工业出版社,2004年.20-59
[28]钟福元.最佳1/2卷积码VITERBI译码算法的简化[J].成都：电子科技大学学报,1989,3(18)：244-248
[29]Analog Devices. Integrated Synthesizer and VCO ADF4360_1 datasheet[Z].2004
[30]赵浩平,刘乃安.锁相频率合成器ADF4360_4及其在WLAN混频电路中的应用[J].国外电子元器件,2007(10)：22-25.
[31]田耀贵等.利用ADF4113设计数字锁相式频率源[J].无线电工程,2004,34(2)：50-51.
[32]李丹,刘宏立.锁相频率合成芯片ADF4360_1及其在射频发射机中的应用[J].仪器仪表用户,2006(13)：96-98.
[33]郑秀文,唐小宏.可用于频率合成的高性能锁相芯片ADF4113[J]国外电子元器件,2005(4)：68-70.
[34]Altera Corporation. QuartusⅡ handbook version 8.1[Z].2008
[35]刘波.精通Verilog HDL语言编程[M].北京：电子工业出版社.2007
[36]李晓刚,蔡德林.2,1,7卷积码Viterbi译码器的一种设计方案[J].信息技术,2008(1)：41-44
[37]王栋良,秦建存Viterbi译码的FPGA免回溯实现[J].无线电工程,2007,4(37)：27-29
[38]P.-N.Chen and F. Alajaji, Optimistic Shannon Coding Theorems for Arbitrary Single-User Systems[J], IEEE Trans. Inform. Theory,1999,45(7):2623-2629
[39]T.S.Han, Information-Spectrum Methods in Information Theory[J], New York, Springer-Verlag,2003
[40]Yangfan Zhong, Fady Alajaji, and L. Lome Campbell, On the Joint Source Channel Coding Error Exponent for Discrete Memoryless Systems[J],2006,52(4):1450-1468
[41]罗新民等.现代通信原理[M].北京：高等教育出版社.2003：394-395
[42]J. Hellerandl. Jacobs, "Viterbi decoding for satellite and space communication, " IEEE Transactions on Communication Technology [J], vol.COM-19, no.5, pp. Oct.1971: 835-848.
[43]G.Forney, "The viterbi algorithm," [J]. Proceedings of the IEEE, vol.61, no.3, pp. March 1973:268-278.
[44]J.Ryu, S.Kim, J. Cho, H. Park, and Y. Y.H.Chang, "Lower power viterbi Decoder architecture with an ewclock-gatingtrace-backunit, " [J]. Proc.6th International Conferenceon VLSI and CAD, Oct.1999:297-300.
[45]S. B. Wicker, Error Control Systems for Digital Communication and Storage[J]. Prentice Hall,1995.
[46]H.-D. LinandD. Messerschmitt, "Algorithms and architectures for concurrent Viterbi decoding," [J]. Proc. IEEE International Conference on Communications, June 1989:836-840.
[47]P. BlackandT.-Y. Meng, "A 140Mb/s 32-state radix-4 viterbi decoder," [J]. IEEE Journal of Solid-State Circuits, vol.27, no.12,.December 1992:1877-1885.
[48]A. YeungandJ. Rabaey, "A 210Mb/s radix-4 bit-level pipelined viterbi decoder, " [J]. Digest of Technical Papers, Proc. International Sol id-State Circuits Conference, February 1995.
[49]P. BlackandT.-Y. Meng, "A 1-gb/s, four-state, sliding block viterbi decoder," [J].IEEE Journal of Solid-State Circuits, vol.32, no.6, June,1997:797-805.
[50]K. PageandP. Chau, "Improved architectures for the add-compare-select operation in long constraint length viterbi decoding, " [J]. IEEE Journal of Solid-State Circuits, vol.33,no.1, January 1998:151-155,.
[51]C.-Y. Tsui, R.-K. Cheng, andC. Ling, "Lowpower acs unit design for the viterbi decoder, " [J]. Proc. IEEE International Symposiumon Circuits and Systems,1999: 137-140.
[52]A.Viterbi, "Error bounds for convolutional codes and asymptotically optimum decoding algorithm, "[J]. IEEE Transactions on Information theory, vol. It-13, no.2, April 1967:260-269.
[2]鲁业频.数字电视原理[M].北京：电子工业出版社,2002：5-10
[3]赵坚勇,周琼鉴.数字电视技术[M].西安：西安电子科技大学出版社,2005：122-152.
[4]ETSI. Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television[J]. ETSI EN 300744 vl.4.1,2001:9-12
[5]Lajos Hanzo, Peter J. Cherriman and Jurgen Streit. Wireless Video Communications: Second to Third Generation System and Beyond[J]. USA New York:IEEE Press,2001.
[6]王育民,梁传甲.信息与编码理论[M].西北电讯工程学院,1986.
[7]C. E. Shannon, Mathematical Theory of Communication[J]. B. S. T. J. Vol.27 Part I: July 1948, Part II:Oct.1948:379-423
[8]D. J. Costello, Jr. J. Hagenaeur, H. Imai,and S. B. Wicker. Applications of error-control coding[J]. IEEE Trans. Inform. Theory. Oct.1998,44(6):2531-2560
[9]R.W.Hamming. Error detecting and error correcting codes[J]. Bell Syst. Tech. J.1950,26(2):147-150
[10]C. Berrou, A. Glavieux, and P. Thitimajshima. Near Shannon limit error-correcting coding and decoding:Turbo codes[J]. in Proc.1993 IEEE Int. Communications Conf. (Geneva, Switzerl and, May 1993)May.1993:1064-1070
[11]C.Berrou and A.Glavieux. Near Optimum Error Correcting Coding and Decoding: Turbo-Codes[J]. IEEE Trans. On Communications, October 1996,44(10):1261-1271
[12]曹志刚,钱亚生.现代通信原理[M].北京：清华大学出版社,1992：322-325
[13]ISO/EC 13818-1. INFORMATIOAN TECHNOLOGY GENERIC CODING OF MOVING PICTURES AND ASSOCIATED AUDIO:SYSTEM,1994[Z].
[14]ETSI:Digital Video Broadcasting(DVB); Framing structure, channel coding and modulation for 11/12 GHz satellite services 1997-08[Z].
[15]井小沛,武斌,张青春.基于FPGA的卷积码的编/译码器设计[J].电子测量技术,2008,31(2)：116-118.
[16](美)Jerry Whitaker数字电视接收技术[M].北京：电子工业出版社,2003：150-164
[17]张宗橙.纠错编码原理和应用[M].北京：电子工业出版社,2005：37-38.
[18]P.Elias, "Coding for noisy channels" [J].IREConv. Rec., pt. IV, pp.37-46,1955.
[19]王新梅,肖国镇.纠错码-原理与方法[M].西安：西安电子科技大学出版社,2003：410-411.
[20]Mason and H. Zimmermann, Electronic Circuits, Signals, and Systems[J]. Wiley, New York,1960.
[21]Conan, "The weight spectra of some short low-rate convolutional codes", IEEE Trans[J]. On Commun, No.9, pp.1984:1050-1053
[22]J. M. Wozencraft. Sequential decoding for reliable communications[J]. IRE National Convention Record,1957,5(2):11-25.
[23]R. M. Fano. A heuristic discussion of probabilistic decoding[J]. IEEE T-IT, 1963,9:No.4,64-74.
[24]Forney, G. D., Jr., and Bower, E. K., "A High Speed sequential decoder:prototype design and test" [J]. IEEE Trans. Commun. Technol., vol. COM19, no.5, Oct.1971, pp.821-835.
[25]A. J. Viterbi. Error bounds for convolutional codes and a asymptotically optimum decoding algorithm[J]. IEEE Trans. on Commun.,1967,13:No.2,260-269
[26]STEL-2020 datasheet[Z]. www.alldatasheet.com
[27]刘东华.Turbo码原理与应用技术[M].北京：电子工业出版社,2004年.20-59
[28]钟福元.最佳1/2卷积码VITERBI译码算法的简化[J].成都：电子科技大学学报,1989,3(18)：244-248
[29]Analog Devices. Integrated Synthesizer and VCO ADF4360_1 datasheet[Z].2004
[30]赵浩平,刘乃安.锁相频率合成器ADF4360_4及其在WLAN混频电路中的应用[J].国外电子元器件,2007(10)：22-25.
[31]田耀贵等.利用ADF4113设计数字锁相式频率源[J].无线电工程,2004,34(2)：50-51.
[32]李丹,刘宏立.锁相频率合成芯片ADF4360_1及其在射频发射机中的应用[J].仪器仪表用户,2006(13)：96-98.
[33]郑秀文,唐小宏.可用于频率合成的高性能锁相芯片ADF4113[J]国外电子元器件,2005(4)：68-70.
[34]Altera Corporation. QuartusⅡ handbook version 8.1[Z].2008
[35]刘波.精通Verilog HDL语言编程[M].北京：电子工业出版社.2007
[36]李晓刚,蔡德林.2,1,7卷积码Viterbi译码器的一种设计方案[J].信息技术,2008(1)：41-44
[37]王栋良,秦建存Viterbi译码的FPGA免回溯实现[J].无线电工程,2007,4(37)：27-29
[38]P.-N.Chen and F. Alajaji, Optimistic Shannon Coding Theorems for Arbitrary Single-User Systems[J], IEEE Trans. Inform. Theory,1999,45(7):2623-2629
[39]T.S.Han, Information-Spectrum Methods in Information Theory[J], New York, Springer-Verlag,2003
[40]Yangfan Zhong, Fady Alajaji, and L. Lome Campbell, On the Joint Source Channel Coding Error Exponent for Discrete Memoryless Systems[J],2006,52(4):1450-1468
[41]罗新民等.现代通信原理[M].北京：高等教育出版社.2003：394-395
[42]J. Hellerandl. Jacobs, "Viterbi decoding for satellite and space communication, " IEEE Transactions on Communication Technology [J], vol.COM-19, no.5, pp. Oct.1971: 835-848.
[43]G.Forney, "The viterbi algorithm," [J]. Proceedings of the IEEE, vol.61, no.3, pp. March 1973:268-278.
[44]J.Ryu, S.Kim, J. Cho, H. Park, and Y. Y.H.Chang, "Lower power viterbi Decoder architecture with an ewclock-gatingtrace-backunit, " [J]. Proc.6th International Conferenceon VLSI and CAD, Oct.1999:297-300.
[45]S. B. Wicker, Error Control Systems for Digital Communication and Storage[J]. Prentice Hall,1995.
[46]H.-D. LinandD. Messerschmitt, "Algorithms and architectures for concurrent Viterbi decoding," [J]. Proc. IEEE International Conference on Communications, June 1989:836-840.
[47]P. BlackandT.-Y. Meng, "A 140Mb/s 32-state radix-4 viterbi decoder," [J]. IEEE Journal of Solid-State Circuits, vol.27, no.12,.December 1992:1877-1885.
[48]A. YeungandJ. Rabaey, "A 210Mb/s radix-4 bit-level pipelined viterbi decoder, " [J]. Digest of Technical Papers, Proc. International Sol id-State Circuits Conference, February 1995.
[49]P. BlackandT.-Y. Meng, "A 1-gb/s, four-state, sliding block viterbi decoder," [J].IEEE Journal of Solid-State Circuits, vol.32, no.6, June,1997:797-805.
[50]K. PageandP. Chau, "Improved architectures for the add-compare-select operation in long constraint length viterbi decoding, " [J]. IEEE Journal of Solid-State Circuits, vol.33,no.1, January 1998:151-155,.
[51]C.-Y. Tsui, R.-K. Cheng, andC. Ling, "Lowpower acs unit design for the viterbi decoder, " [J]. Proc. IEEE International Symposiumon Circuits and Systems,1999: 137-140.
[52]A.Viterbi, "Error bounds for convolutional codes and asymptotically optimum decoding algorithm, "[J]. IEEE Transactions on Information theory, vol. It-13, no.2, April 1967:260-269.