数字电路老化失效预测与防护技术研究
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摘要
工艺尺寸的急剧缩小,使得数字电路的性能得到了大幅度的提高。但是与此同时,也给数字电路的可靠性问题带了更多新的挑战。纳米工艺条件下,老化是影响数字电路可靠性的主要问题之一。老化会导致晶体管阈值电压升高,逻辑门单元翻转速度减慢,电路时延增大,导致时序违例的发生,最终引发电路失效。已有统计表明,老化会在10年内使数字电路的工作速度最多降低20%。
本论文针对数字电路老化失效预测与防护技术进行研究,分别在电路老化关键路径选择、老化失效在线预测、老化过程度量和老化失效防护问题上提出了相应的解决方法。具体内容和主要创新点如下：
(1)基于信号翻转概率的数字电路老化关键路径分析。数字电路中不同路径的老化过程并不相同,只有某些关键路径在老化效应的影响下才会发生时序违例,并最终引起电路失效。传统的老化关键路径选择方法无法有效的缩小关键路径集合规模。本文针对数字电路老化关键选择问题进行研究,提出了基于信号翻转概率的数字电路老化关键路径选择方法。本方法综合考虑电路逻辑门的信号翻转概率,计算电路中工作负载占空比的变化过程；并根据变化的工作负载占空比来计算电路的老化时延,进行老化关键路径的选择。实验数据表明,本文的方法能有准确的反应出电路中数据通路的时延变化过程,有效的缩小了关键路径集合的规模。
(2)基于双沿采样的数字电路老化失效在线预测。老化效应在电路层的特征表现为路径时延的增加。通过对数字电路信号的在线测试和分析,能够有效预测电路是否即将因老化而引起错误的发生。优化的在线预测电路设计是数字电路老化预测的关键问题。本文针对数字电路在线预测进行研究,提出了基于双沿采样的数字电路老化失效在线预测方法。本方法在老化故障模型分析的基础上,针对电路层老化特征,采用双沿触发器作为aging sensor的数据采样和存储单元,使用电路组合逻辑的输出信号作为检测电路的时序控制信号,利用触发器的建立时间产生预测窗口,通过分析aging sensor的采样结果来预测电路的老化情况。仿真实验表明,本文的在线预测方法在保持准确预测电路的老化失效功能的前提下,对工艺偏差影响具有很好的容忍性；同时,本方法还具有低功耗、低面积开销和低性能影响的优点,有效的解决了数字电路老化在线预测电路的综合优化设计问题。
(3)基于自振荡回路的数字电路老化度量。数字电路的实际老化程度是进行电路失效防护方法的依据,准确的评估电路老化过程是电路老化失效防护的关键。传统的评估方法不能准确的反映出电路的实际老化程度。本文针对数字老化评估问题,提出了基于自振荡回路的数字电路老化度量方法。本方法选择电路中的老化敏感特征通路作为待测路径；保持待测路径上具有奇数次“逻辑非”操作,利用待测路径自身结构形成自振荡回路；通过复用内建自测试机制实现老化测试向量的生成和自振荡回路的激发；采用老化特征计数器捕获量化老化特征值,度量老化程度。实验数据表明,本方法的老化度量准确度均达到90%以上,并具有很好的工艺偏差容忍能力。
(4)基于时-空冗余的数字电路老化失效防护。数字电路老化容忍技术的最终目的是为了防止老化引起电路失效的发生。现有的电路老化失效防护方法会永久性的改变电路原有结构和性能。本文针对数字电路的老化失效防护技术进行研究,提出了基于时-空冗余的数字电路老化失效防护机制。本失效防护机制采用冗余的空间单元检测电路中是否出现由老化所导致的错误,采用冗余的时序信号对电路的错误信号进行纠错处理,从而使电路具有了容老化的自检测和自纠错功能；同时,本防护机制在每次进行纠错处理后,统一调整电路的时钟相位,保证电路时钟的一致性。实验数据表明,本防护机制在时钟相位差分别为时钟周期的5%、10%、20%、25%时,可以分别提高2%、23%、116%、232%的电路平均故障间隔时间。
The aggressive scaling down technology has largely improved the performance of digital circuits. However, it has brought more challenges to the reliability of circuits in nanometer technology, one of which is the effect of circuit aging. The circuit aging would increase the transistor threshed voltage, decrease the speed of gate, increase the circuit delay, cause the timing violation and eventually lead to the circuit failure. Previous works show that the aging would lead to a20%degradation of circuit performance in10years.
This dissertation focuses on the aging failure prediction and protection of digital circuits and introduces the related methods to solve the problems caused by circuit aging. The main contributions of the dissertation are as follows:
(1) The Critical Path Selecting of Digital Circuits based on Transition Probability of Signal. In the digital circuits, the aging process of each data path is difference with each other. The timing violation only occurs in some critical data path under the influence of circuit aging. The previous woks could not scale the set of critical path effectively. A critical path selecting method is introduced in this work. In the circuits, each type of gate has its own signal transition probability, so that the duty cycles of them are different from each other. This selecting method makes use of the signal transition probability to compute the duty cycle of workload on data path, base on which the variation of circuit delay during the whole process of circuit aging is described as well. And finally, according to the aging delay of data path, the set of critical path is generated. The experiment results show that the proposed delay computing method could describe the variation of circuit delay precisely the change of circuit delay, and the critical path selecting method could reduce the set of critical path effectively.
(2) The Aging Failure Prediction for Digital Circuits using Double Triggered Pattern. In circuit level, the feather of aging is the increasing of circuit delay on data path. The online testing of circuits could effectively prediction the failure caused by circuit aging. The critical technology of online failure prediction is the optimized design of aging sensor. An online aging failure prediction method using double triggered pattern is proposed in this dissertation. Based on the analysis of aging feathers, this method employs the double-edge-triggered flip-flop to sample the signal of the circuits, and it use signal of the combinational logic to control the sampling process of aging sensor. The detection interval is generated by the setup time of different flip-flops, which is used to predict whether the error caused by circuit aging would occur. The experiment results show that this method would effectively predict the circuit failure, the influence of process variation on the proposed method is low, and it also make a low area, power and performance cost of circuits.
(3) The In-field Circuit Aging Measurement using Self-oscillation Loops. The precise measurement of circuit aging is critical to the implement of specific aging protection method. The traditional aging measurement method could not compute the aging process effectively. In this dissertation, an aging measurement method using self-oscillation loops is presented. This method selects critical path from circuits; keeps the odd times of inverters on the path and construct the self-oscillation loops by the interior devices of the critical path; reuses the mechanism of built-in self test to generate the testing patterns and agitate the self-oscillation loops; employs the aging signature counter to quantify aging feature and measure the aging process. The simulation results show that the measurement precise of proposed method is more than90%, and the method is resilient to the effect of process variation.
(4) The Aging Failure Protection for Digital Circuits using Time-Space Redundancy. The motivation of aging resilient is to protect the digital circuits from failure. The traditional circuit protection methods would permanently modify the structure and the performance of circuits. In this dissertation, an aging protection mechanism using time-space redundancy is proposed. This mechanism employs the redundant space cells to realize the self-detection process of circuits, and employ multi-timing signals to correct the error caused by circuit aging. After each time of error correction, the protection mechanism would make use of self-adaptive clock scaling cell to shift the clock difference, in order to keep the consistency of all the clock of circuits. The experiments show that this protection would improve the Mean Time-to-Failure by2%,23%,116%, and232%with the clock difference of5%,10%,20%, and25%.
本论文针对数字电路老化失效预测与防护技术进行研究,分别在电路老化关键路径选择、老化失效在线预测、老化过程度量和老化失效防护问题上提出了相应的解决方法。具体内容和主要创新点如下：
(1)基于信号翻转概率的数字电路老化关键路径分析。数字电路中不同路径的老化过程并不相同,只有某些关键路径在老化效应的影响下才会发生时序违例,并最终引起电路失效。传统的老化关键路径选择方法无法有效的缩小关键路径集合规模。本文针对数字电路老化关键选择问题进行研究,提出了基于信号翻转概率的数字电路老化关键路径选择方法。本方法综合考虑电路逻辑门的信号翻转概率,计算电路中工作负载占空比的变化过程；并根据变化的工作负载占空比来计算电路的老化时延,进行老化关键路径的选择。实验数据表明,本文的方法能有准确的反应出电路中数据通路的时延变化过程,有效的缩小了关键路径集合的规模。
(2)基于双沿采样的数字电路老化失效在线预测。老化效应在电路层的特征表现为路径时延的增加。通过对数字电路信号的在线测试和分析,能够有效预测电路是否即将因老化而引起错误的发生。优化的在线预测电路设计是数字电路老化预测的关键问题。本文针对数字电路在线预测进行研究,提出了基于双沿采样的数字电路老化失效在线预测方法。本方法在老化故障模型分析的基础上,针对电路层老化特征,采用双沿触发器作为aging sensor的数据采样和存储单元,使用电路组合逻辑的输出信号作为检测电路的时序控制信号,利用触发器的建立时间产生预测窗口,通过分析aging sensor的采样结果来预测电路的老化情况。仿真实验表明,本文的在线预测方法在保持准确预测电路的老化失效功能的前提下,对工艺偏差影响具有很好的容忍性；同时,本方法还具有低功耗、低面积开销和低性能影响的优点,有效的解决了数字电路老化在线预测电路的综合优化设计问题。
(3)基于自振荡回路的数字电路老化度量。数字电路的实际老化程度是进行电路失效防护方法的依据,准确的评估电路老化过程是电路老化失效防护的关键。传统的评估方法不能准确的反映出电路的实际老化程度。本文针对数字老化评估问题,提出了基于自振荡回路的数字电路老化度量方法。本方法选择电路中的老化敏感特征通路作为待测路径；保持待测路径上具有奇数次“逻辑非”操作,利用待测路径自身结构形成自振荡回路；通过复用内建自测试机制实现老化测试向量的生成和自振荡回路的激发；采用老化特征计数器捕获量化老化特征值,度量老化程度。实验数据表明,本方法的老化度量准确度均达到90%以上,并具有很好的工艺偏差容忍能力。
(4)基于时-空冗余的数字电路老化失效防护。数字电路老化容忍技术的最终目的是为了防止老化引起电路失效的发生。现有的电路老化失效防护方法会永久性的改变电路原有结构和性能。本文针对数字电路的老化失效防护技术进行研究,提出了基于时-空冗余的数字电路老化失效防护机制。本失效防护机制采用冗余的空间单元检测电路中是否出现由老化所导致的错误,采用冗余的时序信号对电路的错误信号进行纠错处理,从而使电路具有了容老化的自检测和自纠错功能；同时,本防护机制在每次进行纠错处理后,统一调整电路的时钟相位,保证电路时钟的一致性。实验数据表明,本防护机制在时钟相位差分别为时钟周期的5%、10%、20%、25%时,可以分别提高2%、23%、116%、232%的电路平均故障间隔时间。
The aggressive scaling down technology has largely improved the performance of digital circuits. However, it has brought more challenges to the reliability of circuits in nanometer technology, one of which is the effect of circuit aging. The circuit aging would increase the transistor threshed voltage, decrease the speed of gate, increase the circuit delay, cause the timing violation and eventually lead to the circuit failure. Previous works show that the aging would lead to a20%degradation of circuit performance in10years.
This dissertation focuses on the aging failure prediction and protection of digital circuits and introduces the related methods to solve the problems caused by circuit aging. The main contributions of the dissertation are as follows:
(1) The Critical Path Selecting of Digital Circuits based on Transition Probability of Signal. In the digital circuits, the aging process of each data path is difference with each other. The timing violation only occurs in some critical data path under the influence of circuit aging. The previous woks could not scale the set of critical path effectively. A critical path selecting method is introduced in this work. In the circuits, each type of gate has its own signal transition probability, so that the duty cycles of them are different from each other. This selecting method makes use of the signal transition probability to compute the duty cycle of workload on data path, base on which the variation of circuit delay during the whole process of circuit aging is described as well. And finally, according to the aging delay of data path, the set of critical path is generated. The experiment results show that the proposed delay computing method could describe the variation of circuit delay precisely the change of circuit delay, and the critical path selecting method could reduce the set of critical path effectively.
(2) The Aging Failure Prediction for Digital Circuits using Double Triggered Pattern. In circuit level, the feather of aging is the increasing of circuit delay on data path. The online testing of circuits could effectively prediction the failure caused by circuit aging. The critical technology of online failure prediction is the optimized design of aging sensor. An online aging failure prediction method using double triggered pattern is proposed in this dissertation. Based on the analysis of aging feathers, this method employs the double-edge-triggered flip-flop to sample the signal of the circuits, and it use signal of the combinational logic to control the sampling process of aging sensor. The detection interval is generated by the setup time of different flip-flops, which is used to predict whether the error caused by circuit aging would occur. The experiment results show that this method would effectively predict the circuit failure, the influence of process variation on the proposed method is low, and it also make a low area, power and performance cost of circuits.
(3) The In-field Circuit Aging Measurement using Self-oscillation Loops. The precise measurement of circuit aging is critical to the implement of specific aging protection method. The traditional aging measurement method could not compute the aging process effectively. In this dissertation, an aging measurement method using self-oscillation loops is presented. This method selects critical path from circuits; keeps the odd times of inverters on the path and construct the self-oscillation loops by the interior devices of the critical path; reuses the mechanism of built-in self test to generate the testing patterns and agitate the self-oscillation loops; employs the aging signature counter to quantify aging feature and measure the aging process. The simulation results show that the measurement precise of proposed method is more than90%, and the method is resilient to the effect of process variation.
(4) The Aging Failure Protection for Digital Circuits using Time-Space Redundancy. The motivation of aging resilient is to protect the digital circuits from failure. The traditional circuit protection methods would permanently modify the structure and the performance of circuits. In this dissertation, an aging protection mechanism using time-space redundancy is proposed. This mechanism employs the redundant space cells to realize the self-detection process of circuits, and employ multi-timing signals to correct the error caused by circuit aging. After each time of error correction, the protection mechanism would make use of self-adaptive clock scaling cell to shift the clock difference, in order to keep the consistency of all the clock of circuits. The experiments show that this protection would improve the Mean Time-to-Failure by2%,23%,116%, and232%with the clock difference of5%,10%,20%, and25%.
引文
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