电能计量的低功耗集成电路实现及采样方法研究
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摘要
降低电能计量集成电路的功耗可以减少电能表给电网带来的额外功耗,能够延长电能表中备用供电电池的使用时间,提高电能表防窃电的灵敏度,降低电能表的制造成本。
本文从结构级设计的低功耗策略出发,给出了普通电能计量中时域积分算法的一种数字集成电路设计实现方法。通过将时域积分算法转化为多速率数据处理,降低了对运算能力的要求,减少了翻转率。针对其运算类型和数据更新率逐级降低的特点,设计了有专用指令集和专用结构的数字信号运算单元。由多数据率运算状态机进行合理调度,通过复用运算单元,在电路翻转率为33.288%的情况下完成了所有的运算任务。针对运算任务设计所需的运算指令集,减少了冗余电路、简化了电路结构,降低了功耗。
在计量性能测试达到设计指标的前提下,从已知的工艺条件来看,芯片使用0.25μm的工艺,其数字电路消耗的电流与使用0.18μm工艺的当前主流同类芯片的数字电路电流相当,即在同等工艺下,芯片的数字电路功耗将仅有其他芯片的1/2左右。应用此电路设计方法的电能计量集成电路已经商业化并量产数千万片。
现有的关于谐波电能计量方法的研究工作大都集中在对采样数据的后处理上,需要依赖复杂的算法进而需要强大的数字信号处理能力进行实现,运算量大。即使是同步采样的方法,同样存在运算量大或者生成同步采样时钟的电路结构复杂、设计代价大等不足之处。
本文从减少运算量、简化电路结构、降低功耗、适合集成电路设计实现的角度,充分结合过采样模数转换器的结构特点,提出了一种用于谐波电能计量的非均匀同步过采样方法；详细介绍了非均匀同步过采样时钟的产生原理,分析了各个设计参数之间的相互关系以及它们对采样结果的影响,确定了采样过程在谐波带宽内带来的采样噪声以及频谱泄漏的分布和幅度,并确定了采样过程对谐波信号的幅值和相位的调制影响,给出了选择快速傅里叶变换运算点数的方法。
非均匀同步过采样方法利用过采样和时钟的非均匀特性,降低了对过采样时钟频率分辨率的要求,大幅减少了延时单元的个数,简化了电路结构。通过合理设计过采样率、过采样和降采样两个阶段中非均匀采样时钟频率的概率分布以及变化周期,减小了非均匀采样噪声对谐波频谱的调制影响,保证了非均匀过采样时钟是统计意义上跟踪基波频率的同步采样时钟。
采样数据可以作为均匀同步采样序列直接进行快速傅里叶变换,无需消除非均匀采样噪声或者消除频谱泄漏的额外运算,大幅减小了对后续处理运算能力的要求。各次谐波在频谱上的位置也不再随基波频率变化而波动,可以根据算法带来的增益衰减进行固定补偿,从而降低了对降采样低通滤波器通带设计指标的要求,简化了其电路结构,降低了功耗。
在延时单元个数ND=11的情况下,非均匀同步过采样和降采样带来的采样噪声和频谱泄漏幅度均接近或者小于∑-△过采样模数转换器量化噪声的幅度-120dB。若增大ND的值,会得到更小的测量误差。
本文还针对采样时钟的非均匀和同步特性,在传统的正交解调方法的基础上,提出了正交信号恢复环路测量基波频率的方法,消除了非均匀时钟的频率时变等因素的影响。环路控制量不是传统锁相环或者自动频率控制机制中的相位差或者频率差,而是输入信号频率与输出频率值的商。整个测频算法可以等效成为开环系统,提高了环路的稳定性并缩短了环路的响应时间。
滤除谐波与基波差频的滤波器以及环路中的求相位差运算给基波频率的测量带来了一定的局限性。在今后的工作中将对这些问题进行更深入的研究。
Reducing power consumption of energy metering ICs could decrease extra power loads generated by energy meters on power grid. The life of backup batteries in energy meters could also be extended. Higher level of anti-tampering sensitivity and lower hardware cost of meters could be achieved too.
An IC implementation of the time-domain integral algorithm of ordinary energy metering was given. Computing capability requirements and circuit flip rates were reduced by converting the algorithm into multirate data processing. According to calculation types and progressively reduced data rates, a digital signal computing unit with specific instructions and architecture was designed. Controlled by the multirate computing FSM besides reusing computing resources, all calculation tasks were completed with circuit flip rate of33.288%. The instruction set was designed just according to calculation tasks, thus there is less redundant circuits and lower power consumption is achieved.
The result of metering performance test meets the design specifications. The known process implemented by other mainstream MFEs is0.18μm. The designed chip was manufactured in TSMC0.25μm process. The digital current dissipation of the designed chip is comparable with that of the mainstream MFEs. If implemented in same process, the digital current will be half of that of the mainstream MFEs. Some energy metering ICs applying this design method have been in mass production and have been shipped tens of millions of chips.
Current researches of harmonics energy measurement mostly focused on post process of sampled sequences, depending on sophisticated algorithms, and required powerful digital signal processors to carry out. For synchronous sampling methods, higher calculation requirements or complex sampling clock generation circuit was presented.
According to oversampling ADC's characteristics, a non-uniform synchronous oversampling method used to measure harmonics was proposed, from the perspective of less computation, simpler circuit, lower power consumption and oriented for IC implementation. Principle of the non-uniform synchronous oversampling clock generation by DDLL was explained. Relationship between each design parameter and their effects on sampling results were analyzed. Distribution and amplitude of sampling noise and spectral leakage introduced by sampling were identified. Modulation on harmonic signal's amplitude and phase was determined. How to choose the number of sample points for FFT was also derived.
The requirements on frequency resolution of sampling clock are reduced by clock's oversampling and non-uniform property. Number of delay cells in DDLL is significantly reduced and the structure of DDLL is simplified.Oversampling ratio, probability distribution and variation period of sampling clock frequency in both oversampling and down-sampling stages were properly designed to suppress the impact of spectrum modulation by sampling noise. The generated non-uniform clock can be treated as synchronous clock tracking the fundamental in statistical meaning.
The final down-sampled data can be treated as uniformly sampled and synchronous ones. FFT can be directly applied, no extra work of sampling noise and spectral leakage elimination needed. Position of harmonics in spectrum won't vary any more so that fixed compensation of system attenuation in gain can be carry out, which lowers design requirements on down-sampling low-pass filters. All these characteristics bring low power consumption.
When ND=11, the overall sampling noise and spectral leakage is nearby or smaller than-120dB which is the quantitative noise floor of ADC.The larger ND is, the smaller measurement error will be got.
Regarding the non-uniform and synchronous nature of the sampling clock, a QSRL fundamental frequency measurement method based on traditional quadrature demodulation was proposed. The impact of clock frequency variation is eliminated. Contrary to phase or frequency error in PLL and AFC, the loop control variable is input signal frequency over output frequency. QSRL is equivalent to an open-loop system, with higher stability and shorter response time.
Both the calculation of phase difference and the low-pass filter to cancel beat frequencies between fundamental and harmonics bring limitations to fundamental frequency measurement. These issues will be studied more in future work.
本文从结构级设计的低功耗策略出发,给出了普通电能计量中时域积分算法的一种数字集成电路设计实现方法。通过将时域积分算法转化为多速率数据处理,降低了对运算能力的要求,减少了翻转率。针对其运算类型和数据更新率逐级降低的特点,设计了有专用指令集和专用结构的数字信号运算单元。由多数据率运算状态机进行合理调度,通过复用运算单元,在电路翻转率为33.288%的情况下完成了所有的运算任务。针对运算任务设计所需的运算指令集,减少了冗余电路、简化了电路结构,降低了功耗。
在计量性能测试达到设计指标的前提下,从已知的工艺条件来看,芯片使用0.25μm的工艺,其数字电路消耗的电流与使用0.18μm工艺的当前主流同类芯片的数字电路电流相当,即在同等工艺下,芯片的数字电路功耗将仅有其他芯片的1/2左右。应用此电路设计方法的电能计量集成电路已经商业化并量产数千万片。
现有的关于谐波电能计量方法的研究工作大都集中在对采样数据的后处理上,需要依赖复杂的算法进而需要强大的数字信号处理能力进行实现,运算量大。即使是同步采样的方法,同样存在运算量大或者生成同步采样时钟的电路结构复杂、设计代价大等不足之处。
本文从减少运算量、简化电路结构、降低功耗、适合集成电路设计实现的角度,充分结合过采样模数转换器的结构特点,提出了一种用于谐波电能计量的非均匀同步过采样方法；详细介绍了非均匀同步过采样时钟的产生原理,分析了各个设计参数之间的相互关系以及它们对采样结果的影响,确定了采样过程在谐波带宽内带来的采样噪声以及频谱泄漏的分布和幅度,并确定了采样过程对谐波信号的幅值和相位的调制影响,给出了选择快速傅里叶变换运算点数的方法。
非均匀同步过采样方法利用过采样和时钟的非均匀特性,降低了对过采样时钟频率分辨率的要求,大幅减少了延时单元的个数,简化了电路结构。通过合理设计过采样率、过采样和降采样两个阶段中非均匀采样时钟频率的概率分布以及变化周期,减小了非均匀采样噪声对谐波频谱的调制影响,保证了非均匀过采样时钟是统计意义上跟踪基波频率的同步采样时钟。
采样数据可以作为均匀同步采样序列直接进行快速傅里叶变换,无需消除非均匀采样噪声或者消除频谱泄漏的额外运算,大幅减小了对后续处理运算能力的要求。各次谐波在频谱上的位置也不再随基波频率变化而波动,可以根据算法带来的增益衰减进行固定补偿,从而降低了对降采样低通滤波器通带设计指标的要求,简化了其电路结构,降低了功耗。
在延时单元个数ND=11的情况下,非均匀同步过采样和降采样带来的采样噪声和频谱泄漏幅度均接近或者小于∑-△过采样模数转换器量化噪声的幅度-120dB。若增大ND的值,会得到更小的测量误差。
本文还针对采样时钟的非均匀和同步特性,在传统的正交解调方法的基础上,提出了正交信号恢复环路测量基波频率的方法,消除了非均匀时钟的频率时变等因素的影响。环路控制量不是传统锁相环或者自动频率控制机制中的相位差或者频率差,而是输入信号频率与输出频率值的商。整个测频算法可以等效成为开环系统,提高了环路的稳定性并缩短了环路的响应时间。
滤除谐波与基波差频的滤波器以及环路中的求相位差运算给基波频率的测量带来了一定的局限性。在今后的工作中将对这些问题进行更深入的研究。
Reducing power consumption of energy metering ICs could decrease extra power loads generated by energy meters on power grid. The life of backup batteries in energy meters could also be extended. Higher level of anti-tampering sensitivity and lower hardware cost of meters could be achieved too.
An IC implementation of the time-domain integral algorithm of ordinary energy metering was given. Computing capability requirements and circuit flip rates were reduced by converting the algorithm into multirate data processing. According to calculation types and progressively reduced data rates, a digital signal computing unit with specific instructions and architecture was designed. Controlled by the multirate computing FSM besides reusing computing resources, all calculation tasks were completed with circuit flip rate of33.288%. The instruction set was designed just according to calculation tasks, thus there is less redundant circuits and lower power consumption is achieved.
The result of metering performance test meets the design specifications. The known process implemented by other mainstream MFEs is0.18μm. The designed chip was manufactured in TSMC0.25μm process. The digital current dissipation of the designed chip is comparable with that of the mainstream MFEs. If implemented in same process, the digital current will be half of that of the mainstream MFEs. Some energy metering ICs applying this design method have been in mass production and have been shipped tens of millions of chips.
Current researches of harmonics energy measurement mostly focused on post process of sampled sequences, depending on sophisticated algorithms, and required powerful digital signal processors to carry out. For synchronous sampling methods, higher calculation requirements or complex sampling clock generation circuit was presented.
According to oversampling ADC's characteristics, a non-uniform synchronous oversampling method used to measure harmonics was proposed, from the perspective of less computation, simpler circuit, lower power consumption and oriented for IC implementation. Principle of the non-uniform synchronous oversampling clock generation by DDLL was explained. Relationship between each design parameter and their effects on sampling results were analyzed. Distribution and amplitude of sampling noise and spectral leakage introduced by sampling were identified. Modulation on harmonic signal's amplitude and phase was determined. How to choose the number of sample points for FFT was also derived.
The requirements on frequency resolution of sampling clock are reduced by clock's oversampling and non-uniform property. Number of delay cells in DDLL is significantly reduced and the structure of DDLL is simplified.Oversampling ratio, probability distribution and variation period of sampling clock frequency in both oversampling and down-sampling stages were properly designed to suppress the impact of spectrum modulation by sampling noise. The generated non-uniform clock can be treated as synchronous clock tracking the fundamental in statistical meaning.
The final down-sampled data can be treated as uniformly sampled and synchronous ones. FFT can be directly applied, no extra work of sampling noise and spectral leakage elimination needed. Position of harmonics in spectrum won't vary any more so that fixed compensation of system attenuation in gain can be carry out, which lowers design requirements on down-sampling low-pass filters. All these characteristics bring low power consumption.
When ND=11, the overall sampling noise and spectral leakage is nearby or smaller than-120dB which is the quantitative noise floor of ADC.The larger ND is, the smaller measurement error will be got.
Regarding the non-uniform and synchronous nature of the sampling clock, a QSRL fundamental frequency measurement method based on traditional quadrature demodulation was proposed. The impact of clock frequency variation is eliminated. Contrary to phase or frequency error in PLL and AFC, the loop control variable is input signal frequency over output frequency. QSRL is equivalent to an open-loop system, with higher stability and shorter response time.
Both the calculation of phase difference and the low-pass filter to cancel beat frequencies between fundamental and harmonics bring limitations to fundamental frequency measurement. These issues will be studied more in future work.
引文
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