机内测试技术在某型自动驾驶仪中的应用研究
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摘要
机内测试(Built In Test-BIT)技术是复杂系统或设备整体设计、分系统设计、状态监测、故障诊断和维修决策等方面的关键共性技术。近20年来,随着许多高科技武器系统的应用范围不断扩大,研究实用的机内测试技术,对于提高装备的可测试性,降低维护和保障费用具有重要意义。
本论文对机内测试技术做了深入的研究,在理论分析基础上,通过一种具体的型号设备,对机内测试技术在工程实践中的应用做了一些探索性的研究工作。
结合某型自动驾驶仪弹载计算机系统的实际背景及机内测试技术的发展现状,阐述了开展机内测试技术研究的重要意义。通过分析该型自动驾驶仪弹载计算机系统的功能和机内测试技术的基本理论,提出了机内测试技术的设计准则,并对影响机内测试的虚警率问题和实现机内测试的方法进行了论述,进而给出了针对该弹载计算机系统的机内测试设计思想,为机内测试技术在某型自动驾驶仪中的具体应用奠定了基础。论文的软、硬件设计部分详细论述了各部分硬件电路和软件程序的具体设计过程,给出了调试的步骤和结果分析。其中,硬件设计主要针对目标系统的CPU模块、A/D模块、D/A模块和RS422通讯模块等四个典型功能模块,经过方案论证、芯片选型、原理图绘制、PCB设计、电路调试等步骤,实现了硬件部分的设计,通过标准电压读入转换法、环绕测试法等通用BIT技术,实现了硬件电路的测试功能。软件设计主要包括了从主程序到各个子程序的设计,设计充分考虑了机内测试的可实现性,并采取了表决法、多级门限值设定法和均值法等,尽可能地提高系统的可靠性,降低虚警。
调试结果表明,本课题研究的机内测试系统,可以满足自动驾驶仪测试的设计要求,能够有效地提高自动驾驶仪弹载计算机系统的可靠性,使系统具有更好的应用价值、市场前景和军事意义。
During the past 20 years, the Built-In Test (BIT) technology plays a more and more important role in complex system design, conditional monitoring, fault diagnosis and equipment mantaintance. With the applications of high-tech weapon system, the practical BIT technology execises a great influence on the improvements of military equipment’s testability and reduction of maintainence and support cost.
In this thesis, the implementation of Built-In Test technology in the autopilot device is investigated.
Based on the analysis of onboard computer system in autopilot and the state of art of the BIT technology, the importance of research in BIT theory is expatiated. With the analysis of the autopilot equipment function and the BIT technology, the design principles of BIT system are proposed, the false alarm problem and design method are analyzed in detail. The design philosophy of BIT which provides reference for further implementation in onboard computer system of autopilot is suggested. The software and hardware design of autopilot BIT system with debug routines and results analysis are explained at lenth in this thesis. In hardware system of onboard computer system, BIT functions are implemented in CPU module, A/D module, D/A module and RS422 module. With the implementation of general BIT technologies such as standard voltage compare and loop test, the hardware design goal is accomplished through the procedure which includes conceptual design, circuit schematic design, PCB layout and debugging. On the other hand, in order to get high degree of confidence, the voting method, multi threshold and averaging techniques are adopted to mitigate the false alarm probability in software design; the realizability of software system in BIT system is also considered.
The experimental results demonstrate that the BIT system proposed in this thesis can achieve the goal of system design and increase the system reliability.
本论文对机内测试技术做了深入的研究,在理论分析基础上,通过一种具体的型号设备,对机内测试技术在工程实践中的应用做了一些探索性的研究工作。
结合某型自动驾驶仪弹载计算机系统的实际背景及机内测试技术的发展现状,阐述了开展机内测试技术研究的重要意义。通过分析该型自动驾驶仪弹载计算机系统的功能和机内测试技术的基本理论,提出了机内测试技术的设计准则,并对影响机内测试的虚警率问题和实现机内测试的方法进行了论述,进而给出了针对该弹载计算机系统的机内测试设计思想,为机内测试技术在某型自动驾驶仪中的具体应用奠定了基础。论文的软、硬件设计部分详细论述了各部分硬件电路和软件程序的具体设计过程,给出了调试的步骤和结果分析。其中,硬件设计主要针对目标系统的CPU模块、A/D模块、D/A模块和RS422通讯模块等四个典型功能模块,经过方案论证、芯片选型、原理图绘制、PCB设计、电路调试等步骤,实现了硬件部分的设计,通过标准电压读入转换法、环绕测试法等通用BIT技术,实现了硬件电路的测试功能。软件设计主要包括了从主程序到各个子程序的设计,设计充分考虑了机内测试的可实现性,并采取了表决法、多级门限值设定法和均值法等,尽可能地提高系统的可靠性,降低虚警。
调试结果表明,本课题研究的机内测试系统,可以满足自动驾驶仪测试的设计要求,能够有效地提高自动驾驶仪弹载计算机系统的可靠性,使系统具有更好的应用价值、市场前景和军事意义。
During the past 20 years, the Built-In Test (BIT) technology plays a more and more important role in complex system design, conditional monitoring, fault diagnosis and equipment mantaintance. With the applications of high-tech weapon system, the practical BIT technology execises a great influence on the improvements of military equipment’s testability and reduction of maintainence and support cost.
In this thesis, the implementation of Built-In Test technology in the autopilot device is investigated.
Based on the analysis of onboard computer system in autopilot and the state of art of the BIT technology, the importance of research in BIT theory is expatiated. With the analysis of the autopilot equipment function and the BIT technology, the design principles of BIT system are proposed, the false alarm problem and design method are analyzed in detail. The design philosophy of BIT which provides reference for further implementation in onboard computer system of autopilot is suggested. The software and hardware design of autopilot BIT system with debug routines and results analysis are explained at lenth in this thesis. In hardware system of onboard computer system, BIT functions are implemented in CPU module, A/D module, D/A module and RS422 module. With the implementation of general BIT technologies such as standard voltage compare and loop test, the hardware design goal is accomplished through the procedure which includes conceptual design, circuit schematic design, PCB layout and debugging. On the other hand, in order to get high degree of confidence, the voting method, multi threshold and averaging techniques are adopted to mitigate the false alarm probability in software design; the realizability of software system in BIT system is also considered.
The experimental results demonstrate that the BIT system proposed in this thesis can achieve the goal of system design and increase the system reliability.
引文
1张艳梅.制导炸弹的历史与现状.飞航导弹.1995,12:22~25
2付伟.激光制导武器的发展现状.飞航导弹.1995,5:16~17
3易晓山,李剑,刘冠军.某捷联惯导系统的BIT设计与实现.测控技术.2000,19 (9):15~18
4 Walker R.K.,Built In Test Utilization for Improved Supportability of The F-20 Aircraft, 1985 IEEE AUTOTESTCON, PP: 446~449
5 Colins M.A Universal Framework for Managed Built-in Test. International Test Conference,1993:1170~1175
6韩庆田,卢洪义,杨兴根.军用装备测试性技术发展趋势分析.仪器仪表学报.2006,27(6):352~353
7 Dale W P. Smart Built-in Test. N90-25512,1990:123~126
8 Van De Goor, A.J., Using march tests to test SRAMs. IEEE Design & Test of Computers.1993-10, PP:8～14
9 George D,Mike S. BIT Blueprint Toward More Effective Built in Test. IEEE. Piscataway, NJ, USA, 1990:353～360
10温熙森,徐永成,易晓山.智能机内测试理论与应用.国防工业出版社.2002:4～40
11申安玉,申学仁.自动飞行控制系统.国防工业出版社, 2003:32～45
12以光衢等.航空机载电子系统与设备.北京航空航天大学出版社, 1997:26
13卞春江.航空发动机电子控制器BIT设计及验证技术研究.南京航空航天大学.2005.3:16
14 Zbytniewski. J , Cooper. C. CNDs and RTOKs : are we addressing these problems correstly In : 1994 Proc. of Naccon. Dayton , OH , 1994: 402～410
15 Kerry. Westervelt . F/ A218D (RC) Built-in Test False Alarms. Naval Air Warfare Center Aircraf t Division ,2000 , MD2067021624 : 2961～2970
16 Press. R. E , Elerin. L. M. The application of neural network technology to built-in test false alarm filtering. AIAA 293247152 CP , 1993:1383～1398
17 William . R Simpson , John . W. Sheppard. Analysis of False Alarms During System Design. IEEE NAECON , 1992:56～74
18徐亨成,杨文杰.机内测试虚警分析及控制.国外电子测量技术.2005,5:39～42
19冯振声,黄考利.陆军导弹武器系统测试性研究.火力与指挥控制.2004,29(5):88~92
20 Monahos,Baluta,Kelly. Computer-Aided Design for Built-in-Test(CADBI T). RADETR-89-209,1989:160～164
21曾天翔.电子设备测试性及诊断技术,航空工业出版社,1996:64~70
22田仲,石君友.系统测试性设计分析与验证,北京:北京航空航天大学出版社, 2001:37~45
23张小林.机载测控系统BIT设计中关键技术研究.测控技术.2003年第
22卷第11期:31～33
24 Isermann R. Fault diagnosis of machines via parameter estimation and knowledge processing-a tutorial paper. Automatica, 1993,29(4):815～835
25周东华,叶银忠.现代故障诊断与容错控制北京.清华大学出版社,2000:149~156
26 Wang H. Fault detection and diagnosis for unknown nonlinear systems:a generalized framework via neural networks In:proc. Of IEEE Int. Con. On Intelligent Processing Systems,ICIPS, v 2, 1998:1506～1510
27 Patton R J. Fault diagnosis in nonlinear dynamic systems via neural network[J]. IEEE Conference Publication,Coventry, UK 1994,2(389):21～24
28张宝珍,曾天翔.智能BIT技术测控技术,2000 , (11) :1～4
29 Dekker R, Beenker F, Thijssen L. Fault modeling and test algorithm development for static random access memories. IEEE International Test Conference,Washington, DC, USA 1988:343～352
30 Daniel L. Ostapko and SE June Hong, Fault Analysis and Test Generation for Programmable Logic Arrays(PLA’s),IEEE Trans. On Comp. Vol. C-28, NO. 9, September 1979:617～627
31李志刚. 1553B总线测试系统的设计与实现.西北工业大学硕士学位论文. 2005:6～10
32任哲平,韩永,牛春平.对1553B总线系统的一种测试方法.车辆与动力技术. 2003,(3):19～23
33陆尧,苗克坚,俞华虎. 1553B总线接口实时时钟的设计与实现.测控技术.2001, 20(6):23～34
34 RS-422 and RS-485 Application Note. B&B Electronics Mfg.Co.Inc.1997:1～11
35沙占有.新型特种集成电源及应用.人民邮电出版社.1997:1~3
36 Protel DXP电路原理图与PCB设计.机械工业出版社.2004:1～2
37索世文,马刚.基于Protel的PCB板图设计.沈阳航空工业学院学报.2007, 24(3):54~60
38赵建领.Protel电路设计与制板.电子工业出版社,2007.1:214～215
39夏路易,石宗义.电路原理图与电路板设计教程.北京希望电子出版社, 2002:10～68
40高鹏,安涛,寇怀成.电路设计与制板Protel99入门与提高.人民邮电出版社, 2004:51～64
41 TMS320C6000 Programmer’s Guide. Texas Instruments Incorporated. 2002:29～43
42 Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang, An on-chip march pattern generator for testing embedded memory cores, IEEE Trans on Very Large Scale Integration (VLSI) Systems, 2001-9(5):730～735
43 Yarmolik, V.N., Klimets, Yu.V., van de Goor, A.J., Demidenko, S.N.,RAM diagnostic tests,Memory Technology, Design and Testing, 1996. Records of the 1996 IEEE International Workshop on , August 13-14, Baltimore, MD, United States 1996:100～102
44 Gang-Min Park, Hoon Chang, An extended march test algorithm for embedded memories, Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian , 17-19 Nov. Akita, Jpn 1997:404～409
2付伟.激光制导武器的发展现状.飞航导弹.1995,5:16~17
3易晓山,李剑,刘冠军.某捷联惯导系统的BIT设计与实现.测控技术.2000,19 (9):15~18
4 Walker R.K.,Built In Test Utilization for Improved Supportability of The F-20 Aircraft, 1985 IEEE AUTOTESTCON, PP: 446~449
5 Colins M.A Universal Framework for Managed Built-in Test. International Test Conference,1993:1170~1175
6韩庆田,卢洪义,杨兴根.军用装备测试性技术发展趋势分析.仪器仪表学报.2006,27(6):352~353
7 Dale W P. Smart Built-in Test. N90-25512,1990:123~126
8 Van De Goor, A.J., Using march tests to test SRAMs. IEEE Design & Test of Computers.1993-10, PP:8～14
9 George D,Mike S. BIT Blueprint Toward More Effective Built in Test. IEEE. Piscataway, NJ, USA, 1990:353～360
10温熙森,徐永成,易晓山.智能机内测试理论与应用.国防工业出版社.2002:4～40
11申安玉,申学仁.自动飞行控制系统.国防工业出版社, 2003:32～45
12以光衢等.航空机载电子系统与设备.北京航空航天大学出版社, 1997:26
13卞春江.航空发动机电子控制器BIT设计及验证技术研究.南京航空航天大学.2005.3:16
14 Zbytniewski. J , Cooper. C. CNDs and RTOKs : are we addressing these problems correstly In : 1994 Proc. of Naccon. Dayton , OH , 1994: 402～410
15 Kerry. Westervelt . F/ A218D (RC) Built-in Test False Alarms. Naval Air Warfare Center Aircraf t Division ,2000 , MD2067021624 : 2961～2970
16 Press. R. E , Elerin. L. M. The application of neural network technology to built-in test false alarm filtering. AIAA 293247152 CP , 1993:1383～1398
17 William . R Simpson , John . W. Sheppard. Analysis of False Alarms During System Design. IEEE NAECON , 1992:56～74
18徐亨成,杨文杰.机内测试虚警分析及控制.国外电子测量技术.2005,5:39～42
19冯振声,黄考利.陆军导弹武器系统测试性研究.火力与指挥控制.2004,29(5):88~92
20 Monahos,Baluta,Kelly. Computer-Aided Design for Built-in-Test(CADBI T). RADETR-89-209,1989:160～164
21曾天翔.电子设备测试性及诊断技术,航空工业出版社,1996:64~70
22田仲,石君友.系统测试性设计分析与验证,北京:北京航空航天大学出版社, 2001:37~45
23张小林.机载测控系统BIT设计中关键技术研究.测控技术.2003年第
22卷第11期:31～33
24 Isermann R. Fault diagnosis of machines via parameter estimation and knowledge processing-a tutorial paper. Automatica, 1993,29(4):815～835
25周东华,叶银忠.现代故障诊断与容错控制北京.清华大学出版社,2000:149~156
26 Wang H. Fault detection and diagnosis for unknown nonlinear systems:a generalized framework via neural networks In:proc. Of IEEE Int. Con. On Intelligent Processing Systems,ICIPS, v 2, 1998:1506～1510
27 Patton R J. Fault diagnosis in nonlinear dynamic systems via neural network[J]. IEEE Conference Publication,Coventry, UK 1994,2(389):21～24
28张宝珍,曾天翔.智能BIT技术测控技术,2000 , (11) :1～4
29 Dekker R, Beenker F, Thijssen L. Fault modeling and test algorithm development for static random access memories. IEEE International Test Conference,Washington, DC, USA 1988:343～352
30 Daniel L. Ostapko and SE June Hong, Fault Analysis and Test Generation for Programmable Logic Arrays(PLA’s),IEEE Trans. On Comp. Vol. C-28, NO. 9, September 1979:617～627
31李志刚. 1553B总线测试系统的设计与实现.西北工业大学硕士学位论文. 2005:6～10
32任哲平,韩永,牛春平.对1553B总线系统的一种测试方法.车辆与动力技术. 2003,(3):19～23
33陆尧,苗克坚,俞华虎. 1553B总线接口实时时钟的设计与实现.测控技术.2001, 20(6):23～34
34 RS-422 and RS-485 Application Note. B&B Electronics Mfg.Co.Inc.1997:1～11
35沙占有.新型特种集成电源及应用.人民邮电出版社.1997:1~3
36 Protel DXP电路原理图与PCB设计.机械工业出版社.2004:1～2
37索世文,马刚.基于Protel的PCB板图设计.沈阳航空工业学院学报.2007, 24(3):54~60
38赵建领.Protel电路设计与制板.电子工业出版社,2007.1:214～215
39夏路易,石宗义.电路原理图与电路板设计教程.北京希望电子出版社, 2002:10～68
40高鹏,安涛,寇怀成.电路设计与制板Protel99入门与提高.人民邮电出版社, 2004:51～64
41 TMS320C6000 Programmer’s Guide. Texas Instruments Incorporated. 2002:29～43
42 Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang, An on-chip march pattern generator for testing embedded memory cores, IEEE Trans on Very Large Scale Integration (VLSI) Systems, 2001-9(5):730～735
43 Yarmolik, V.N., Klimets, Yu.V., van de Goor, A.J., Demidenko, S.N.,RAM diagnostic tests,Memory Technology, Design and Testing, 1996. Records of the 1996 IEEE International Workshop on , August 13-14, Baltimore, MD, United States 1996:100～102
44 Gang-Min Park, Hoon Chang, An extended march test algorithm for embedded memories, Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian , 17-19 Nov. Akita, Jpn 1997:404～409