一款FPGA可编程逻辑块的全定制设计
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摘要
可编程逻辑块是FPGA可以通过配置实现各种数字电路结构的核心器件。其设计的优劣直接影响着FPGA实现具体设计的性能及FPGA芯片可以承载的最大系统级晶体管数。因此,在FPGA芯片设计中,可编程逻辑块的设计是最关键的环节。
本文使用130nm工艺设计了一款适用于1000万系统门FPGA的可编程逻辑块。根据从顶到底的全定制设计方法,首先利用实验法及CAD工具完成了总体结构初步设计,然后根据各模块的可配置的功能特点结合可实现电路的基本形式,完成了电路的手工搭建工作,并且利用Elmore线性模型及Logic effort方法完成速度的优化及晶体管尺寸的确定,最后根据总体结构及面积的大小进行了版图规划,并对所设计的模块进行功耗评估、仿真验证、速度性能对比等。
设计完成的可编程逻辑块,独有一条快速的查找表输出路径,提高了查找表独立使用时的速度,与Xilinx VirtexII相比该路径速度提升了接近10%;另外加入了一条快速进位路径,提高了FPGA实现加法器的性能;所设计的可配置存储单元可以根据配置成为同步/异步的锁存器/D触发器,提高了存储单元的多变性,并且利用低功耗工艺,使可编程逻辑块的静态电流约降低为441.46nA,从而整体降低以此模块实现的FPGA芯片的静态功耗。所设计的可编程逻辑块可实现1000万系统门的FPGA芯片,并通过MPW流片验证该模块查找表、可编程存储器、进位链等功能的正确性。
Configurable logic blocks is the core of the FPGAs which makes FPGA be able to achieve a variety of digital circuit structures.The quality of the block’s design directly effects the performance of the FPGA and the maximum system gates that FPGA included. Therefore,the design of the configuration logic block is the most important thing in the design of FPGA devices.
The goal of this paper is to develop a method of designing a configurable logic block , and design a configurable logic block with 130nm CMOS process which can be used to construct a 10 million system gates FPGA device.At first, the overall structure of the configurable logic block is designed by combining the experiment method and CAD tool with the top-down approach. Secondly, each module of the block is implemented regarding to their specific functionalities. Third, the speed optimization and determination of the transistor sizes are carried out using Elmore linear model and logic effort method. Finally, the overlook of the layout is drawn by the structure and the area. In the end after evaluating the power consumtion of the block we verified the functionality and performance of the block through simulations .
The completed configurable logic block has a unique fast output path of the lookup table. Thus, it is 10% faster than Xilinx VirtexII when it is used indepently.The configurable logic block also has a fast carrychain increasing the performance of the adder and the configurable store unite is able to be set as a synchronous / asynchronous latch / D flip-flop, which increases the volatility of the memory cell. Moreover, by introducing the low-power process, this design reduces the static current to 441.46nA, which leads to a significant reduction to the whole static power of the FPGA device.The design can be used to construct a 10 million system gates FPGA and the function of the look-up table, programmable memory, carry chain and other modules are verified by the MPW tape.
本文使用130nm工艺设计了一款适用于1000万系统门FPGA的可编程逻辑块。根据从顶到底的全定制设计方法,首先利用实验法及CAD工具完成了总体结构初步设计,然后根据各模块的可配置的功能特点结合可实现电路的基本形式,完成了电路的手工搭建工作,并且利用Elmore线性模型及Logic effort方法完成速度的优化及晶体管尺寸的确定,最后根据总体结构及面积的大小进行了版图规划,并对所设计的模块进行功耗评估、仿真验证、速度性能对比等。
设计完成的可编程逻辑块,独有一条快速的查找表输出路径,提高了查找表独立使用时的速度,与Xilinx VirtexII相比该路径速度提升了接近10%;另外加入了一条快速进位路径,提高了FPGA实现加法器的性能;所设计的可配置存储单元可以根据配置成为同步/异步的锁存器/D触发器,提高了存储单元的多变性,并且利用低功耗工艺,使可编程逻辑块的静态电流约降低为441.46nA,从而整体降低以此模块实现的FPGA芯片的静态功耗。所设计的可编程逻辑块可实现1000万系统门的FPGA芯片,并通过MPW流片验证该模块查找表、可编程存储器、进位链等功能的正确性。
Configurable logic blocks is the core of the FPGAs which makes FPGA be able to achieve a variety of digital circuit structures.The quality of the block’s design directly effects the performance of the FPGA and the maximum system gates that FPGA included. Therefore,the design of the configuration logic block is the most important thing in the design of FPGA devices.
The goal of this paper is to develop a method of designing a configurable logic block , and design a configurable logic block with 130nm CMOS process which can be used to construct a 10 million system gates FPGA device.At first, the overall structure of the configurable logic block is designed by combining the experiment method and CAD tool with the top-down approach. Secondly, each module of the block is implemented regarding to their specific functionalities. Third, the speed optimization and determination of the transistor sizes are carried out using Elmore linear model and logic effort method. Finally, the overlook of the layout is drawn by the structure and the area. In the end after evaluating the power consumtion of the block we verified the functionality and performance of the block through simulations .
The completed configurable logic block has a unique fast output path of the lookup table. Thus, it is 10% faster than Xilinx VirtexII when it is used indepently.The configurable logic block also has a fast carrychain increasing the performance of the adder and the configurable store unite is able to be set as a synchronous / asynchronous latch / D flip-flop, which increases the volatility of the memory cell. Moreover, by introducing the low-power process, this design reduces the static current to 441.46nA, which leads to a significant reduction to the whole static power of the FPGA device.The design can be used to construct a 10 million system gates FPGA and the function of the look-up table, programmable memory, carry chain and other modules are verified by the MPW tape.
引文
[1] Clive Max Maxfield . The Design Warrior’s Guide to FPGAs Devices ,Tools and Flows.人民邮电出版社2007.P36
[2] Vaughn Betz .Jonathan Rose,Alexander,Marquardt.Architecture and CAD for Deep-Submicron FPGAs.电子工业出版社.2007.P1-124
[3] A. Marquardt. V. Betz and J. Rose.Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Monterey. CA. February 1999. P37 - 46
[4] V. Betz and J. Rose, How Much Logic Should Go in an FPGA Logic Block?. IEEE Design and Test Magazine. Spring 1998. P10 - 15
[5] V. Betz and J. Rose, VPR: A New Packing. Placement and Routing Tool for FPGA Research.Seventh International Workshop on Field-Programmable Logic and Applications, London. UK. 1997. P213 - 222
[6] V. Betz and J. Rose, Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size, IEEE Custom Integrated Circuits Conference. Santa Clara. CA. 1997. P551 - 554
[7] Xilinx.Virtex-II Platform FPGAs:Complete Data Sheet 2000.P3-300
[8] Xilinx. Virtex Platform FPGAs:Complete Data Sheet 1998.P3-300
[9] Altera . Cyclone FPGA Family Data Sheet 1998.P12-20
[10] Altera. Cyclone II Device Family Data Sheet 2000.P1-50
[11] Neil H.E Weste .CMOS VLSI DesigNMOS:a Circuits and Ststems Persoective.Third Edition .2006. P599
[12] Algotronix.Method and apparatus for secure configuration of a field programmable gate array. US Pat. 7203842.2000 P1-8
[13]Xilinx.San Jose.FPGA architecture with deep lookup table rams,American patent 2000 P1-8
[14]Xilinx.FPGA lookup table with transmission gate structure for reliable low-voltage operation.American patent.2003 P1-5
[15] Trevor J .Bauer.FPGA Lookup Table With Dual Ended Write For Ram And Shift Register Modes. American patent.2000 P1-10
[16] Xilinx. Method for implemeting priority encoders using FPGA carry logic .1998 P1-9
[17]Xilinx.Trevor. FPGA architecture with dual-port deep lookup table rams.American patent 2000 P1-9
[18] Philip M .Fredin,Sunnyvale ;Edmond Y.Synchronous dual port ram .American patent .1995 P1-10
[19]Xilinx. FPGA lookup table with NOR gate write decoder and high speed read decode .American patent.2002.P1-10
[20] Kammal Chaudhary.FPGA Having Logic Element Carry Chain Capable of Generation Wide Xor Functions.2000 P1-8
[21]Xilinx.one bit full adder with sum and carry outputs capable of independent functionalities.American patent. 2005 P1-8
[22]Xilinx.Structures and methods for reducing power consumption in programmable logic devices.American patent .2005 P1-8
[23] Neil H.E Weste .CMOS VLSI DesigNMOS:a Circuits and Ststems Persoective.Third Edition .2006.P130-318
[24] Ivan Sutherland .Bob Sproull,David Harris .Logical Effort Design Fast COMOS Circuit,中国电力出版社.2009.P225-263,P130-222
[25] A. Marquardt. V. Betz and J. Rose. Timing-Driven Placement for FPGAs. ACM/SIGDA Int. Symp. on FPGAs, 2000. P203 - 213
[26] V. Betz and J. Rose.Automatic Generation of FPGA Routing Architectures from High-Level Descriptions. ACM/SIGDA Int. Symp. on FPGAs. 2000. P175 - 184.
[27] Ivo Bolsens.Challenges and Opportunities for FPGA Platforms. Springer Berlin 2002 P1-8
[28] Lei He. Tim Tuan. Challenges and Opportunities for Low Power FPGAs in Nanometer Technologies. ISLPED’05. August 8–10. 2005.P1-8
[29] Bernard J .NEW.Method and structure for providing a flip flop circuit with a configurable data input path 1995 P1-8
[30]SeyiVerma.How to perform meaningful benchmarks on FPGAs from different vendors .www.icembed.com.2000 P1-8
[31] J. Cong and Y. Ding, An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table .Based FPGA Designs. ICCAD. 1992. P48-53
[32] Maogang Wang .Multi-Million Gate FPGA Physical Design Challenges.ieee.2003 P1-8
[33] C. S. Chen. Y.-W. Tsay. T. HwangA. C. H. Wu and Y.-L. Lin.Combining Technology Mapping and Placement for Delay-Optimization inFffiA Designs. ICCAD. 1993.P240-247
[34] Xilinx.Virtex-II Platform FPGAs:Complete Data Sheet 2000. P49
[2] Vaughn Betz .Jonathan Rose,Alexander,Marquardt.Architecture and CAD for Deep-Submicron FPGAs.电子工业出版社.2007.P1-124
[3] A. Marquardt. V. Betz and J. Rose.Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Monterey. CA. February 1999. P37 - 46
[4] V. Betz and J. Rose, How Much Logic Should Go in an FPGA Logic Block?. IEEE Design and Test Magazine. Spring 1998. P10 - 15
[5] V. Betz and J. Rose, VPR: A New Packing. Placement and Routing Tool for FPGA Research.Seventh International Workshop on Field-Programmable Logic and Applications, London. UK. 1997. P213 - 222
[6] V. Betz and J. Rose, Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size, IEEE Custom Integrated Circuits Conference. Santa Clara. CA. 1997. P551 - 554
[7] Xilinx.Virtex-II Platform FPGAs:Complete Data Sheet 2000.P3-300
[8] Xilinx. Virtex Platform FPGAs:Complete Data Sheet 1998.P3-300
[9] Altera . Cyclone FPGA Family Data Sheet 1998.P12-20
[10] Altera. Cyclone II Device Family Data Sheet 2000.P1-50
[11] Neil H.E Weste .CMOS VLSI DesigNMOS:a Circuits and Ststems Persoective.Third Edition .2006. P599
[12] Algotronix.Method and apparatus for secure configuration of a field programmable gate array. US Pat. 7203842.2000 P1-8
[13]Xilinx.San Jose.FPGA architecture with deep lookup table rams,American patent 2000 P1-8
[14]Xilinx.FPGA lookup table with transmission gate structure for reliable low-voltage operation.American patent.2003 P1-5
[15] Trevor J .Bauer.FPGA Lookup Table With Dual Ended Write For Ram And Shift Register Modes. American patent.2000 P1-10
[16] Xilinx. Method for implemeting priority encoders using FPGA carry logic .1998 P1-9
[17]Xilinx.Trevor. FPGA architecture with dual-port deep lookup table rams.American patent 2000 P1-9
[18] Philip M .Fredin,Sunnyvale ;Edmond Y.Synchronous dual port ram .American patent .1995 P1-10
[19]Xilinx. FPGA lookup table with NOR gate write decoder and high speed read decode .American patent.2002.P1-10
[20] Kammal Chaudhary.FPGA Having Logic Element Carry Chain Capable of Generation Wide Xor Functions.2000 P1-8
[21]Xilinx.one bit full adder with sum and carry outputs capable of independent functionalities.American patent. 2005 P1-8
[22]Xilinx.Structures and methods for reducing power consumption in programmable logic devices.American patent .2005 P1-8
[23] Neil H.E Weste .CMOS VLSI DesigNMOS:a Circuits and Ststems Persoective.Third Edition .2006.P130-318
[24] Ivan Sutherland .Bob Sproull,David Harris .Logical Effort Design Fast COMOS Circuit,中国电力出版社.2009.P225-263,P130-222
[25] A. Marquardt. V. Betz and J. Rose. Timing-Driven Placement for FPGAs. ACM/SIGDA Int. Symp. on FPGAs, 2000. P203 - 213
[26] V. Betz and J. Rose.Automatic Generation of FPGA Routing Architectures from High-Level Descriptions. ACM/SIGDA Int. Symp. on FPGAs. 2000. P175 - 184.
[27] Ivo Bolsens.Challenges and Opportunities for FPGA Platforms. Springer Berlin 2002 P1-8
[28] Lei He. Tim Tuan. Challenges and Opportunities for Low Power FPGAs in Nanometer Technologies. ISLPED’05. August 8–10. 2005.P1-8
[29] Bernard J .NEW.Method and structure for providing a flip flop circuit with a configurable data input path 1995 P1-8
[30]SeyiVerma.How to perform meaningful benchmarks on FPGAs from different vendors .www.icembed.com.2000 P1-8
[31] J. Cong and Y. Ding, An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table .Based FPGA Designs. ICCAD. 1992. P48-53
[32] Maogang Wang .Multi-Million Gate FPGA Physical Design Challenges.ieee.2003 P1-8
[33] C. S. Chen. Y.-W. Tsay. T. HwangA. C. H. Wu and Y.-L. Lin.Combining Technology Mapping and Placement for Delay-Optimization inFffiA Designs. ICCAD. 1993.P240-247
[34] Xilinx.Virtex-II Platform FPGAs:Complete Data Sheet 2000. P49