p型多晶硅薄膜晶体管在动态负偏置温度应力下的退化研究
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摘要
本文主要研究了p型多晶硅薄膜晶体管(Thin Film Transistor, TFT )在动态负偏置温度(Negative Bias Temperature, NBT)应力下的退化特性。首次观察到了器件在动态NBT应力下的两阶段退化现象。在第一阶段Vth向正向漂移,在很长一段应力时间之后Vth出现回转现象向负向漂移。本文认为动态NBT应力下的动态效应是引起Vth正向漂移主要因素。动态效应强烈的依赖于脉冲的幅度以及脉冲下降沿,幅度越高、下降沿越快动态效应的影响越明显。动态效应下氧化层中产生了大量的固定负电荷引起了器件Vth的正向漂移。在动态效应饱和后,直流负偏置温度不稳定(Negative Bias Temperature Instability, NBTI)产生的晶界缺陷态导致了Vth的负向漂移。本文提出了在动态NBT应力下的氧化层负电荷产生模型,扩散进入氧化层的水汽以及脉冲应力下降沿时在沟道与源漏之间耗尽区产生的碰撞离化效应认为是退化模型的两个关键因素。并通过SILVACO软件模拟以及验证实验对所提出的模型进行验证。
此外,本文首次观察到了动态NBT应力后亚阈值区hump由产生到逐渐增大再逐步消失的过程。研究发现当动态效应主导器件的退化时,能够观察到hump现象,且随着应力幅度的减小hump出现和消失的时间延后。在高温时,与动态效应一样hump现象也受到抑制。基于本文提出的动态NBT应力下的退化模型,我们认为边缘寄生器件的存在以及其在动态NBT应力后不同时间段退化量的不同是引起亚阈值区hump产生和消失的原因。通过构建由一个中心器件和两个边缘寄生器件组合而成的器件,模拟应力后的中心器件和边缘器件的不同Vth漂移量来拟合实验器件亚阈值区的hump现象,很好的验证了动态NBT应力下的退化模型。
Degradation of p-channel poly-Si thin film transistors (TFTs) under dynamic negative bias temperature (NBT) stress has been studied. A two-stage degradation behavior is observed for the first time under the dynamic NBT stress. Device threshold voltage (Vth) shift towards positive values in the first stage to more negative values in the second stage. The Vth positive shift is thought to due to the dynamic effect under dynamic NBT stress and which will saturate after a long time stress. The dynamic effect is more significant under dynamic NBT stress with shorter pulse falling time and/or higher pulse amplitude. The negative charge generation in the gate oxide during the dynamic NBT stress is thought to be responsible for the positive Vth shift, while the well-known DC NBTI effect causes the negative Vth shift. A degradation mechanism is proposed to explain the negative charge generation under the dynamic NBT stress. The degradation model has been verified by both simulation and experimental results
The stress induced hump appearance and vanishing in the sub-threshold region is observed. The hump appears in the first stage of the degradation under dynamic NBT stress. The presence of parasitic edge transistor at the channel width side is thought to be responsible for the hump phenomenon. Based on our proposed degradation model under dynamic NBT stress, the device composed by a main transistor and two narrow edge transistors is introduced to clarify the hump phenomenon by considering the different Vth shift of the main transistor and two parasitic edge transistors. The well fitting result further proves the proposed degradation mechanism.
此外,本文首次观察到了动态NBT应力后亚阈值区hump由产生到逐渐增大再逐步消失的过程。研究发现当动态效应主导器件的退化时,能够观察到hump现象,且随着应力幅度的减小hump出现和消失的时间延后。在高温时,与动态效应一样hump现象也受到抑制。基于本文提出的动态NBT应力下的退化模型,我们认为边缘寄生器件的存在以及其在动态NBT应力后不同时间段退化量的不同是引起亚阈值区hump产生和消失的原因。通过构建由一个中心器件和两个边缘寄生器件组合而成的器件,模拟应力后的中心器件和边缘器件的不同Vth漂移量来拟合实验器件亚阈值区的hump现象,很好的验证了动态NBT应力下的退化模型。
Degradation of p-channel poly-Si thin film transistors (TFTs) under dynamic negative bias temperature (NBT) stress has been studied. A two-stage degradation behavior is observed for the first time under the dynamic NBT stress. Device threshold voltage (Vth) shift towards positive values in the first stage to more negative values in the second stage. The Vth positive shift is thought to due to the dynamic effect under dynamic NBT stress and which will saturate after a long time stress. The dynamic effect is more significant under dynamic NBT stress with shorter pulse falling time and/or higher pulse amplitude. The negative charge generation in the gate oxide during the dynamic NBT stress is thought to be responsible for the positive Vth shift, while the well-known DC NBTI effect causes the negative Vth shift. A degradation mechanism is proposed to explain the negative charge generation under the dynamic NBT stress. The degradation model has been verified by both simulation and experimental results
The stress induced hump appearance and vanishing in the sub-threshold region is observed. The hump appears in the first stage of the degradation under dynamic NBT stress. The presence of parasitic edge transistor at the channel width side is thought to be responsible for the hump phenomenon. Based on our proposed degradation model under dynamic NBT stress, the device composed by a main transistor and two narrow edge transistors is introduced to clarify the hump phenomenon by considering the different Vth shift of the main transistor and two parasitic edge transistors. The well fitting result further proves the proposed degradation mechanism.
引文
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[1] Naoyuki Shigyo, Ryo Dang,“Analysis of an Anomalous Subthreshold Current in a Fully Recessed Oxide MOSFET Using a Three-Dimensional Device Simulator,”IEEE Trans. Electron Devices, vol. ed-32, n. 2, pp. 441-445, 1985.
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[10] A. Valletta, P. Gaucci, L. Mariucci, G. Fortunato, and F. Templier,““Hump”characteristics and edge effects in polysilicon thin film transistors,”J. Appl. Phys., vol. 104, pp. 124511.1-124511.6, 2008.
[11] Szu-I Hsieh, Hsing-Yi Liang, Chrong-Jung Lin, and Ya-Chin King,“Stress Induced Width Dependent Degradation Of Low Temperature Polycrystalline Silicon Thin Film Transistor,”Applied Physics Letters. Vol.90, pp.183502, 2007.
[12] Ching-Fang Huang, Cheng-Yi Peng, Ying-Jhe Yang, Hung-Chang Sun, Hung-Chih Chang, Ping-Sheng Kuo, Huan-Lin Chang, Chee-Zxaing Liu, and Chee Wee Liu,“Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors, IEEE Electron Device Lett., Vol.29, No.12, pp.1332-1335, 2008.
[2]张猛,“动态电应力下n型多晶硅薄膜晶体管的退化研究,”苏州大学硕士学位论文,2010年5月.
[3] H. Wang, M. Wang, Z. Yang, H. Hao, and M. Wong,“Stress power dependent self-heating degradation of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors,”IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3276–3284, Dec. 2007.
[4] S. Inoue, H. Ohshimai, and T. Shimoda,“Analysis of degradation phenomenon caused byself-heating in low-temperature-processed polycrystalline silicon thin film transistors,”Jpn. J. Appl. Phys., vol. 41, no. 11A, pp. 6313–6319, Nov. 2002.
[5] M. Xue, M. Wang, Z. Zhu, D. Zhang, and M. Wong,“Degradation behaviors of metal-induced laterally crystallized n-type polycrystalline silicon thin-film transistors under DC bias stresses,”IEEE Trans. Electron Devices, vol. 54, no. 2, pp. 225–232, Feb. 2007.
[6] H. Tango, T. Satoh, and Y. Imai,“Hot-carrier-induced degradation of threshold voltage and transconductance in n-channel LDD and SD poly-Si TFTs,”Electron. Lett., vol. 38, no. 20, pp. 1227–1228, Sep. 2002.
[7] L. Mariucci, G. Fortunato, R. Carluccio, A. Pecora, S. Giovannini, and F. Massussi,“Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors,”J. Appl. Phys., vol. 84, no. 4, pp. 2341–2348, Aug. 1998.
[8] C. Hu, M. Wang, B. Zhang, and M. Wong“Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors,”IEEE Trans. Electron Devices, vol. 56, no. 4, pp. 587–594, Apr. 2009.
[9] C. Y. Chen, J. W. Lee, S. D. Wang, M. S. Shieh, P. H. Lee, W. C. Chen, H. Y. Lin, K. L. Yeh, and T. F. Lei,“Negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors,”IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 2993–3000, Dec. 2006.
[10] Zhu Zhen, Wang Mingxiang, Zhang Dongli, Wong Man,“Hot carrier induced leakage current instability in metal induced laterally crystallized n-type poly-silicon thin film transistors,”International Conference on Solid-State and Integrated Circuit Technology, Proceedings, pp.1129-1131, 2006
[11] Hu Chunfeng, Wang Mingxiang, Xu Meijuan,“Hot carrier stress induced negative differential resistance in the output characteristic of poly-Si TFTs,”Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, pp.337-340, 2010
[12] Zhang Meng, Wang Mingxiang, Wang Huaisheng,“Degradation of metal-induced laterally crystallized n-type poly-Si thin-film transistors under dynamic voltage stress,”Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 2008
[13] Wang Huaisheng, Wang Mingxiang, Wong Man,“Degradation of metal induced laterally crystallized n-type polysilicon TFTs under dynamic gate voltage stresses”, International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, pp. 640-643, 2008
[14] Meng ZHANG, Mingxiang WANG, Huaisheng WANG, Jie ZHOU,“Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors under Synchronized Voltage Stress,”IEEE Transactions on Electron Devices, VOL.56, No.11, pp.2726-32, 2009
[15] Hu Chunfeng, Wang Mingxiang, Zhang Meng, Zhang Bo, Wong Man, Degradation of solution based metal induced laterally crystallized p-type poly-si TFTs under DC bias stresses, IEEE International Reliability Physics Symposium Proceedings, pp. 363-367, 2008
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