应用于数字视频接收器的低功耗高速流水线模数转换器的研究
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摘要
随着数字机顶盒、数字高清电视和液晶平板电视的迅猛发展，日常消费电子产品中的数字视频解调接收器和视频图像处理信号接收前端的重要模块-模数转换器的应用越来越广泛，而且随着整机产品的功能和性能要求越来越高，功耗低面积小的数字视频片上系统(SoC)单芯片已经成为10位分辨率、多通道模数转换器的主要应用芯片，例如3通道采集RGB和YUV信号的视频模拟前端。但是由于片上系统单芯片集成了大量的模拟电路和数字逻辑电路，内部时钟频率也非常高，因此导致电路噪声偏大，影响模数转换器的性能。如何使模数转换器既拥有较强的抗干扰能力，同时达到低功耗的要求，越来越成为模拟集成电路研究的热点和难点。
论文主要研究了兼容0.18um 1.8V标准数字逻辑CMOS工艺应用于数字视频领域的流水线模数转换器，通过matlab的分析和优化，建立了系统级的设计框架，然后根据系统需求的采样率、输出分辨率等要求计算出影响模数转换器性能参数的限制指标。再根据工艺参数和EDA工具设计出了晶体管级电路并进行了全电路性能仿真。最后设计了整个模数转换器和测试芯片的布局及版图，完成了整个芯片设计的全部流程。期间主要的研究成果和工作有以下几个方面：
(1) 一般流水线模数转换器常用的动态比较器需要从外部输入参考源与输入信号进行比较然后输出数字域的结果，而本文提出的无输入参考源动态比较器不需要在比较器之外引入参考源而是利用比较器输入对管的差别产生比较阈值，这样减轻了参考源驱动电路的负载，排除了外部电路对动态比较器组成的子模数转换器模块的干扰，另外减少了外部引入参考源走线的数量进而减小了硅面积。
(2) 论文设计的低功耗高速模数转换器使用了1.8V电源，为了减少开关电容电路采样的信号失真，提出了一种新型的开关栅增压电路，使得信号开关器件的栅电压与输入信号无关，保持开关的导通电阻是常数，而且在增压传输路径中的开关导通电阻也与信号无关，从而降低了信号的谐波失真，提高了电路的动态范围。此外，所有的NMOS开关电路的衬底始终接在电路的最低电平上，这样就使该电路可以在普通的0.18um 1.8V数字标准逻辑CMOS工艺上实现，从而降低了芯片制造成本。
(3) 虽然流水线模数转换器的冗余位数字校正(RSD)能够消除一定的误差，但是在低电压应用中，由于信号输入幅度相对较高，因此冗佘校正后的误差仍较大，为了保证整个模数转换器依然有良好的线性度和良好的信噪比，论文提出了内插冗余校正技术。该技术的原理是：由于根据系统定义的噪声限制指标和制造工厂提供的工艺匹配参数可以计算出第i级之后插入一级冗余校正级。因此内插冗余校正级可以把第i级的输出大于正常输入范围数倍之内的信号做为输入(主要是第1级到第i级累积的误差并被MDAC电路放大引起的)然后输出时校正到后级能接受的正常输入范围，这样就可以避免最终模数转换器输出钳位和饱和引起整个ADC的线性度和动态范围的下降。
(4) 为了兼容标准数字逻辑工艺，MDAC中没有使用线性度较高的MiM电容，而是选
择了三明治式金属层间电容(stack capacitor)，这需要通过仔细提取金属层间电容的寄生参数以确保电容的线性度能保证整个ADC的性能。
(5) 为了优化电路的功耗和面积，论文设计的流水线模数转换器采用了运算放大器复用技术，这样可以让相邻的两个MDAC共用一个运算放大器，有效地降低了功耗和面积。
论文进行了两次硅实验，实验一是使用0.5um 2层多晶硅3层金属CMOS混合信号工艺实现了1MHz采样的10位流水线模数转换器电路，验证满足静态参数特性和动态参数性能的设计方法；实验二是使用0.18um 1.8V单层多晶硅6层金属标准逻辑工艺实现了100MHz采样的10位流水线模数转换器。在模数转换器的测试方面主要设计了高速电路应用的PCB板和整个测试平台环境搭建。实验一和实验二的DNL分别为0.71 LSB和0.47LSB；INL分别为0.8LSB和0.55LSB；实现的有效位(ENOB)分别为9.7位(1MHz采样)和9.3位(100MHz采样)；芯片面积分别为1.7mm~2和0.98mm~2；功耗分别为45mW和63mW，其中实验二的功耗优质因子(FOM)和面积优质因子(FOM_A)分别为0.995pJ.V／Sa和1.55e-11mm~2／Sa，这两个指标达到了近几年收录在JSSC和ISSCC等国际核心刊物的流水线模数转换器的研究成果，能够实现低功耗低硅面积数字视频及SoC嵌入式应用。
Nowadays, DVB-X, Set-top box and high definition TV market are progressively calling for analog-to-digital converter. Since high performance and various functions applied in multimedia systems are required, 10-bit resolution, low power and low cost analog front-end solution handling dense multi-channel operates on a single chip, for example, triple channel application like YUV or RGB capture. As a result of integration of analog and digital circuit with high frequency operation on a single die, high frequency noise is the significant source to degrade the performance of analog-to-digital converter. Low power, low cost and noise free is a hot research on the field of analog-to-digital converter.
This work is focusing on pipelined ADC applied for the digital video with 0.18 um 1.8-V logic CMOS process. Above all, system architecture is defined by matlab, according to system requirements, limited parameters of ADC's sub circuits are modeled mathematically. Secondly, based on process characteristics and spice tools, this work presents the transistor level of pipelined ADC. Finally, layout and chip testing are described. The main contributions can be concluded as following:
1. There are lots of input reference wires connected to sub ADC of every pipeline stage if sub ADC is operated by conventional dynamic comparator so that reference buffer is significantly disturbed by coupling noise between reference wires. Another big problem is that dynamic comparator bumps up frequently under high-speed switching. Conventional solution is to design a RC filter to eliminate kickback noise with large silicon area. A new circuit is proposed in this work. There is not any input reference in dynamic comparator, so the mentioned problems are eliminated.
2. In order to deal with high frequencies inputs, the SHA requires sampling switches with very low and constant on-resistance. A proposed gate-bootstrapping circuit is suitable for low power supply that is 1.8-V power supply used in this work. This circuit decreases the output distortion of switched capacitor circuit. Otherwise, this circuit can be used in logic CMOS process to reduce silicon cost.
3. An important problem, conventional 1.5-bit per-stage pipelined ADC operated in low power supply although there is 0.5 bit redundant correction (RSD) in the range of ± 1/4Vref, is that overall linearity of the converter is degraded by deceasing power supply. This work proposed an interpolated-redundance correction to enhance overall linearity of pipelined ADC. Based on definition of system level and process characteristics, The solution is to insert an interpolated-redundance correction stage, and then convert an input range larger than ± V_(vef) that is accumulated from first stage to the i~(th) stage into norminal range from -V_(vef) and +V_(vef) to avoid the overall distortion.
4. Being compatible with logic CMOS process, MDAC has not high linear MiM capacitor but stack capacitor. Be careful layout extraction to guarantee the overall linearity of analog-to-digital converter.
5. Operational amplifier sharing is based on the fact that in switched-capacitor architecture, the amplifier is used for only one half of a clock cycle, which is during the amplification phase. This way, the same amplifier could be used during different clock phases. This sharing technique can reduce power consumption and silicon area significantly.
This dissertation has two silicon experiments. One is fabricated by 0.5um DPTM CMOS process for 10-bit 1MS/s pipelined ADC. The experimental results prove the error analysis and matlab models suitable for pipelined ADC. The other silicon experiment is fabricated by 0.18um 1.8-V single poly six metals logic CMOS process for 10-bit 100MS/s pipelined ADC. For testing environment, this work sets up testing environment of high-speed ADC and PCB design. These two experiments present two sampling rate 10-bit pipelined ADC with different process, featuring 0.8/0.55 LSB INL and 0.71/0.47 LSB DNL, 9.7/9.3 ENOB, 1.7/0.98 mm~2, 45/63 mW. The second Experiment shows 0.995 pJ. V~2/Sa FOM and 1.55e-11 mm~2/Sa FOM_A, Such the level of performance reach high level of research on pipelined ADC reported in JSSC and ISSCC et al during the recent years and is sufficient for video analog front-end and other receiver operations.
论文主要研究了兼容0.18um 1.8V标准数字逻辑CMOS工艺应用于数字视频领域的流水线模数转换器，通过matlab的分析和优化，建立了系统级的设计框架，然后根据系统需求的采样率、输出分辨率等要求计算出影响模数转换器性能参数的限制指标。再根据工艺参数和EDA工具设计出了晶体管级电路并进行了全电路性能仿真。最后设计了整个模数转换器和测试芯片的布局及版图，完成了整个芯片设计的全部流程。期间主要的研究成果和工作有以下几个方面：
(1) 一般流水线模数转换器常用的动态比较器需要从外部输入参考源与输入信号进行比较然后输出数字域的结果，而本文提出的无输入参考源动态比较器不需要在比较器之外引入参考源而是利用比较器输入对管的差别产生比较阈值，这样减轻了参考源驱动电路的负载，排除了外部电路对动态比较器组成的子模数转换器模块的干扰，另外减少了外部引入参考源走线的数量进而减小了硅面积。
(2) 论文设计的低功耗高速模数转换器使用了1.8V电源，为了减少开关电容电路采样的信号失真，提出了一种新型的开关栅增压电路，使得信号开关器件的栅电压与输入信号无关，保持开关的导通电阻是常数，而且在增压传输路径中的开关导通电阻也与信号无关，从而降低了信号的谐波失真，提高了电路的动态范围。此外，所有的NMOS开关电路的衬底始终接在电路的最低电平上，这样就使该电路可以在普通的0.18um 1.8V数字标准逻辑CMOS工艺上实现，从而降低了芯片制造成本。
(3) 虽然流水线模数转换器的冗余位数字校正(RSD)能够消除一定的误差，但是在低电压应用中，由于信号输入幅度相对较高，因此冗佘校正后的误差仍较大，为了保证整个模数转换器依然有良好的线性度和良好的信噪比，论文提出了内插冗余校正技术。该技术的原理是：由于根据系统定义的噪声限制指标和制造工厂提供的工艺匹配参数可以计算出第i级之后插入一级冗余校正级。因此内插冗余校正级可以把第i级的输出大于正常输入范围数倍之内的信号做为输入(主要是第1级到第i级累积的误差并被MDAC电路放大引起的)然后输出时校正到后级能接受的正常输入范围，这样就可以避免最终模数转换器输出钳位和饱和引起整个ADC的线性度和动态范围的下降。
(4) 为了兼容标准数字逻辑工艺，MDAC中没有使用线性度较高的MiM电容，而是选
择了三明治式金属层间电容(stack capacitor)，这需要通过仔细提取金属层间电容的寄生参数以确保电容的线性度能保证整个ADC的性能。
(5) 为了优化电路的功耗和面积，论文设计的流水线模数转换器采用了运算放大器复用技术，这样可以让相邻的两个MDAC共用一个运算放大器，有效地降低了功耗和面积。
论文进行了两次硅实验，实验一是使用0.5um 2层多晶硅3层金属CMOS混合信号工艺实现了1MHz采样的10位流水线模数转换器电路，验证满足静态参数特性和动态参数性能的设计方法；实验二是使用0.18um 1.8V单层多晶硅6层金属标准逻辑工艺实现了100MHz采样的10位流水线模数转换器。在模数转换器的测试方面主要设计了高速电路应用的PCB板和整个测试平台环境搭建。实验一和实验二的DNL分别为0.71 LSB和0.47LSB；INL分别为0.8LSB和0.55LSB；实现的有效位(ENOB)分别为9.7位(1MHz采样)和9.3位(100MHz采样)；芯片面积分别为1.7mm~2和0.98mm~2；功耗分别为45mW和63mW，其中实验二的功耗优质因子(FOM)和面积优质因子(FOM_A)分别为0.995pJ.V／Sa和1.55e-11mm~2／Sa，这两个指标达到了近几年收录在JSSC和ISSCC等国际核心刊物的流水线模数转换器的研究成果，能够实现低功耗低硅面积数字视频及SoC嵌入式应用。
Nowadays, DVB-X, Set-top box and high definition TV market are progressively calling for analog-to-digital converter. Since high performance and various functions applied in multimedia systems are required, 10-bit resolution, low power and low cost analog front-end solution handling dense multi-channel operates on a single chip, for example, triple channel application like YUV or RGB capture. As a result of integration of analog and digital circuit with high frequency operation on a single die, high frequency noise is the significant source to degrade the performance of analog-to-digital converter. Low power, low cost and noise free is a hot research on the field of analog-to-digital converter.
This work is focusing on pipelined ADC applied for the digital video with 0.18 um 1.8-V logic CMOS process. Above all, system architecture is defined by matlab, according to system requirements, limited parameters of ADC's sub circuits are modeled mathematically. Secondly, based on process characteristics and spice tools, this work presents the transistor level of pipelined ADC. Finally, layout and chip testing are described. The main contributions can be concluded as following:
1. There are lots of input reference wires connected to sub ADC of every pipeline stage if sub ADC is operated by conventional dynamic comparator so that reference buffer is significantly disturbed by coupling noise between reference wires. Another big problem is that dynamic comparator bumps up frequently under high-speed switching. Conventional solution is to design a RC filter to eliminate kickback noise with large silicon area. A new circuit is proposed in this work. There is not any input reference in dynamic comparator, so the mentioned problems are eliminated.
2. In order to deal with high frequencies inputs, the SHA requires sampling switches with very low and constant on-resistance. A proposed gate-bootstrapping circuit is suitable for low power supply that is 1.8-V power supply used in this work. This circuit decreases the output distortion of switched capacitor circuit. Otherwise, this circuit can be used in logic CMOS process to reduce silicon cost.
3. An important problem, conventional 1.5-bit per-stage pipelined ADC operated in low power supply although there is 0.5 bit redundant correction (RSD) in the range of ± 1/4Vref, is that overall linearity of the converter is degraded by deceasing power supply. This work proposed an interpolated-redundance correction to enhance overall linearity of pipelined ADC. Based on definition of system level and process characteristics, The solution is to insert an interpolated-redundance correction stage, and then convert an input range larger than ± V_(vef) that is accumulated from first stage to the i~(th) stage into norminal range from -V_(vef) and +V_(vef) to avoid the overall distortion.
4. Being compatible with logic CMOS process, MDAC has not high linear MiM capacitor but stack capacitor. Be careful layout extraction to guarantee the overall linearity of analog-to-digital converter.
5. Operational amplifier sharing is based on the fact that in switched-capacitor architecture, the amplifier is used for only one half of a clock cycle, which is during the amplification phase. This way, the same amplifier could be used during different clock phases. This sharing technique can reduce power consumption and silicon area significantly.
This dissertation has two silicon experiments. One is fabricated by 0.5um DPTM CMOS process for 10-bit 1MS/s pipelined ADC. The experimental results prove the error analysis and matlab models suitable for pipelined ADC. The other silicon experiment is fabricated by 0.18um 1.8-V single poly six metals logic CMOS process for 10-bit 100MS/s pipelined ADC. For testing environment, this work sets up testing environment of high-speed ADC and PCB design. These two experiments present two sampling rate 10-bit pipelined ADC with different process, featuring 0.8/0.55 LSB INL and 0.71/0.47 LSB DNL, 9.7/9.3 ENOB, 1.7/0.98 mm~2, 45/63 mW. The second Experiment shows 0.995 pJ. V~2/Sa FOM and 1.55e-11 mm~2/Sa FOM_A, Such the level of performance reach high level of research on pipelined ADC reported in JSSC and ISSCC et al during the recent years and is sufficient for video analog front-end and other receiver operations.
引文
[1] Mikael Gustavsson, J. Jacob Wiker, Nianxiong Tan. CMOS data converters for communications [M]. Kluwer Academic Publishers, 2000.
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[1] Rudy van de Plassche. CMOS integrated analog-to-digital and digital-to-analog converters [M]. 2nd Edition, Kluwer Academic publishers, 2003.
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