H.264解码关键算法的VLSI实现研究
摘要
H.264是目前最先进的视频编码标准,与以往的标准相比,H.264在同样的重建图像质量下,其码率能降低50%左右。本文通过深入分析H.264标准的特点,根据熵编码原理,提出了一种基于快速“首位1检测”的指数哥伦布码解码器硬件结构,还提出了一种解码CAVLC的变长分组VLD结构;在片层解码部分,提出了并行的图像标记处理硬件结构及图像序列输出计算和排序的解码机制;在宏块解码部分,提出了一种可重构的帧内预测解码器结构;在去方块滤波部分,提出了一种改进滤波顺序,并采用三级流水线进行滤波处理的滤波器硬件结构。经过验证,本文设计的解码器能够满足H.264标准Baseline档次30帧/秒,分辨率为352×288标准视频序列的实时解码要求。
With the fast developing of very large scale integrated circuit and technology of video encoding and decoding, we have entered a multimedia era. The developing of multimedia has brought more and more conveniences for people, and has made great changes to our lives. The video encoding and decoding technology is the core of multimedia technology. H.264 is a new generation video encoding standard constituted by ISO/IEC and ITU-T. H.264 is the most advanced video encoding standard currently. Contrasting with other video encoding standards, H.264 has higher encoding efficiency and can reduces code rate by fifty percent under same picture reconstructing quality. H.264 adopts many advanced encoding methods to enhance encoding efficiency. H.264 is applied widely in many fields of different speed and quality grades, for example, high definition TV, IP visible telephone, internet video meeting and so on. The application of H.264 baseline profile doesn’t need copyright, it can satisfy application of IP and wireless net primely. H.264 is advanced in the application of transferring multimedia information on internet or mobile net. The usage of very large scale integrated circuit has become the main tide in the development of electronic technology. The integrated circuit chip has less dimension but high stability and low cost. We can conclude that developing H.264 encoder and decoder by integrated circuit technology has significant application prospect.
This subject originates from a scientific and technical project of Shenzhen City. The main object is to design the H.264 hardware decoder which is applied to IP visible telephone and internet video meeting. This paper analyses the H.264 decoding algorithms in detail, proves the feasibility of developing H.264 hardware decoder, and points out that using hardware method to implement H.264 decoder is a simple, reliable and low cost scheme for internet video stream transfer. This paper also implements the hardware architecture design of main decoding algorithms in H.264.
By optimizing the hardware architecture, we have reduced the cost of hardware resource and raised data stream disposing capability. The innovation is shown as below:
1. In H.264, lots of syntaxes in slice layer are encoded in Exp-Golomb code. According to the character of Exp-Golomb encoding algorithm, a first“1”detecting hardware architecture is proposed. Working with a long data sequence buffer, this architecture can reduce processing time and chip area definitely. In H.264, the residual data is encoded by CAVLC. Analyzing the architecture of CAVLC, we separate the code word as two parts: the prefix part and the suffix part. In the prefix part, the leading“0”is determined by the first“1”detector; introducing a Variable Length Group VLD Architecture, the suffix part is derived from the binary tree traversing method. For the subtree of binary tree only includes three grades, this architecture can decrease the mount of traversing nodes, shorten addressing route, and reduce hardware implementation complexity. This architecture also solves the disadvantage of which the decoder has to analyze the input code word bit by bit for the decoder can’t get the length of the current code word beforehand.
2. This paper analyzes the algorithms of H.264 slice decoding process, and proposes a hardware architecture to implement the H.264 slice decoding. We have studied the picture sequence ordering and output principle, and propose corresponding hardware architecture to implement the picture IDR marking, sliding window marking and adaptive marking process. By setting a special Decoded Picture Buffer(DPB) and distributing memory to reference pictures dynamically, and adopting a mapping method to manage the picture ordering, reading and output operations, we can accomplish the picture visiting and management operation more effectively.
3. In this paper, we have analyzed the algorithm character of intra prediction and propose a hardware architecture of intra prediction. In H.264, intra prediction is adopted to wipe off space redundancies of current picture and improve the coding efficiency. According to the characteristics of intra prediction, a reconfigurable hardware decoding architecture of which combine the same operation in different prediction modes is proposed. This architecture compresses the hardware implementation area and also improves the module utilization efficiency.
4. In H.264, deblocking filter is introduced to remove the blocking effect. Analazing the principle of deblocking filter, a hardware filter architecture is proposed to increase filtering efficiency and throughput by the mean of improved filtering sequence, optimized buffer management and pipeline operation. The improved filtering sequence decoding method can reduce the frequency of reading and writing operation between the decoder and memory. Under the architecture of three grade pipeline, decoder can synchronously fill or release memory and finish the filtering operation.
Besides,this paper proposes the hardware architecture of inter prediction, inverse DCT conversion and inverse quantization algorithm. This paper also finishes the development of FPGA hardware validating platform. This platform can accomplish the functions of program downloading and configuration, function validating, data stream transfer and storage. We select the proper devices according to the decoding quality and speed requirement of H.264, so that the platform can accomplish the job of function validating and testing.
The H.264 decoder mentioned in this paper is implemented by VerilogHDL under Xilinx ISE developing environment, and has passed the RTL Level emulation and synthesis under the Cadence Synplify developing environment. The decoder has been validated by Xilinx Spartan3 XC3S2000 on FPGA platform. Under clock frequency of 133MHz, the H.264 decoder meets the quality and speed requirements on basis of baseline profile of H.264 with 30Frames/s and the resolution ratio of 352×288.
With the fast developing of very large scale integrated circuit and technology of video encoding and decoding, we have entered a multimedia era. The developing of multimedia has brought more and more conveniences for people, and has made great changes to our lives. The video encoding and decoding technology is the core of multimedia technology. H.264 is a new generation video encoding standard constituted by ISO/IEC and ITU-T. H.264 is the most advanced video encoding standard currently. Contrasting with other video encoding standards, H.264 has higher encoding efficiency and can reduces code rate by fifty percent under same picture reconstructing quality. H.264 adopts many advanced encoding methods to enhance encoding efficiency. H.264 is applied widely in many fields of different speed and quality grades, for example, high definition TV, IP visible telephone, internet video meeting and so on. The application of H.264 baseline profile doesn’t need copyright, it can satisfy application of IP and wireless net primely. H.264 is advanced in the application of transferring multimedia information on internet or mobile net. The usage of very large scale integrated circuit has become the main tide in the development of electronic technology. The integrated circuit chip has less dimension but high stability and low cost. We can conclude that developing H.264 encoder and decoder by integrated circuit technology has significant application prospect.
This subject originates from a scientific and technical project of Shenzhen City. The main object is to design the H.264 hardware decoder which is applied to IP visible telephone and internet video meeting. This paper analyses the H.264 decoding algorithms in detail, proves the feasibility of developing H.264 hardware decoder, and points out that using hardware method to implement H.264 decoder is a simple, reliable and low cost scheme for internet video stream transfer. This paper also implements the hardware architecture design of main decoding algorithms in H.264.
By optimizing the hardware architecture, we have reduced the cost of hardware resource and raised data stream disposing capability. The innovation is shown as below:
1. In H.264, lots of syntaxes in slice layer are encoded in Exp-Golomb code. According to the character of Exp-Golomb encoding algorithm, a first“1”detecting hardware architecture is proposed. Working with a long data sequence buffer, this architecture can reduce processing time and chip area definitely. In H.264, the residual data is encoded by CAVLC. Analyzing the architecture of CAVLC, we separate the code word as two parts: the prefix part and the suffix part. In the prefix part, the leading“0”is determined by the first“1”detector; introducing a Variable Length Group VLD Architecture, the suffix part is derived from the binary tree traversing method. For the subtree of binary tree only includes three grades, this architecture can decrease the mount of traversing nodes, shorten addressing route, and reduce hardware implementation complexity. This architecture also solves the disadvantage of which the decoder has to analyze the input code word bit by bit for the decoder can’t get the length of the current code word beforehand.
2. This paper analyzes the algorithms of H.264 slice decoding process, and proposes a hardware architecture to implement the H.264 slice decoding. We have studied the picture sequence ordering and output principle, and propose corresponding hardware architecture to implement the picture IDR marking, sliding window marking and adaptive marking process. By setting a special Decoded Picture Buffer(DPB) and distributing memory to reference pictures dynamically, and adopting a mapping method to manage the picture ordering, reading and output operations, we can accomplish the picture visiting and management operation more effectively.
3. In this paper, we have analyzed the algorithm character of intra prediction and propose a hardware architecture of intra prediction. In H.264, intra prediction is adopted to wipe off space redundancies of current picture and improve the coding efficiency. According to the characteristics of intra prediction, a reconfigurable hardware decoding architecture of which combine the same operation in different prediction modes is proposed. This architecture compresses the hardware implementation area and also improves the module utilization efficiency.
4. In H.264, deblocking filter is introduced to remove the blocking effect. Analazing the principle of deblocking filter, a hardware filter architecture is proposed to increase filtering efficiency and throughput by the mean of improved filtering sequence, optimized buffer management and pipeline operation. The improved filtering sequence decoding method can reduce the frequency of reading and writing operation between the decoder and memory. Under the architecture of three grade pipeline, decoder can synchronously fill or release memory and finish the filtering operation.
Besides,this paper proposes the hardware architecture of inter prediction, inverse DCT conversion and inverse quantization algorithm. This paper also finishes the development of FPGA hardware validating platform. This platform can accomplish the functions of program downloading and configuration, function validating, data stream transfer and storage. We select the proper devices according to the decoding quality and speed requirement of H.264, so that the platform can accomplish the job of function validating and testing.
The H.264 decoder mentioned in this paper is implemented by VerilogHDL under Xilinx ISE developing environment, and has passed the RTL Level emulation and synthesis under the Cadence Synplify developing environment. The decoder has been validated by Xilinx Spartan3 XC3S2000 on FPGA platform. Under clock frequency of 133MHz, the H.264 decoder meets the quality and speed requirements on basis of baseline profile of H.264 with 30Frames/s and the resolution ratio of 352×288.
引文
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