SOPC技术在双星定位用户机中的应用
摘要
双星定位系统是我国自主研制开发的区域性有源卫星导航定位系统,可全天候提供快速定位、实时导航、简短通信和精确授时四大功能。目前,该系统已初具规模,在军用和民用导航方面的发挥着日益重要的作用。
近年来,随着微电子技术的进步,大规模逻辑器件的性价比不断提高,使得在单片大规模逻辑器件上实现系统级设计已经成为可能。SOPC技术是Altera公司于2000年提出的一种软硬件协同设计方案,它以IP核为基础,将处理器、存储器、定时器等系统所需要的功能模块都集成到单片FPGA上,构成可编程的片上系统。SOPC技术是一种灵活、高效的SOC解决方案,使得电路设计在设计周期、开发成本、电路规模、功耗、可靠性和硬件升级等多方面达到最优化,代表了嵌入式系统设计的发展方向。
本文根据某车载型双星定位用户机的多芯片(MCU+DSP+FPGA)设计结构,本着将尽可能多的功能模块集中在FPGA中实现的设计思想,提出基于SOPC技术的单芯片实现方案。改进后,FPGA实现的功能除了原有的多通道同步扩频解调外,还包含了DSP和MCU的功能。此外,原方案中在射频部分实现的下变频、成形滤波、BPSK调制也都放入FPGA中进行数字实现。本文采用Altera提供的SOPC设计工具,从IP核的具体应用方面展开研究,完成双星定位用户机方案的实现。具体工作:接收部分完成了正交数字下变频、解扩解调、帧同步、VIterbi译码;发射部分完成了卷积编码、成形滤波和BPSK调制;而原方案中用于控制的MCU芯片,则使用SOPC Builder工具完成了NiosⅡ软核方案的微控制器设计,并移植了μC/OS-ⅡRTOS。原方案中在FPGA实现的载波和伪码同步,以及MCU软件设计,在改进方案中予以保留。限于篇幅,本文不进行讨论。
Double-star positioning system, the independent research and development of China's active regional satellite navigation and positioning system, can provide four major functions: rapid positioning, real-time navigation, shortness communication and precision. At present, the system has begun to take shape, and played an increasingly important role in the military and civilian navigation.
Recently, with the development of microelectronics technology, performance price ratio of large-scale logic devices improved. System-level design in a single logic device has become possible. SOPC, put forward by Altera in 2000, is a new hardware-software co-design technology. Processor, memory, timers and other function modules needed are integrated into a FPGA based on IP core. SOPC is a flexible, cost-effective solution of SOC, making circuit design in the design cycle, development costs, circuit size, power consumption, reliability, and hardware upgrades, etc. achieve optimized. It can be predicted, SOPC technology will be embedded system design trends.
This paper, based on dual-satellite positioning Vehicle terminal’s multi-chip design structure put forward a modified single-chip realization. After improvements, FPGA realizated not only multi-channel synchronous demodulator in original program, but also includes DSP and MCU functionality. In addition, DDC, shaping filter, BPSK modulation which achieved in the RF of original program is also achieved in the FPGA. In this paper, using SOPC design tools, the simulation realization of the SOPC program was completed. Receiving part: DDC, demodulation dispreading, frame synchronization and Viterbi decoding was completed. Launching part: convolution code, BPSK modulation and shaping filter were completed. SOPC Builder tool was used to complete a NiosⅡsoft-core microcontroller was completed to replace MCU chip which used to be controller in the original program. what’s more, transplantation ofμC/OS-ⅡRTOS was completed. The original program in the FPGA to achieve the carrier and PN code synchronization, as well as MCU software design, wad retained in the improvement program. Due to space limitations, do not discuss in this article.
近年来,随着微电子技术的进步,大规模逻辑器件的性价比不断提高,使得在单片大规模逻辑器件上实现系统级设计已经成为可能。SOPC技术是Altera公司于2000年提出的一种软硬件协同设计方案,它以IP核为基础,将处理器、存储器、定时器等系统所需要的功能模块都集成到单片FPGA上,构成可编程的片上系统。SOPC技术是一种灵活、高效的SOC解决方案,使得电路设计在设计周期、开发成本、电路规模、功耗、可靠性和硬件升级等多方面达到最优化,代表了嵌入式系统设计的发展方向。
本文根据某车载型双星定位用户机的多芯片(MCU+DSP+FPGA)设计结构,本着将尽可能多的功能模块集中在FPGA中实现的设计思想,提出基于SOPC技术的单芯片实现方案。改进后,FPGA实现的功能除了原有的多通道同步扩频解调外,还包含了DSP和MCU的功能。此外,原方案中在射频部分实现的下变频、成形滤波、BPSK调制也都放入FPGA中进行数字实现。本文采用Altera提供的SOPC设计工具,从IP核的具体应用方面展开研究,完成双星定位用户机方案的实现。具体工作:接收部分完成了正交数字下变频、解扩解调、帧同步、VIterbi译码;发射部分完成了卷积编码、成形滤波和BPSK调制;而原方案中用于控制的MCU芯片,则使用SOPC Builder工具完成了NiosⅡ软核方案的微控制器设计,并移植了μC/OS-ⅡRTOS。原方案中在FPGA实现的载波和伪码同步,以及MCU软件设计,在改进方案中予以保留。限于篇幅,本文不进行讨论。
Double-star positioning system, the independent research and development of China's active regional satellite navigation and positioning system, can provide four major functions: rapid positioning, real-time navigation, shortness communication and precision. At present, the system has begun to take shape, and played an increasingly important role in the military and civilian navigation.
Recently, with the development of microelectronics technology, performance price ratio of large-scale logic devices improved. System-level design in a single logic device has become possible. SOPC, put forward by Altera in 2000, is a new hardware-software co-design technology. Processor, memory, timers and other function modules needed are integrated into a FPGA based on IP core. SOPC is a flexible, cost-effective solution of SOC, making circuit design in the design cycle, development costs, circuit size, power consumption, reliability, and hardware upgrades, etc. achieve optimized. It can be predicted, SOPC technology will be embedded system design trends.
This paper, based on dual-satellite positioning Vehicle terminal’s multi-chip design structure put forward a modified single-chip realization. After improvements, FPGA realizated not only multi-channel synchronous demodulator in original program, but also includes DSP and MCU functionality. In addition, DDC, shaping filter, BPSK modulation which achieved in the RF of original program is also achieved in the FPGA. In this paper, using SOPC design tools, the simulation realization of the SOPC program was completed. Receiving part: DDC, demodulation dispreading, frame synchronization and Viterbi decoding was completed. Launching part: convolution code, BPSK modulation and shaping filter were completed. SOPC Builder tool was used to complete a NiosⅡsoft-core microcontroller was completed to replace MCU chip which used to be controller in the original program. what’s more, transplantation ofμC/OS-ⅡRTOS was completed. The original program in the FPGA to achieve the carrier and PN code synchronization, as well as MCU software design, wad retained in the improvement program. Due to space limitations, do not discuss in this article.
引文
1刘基余. GPS卫星导航定位原理与方法.科学出版社. 2003:1~16
2 Emil Dziadczyk, Wojciech Zabierowski, Andrzej Napieralski. The Future of the Global Positioning System. Published by Defence Science Board Task force. 2005(11):117~119
3 H Sairo, D Akopian, J Takala. Weighted dilution of precision asquality measure in satellite positioning. IEEE Radar, Sonarand Navigation. 2003, 150 (6):430-436
4 Alison Brown, Marvin May, Barry Tanju. Benefits of Software GPS Receivers for Enhanced Signal Processing. GPS Solutions, 2000,4(1) :56~66.
5 D.M.Akos, T.B.James. Design and Implementation of a Direct Digitization GPS Receiver Front End. IEEE Trans on Microwave Theory and Techniques. 1996,(12): 2334~2339
6丁宏才.全球卫星导航系统的选择不应过分依赖GPS.青岛远洋船员学院学报. 1998,19(2): 70-73
7 P.K.Enge, R.M.Kalafus, M.F.Ruane. Differential Operation of the Global Positioning System. Communications Magazine. 1988,(7):48~60
8 Arjun Singh. Interoperability between GAGAN and other Satellite Based Augmentation Systems. India-United States Conference, on Space Science, Applications and Commerce. Bangalore,India. 2004(7): 21~25
9窦长江.中国的北斗中国的骄傲.中国航天. 2007,(1):9~13
10 John J.etal. GPS Modeling for Designing Aerospace Vehicle Navigation Systems. IEEE Transactions on Aerospace and Electronic System, 1995, (2):695~704
11潘松,黄继业,曾毓. SOPC技术实用教程.清华大学出版社. 2005:1~11
12 X.Meng, G. W.Roberts, A. H.Dodson, E.Cosser, J.Barnes, C.Rizos. Impact of GPS satellite and pseudolite geometry on structural deformation monitoring: analytical and empirical studies. Journal of Geodesy. 2004,77(12):809~822
13林雪原,刘建业.北斗双星定位系统改进及其算法的研究.空间科学学报. 2003,(3):149~154
14吕伟,朱建军.北斗卫星导航系统发展综述.地矿测绘. 2007,23(3):29~32
15李俊锋.“北斗”卫星导航定位系统与全球定位系统之比较分析.北京测绘. 2007,(1):51~53
16杨军,曹冲.我国北斗卫星导航系统应用需求及效益分析.武汉大学学报.2004,(9):775-778
17 S.Miao,S.Wang ec al. The Design and Implementation of the GPS based Real-time Monitoring System for the State of Power Network.International Journals of Power & Energy Systems. 2001,12(3):159-163 .
18 Delahaye Jean-Philippe, Gogniat Guy, Roland Christian, Bomel Pierre. Software Radio and Dynamic Reconfiguration on a DSP/FPGA Platform. Frequenz, 2004, 58(5-6) :152-159
19 Zhuan Ye, Grosspietsch J, Memik G, An FPGA Based All-Digital Transmitter with RadioFrequency Output for Software Defined Radio, Design, Automation&Test in Europe Conference & Exhibition, 2007: 1-6.
20孙国良,丁子明.双星系统工作方式改进的探讨.电子学报. 2001, 29(9):1217-1220
21 Michael Keating, Pierre Bricaud. Reuse methodology Manual for System on a Chip Designs. 3rd ed. USA:Kluwer academic publishers. 2002:217-219
22 Eeckhaut Hendrik, Christiaens Mark, Faes Philipe, Stroobandt Dirk. Improving External Memory Access for Avalon Systems on Programmable Chips. Field Programmable Logic and Application. 2006:27~29
23 Suwartadi Eka, Gunawan Candra, Steijadi P.Ary, et al. First Step toward Internet Based Embedded Control System. 20045th Asian Control Conference. 2004: 1226~1231 .
24李兰英. NiosⅡ嵌入式软核SOPC设计原理及应用.北京航空航天大学出版社. 2006:15~26
25 Cardells-Tormo F, Valls-Coquillat A. Optimized FPGA-Implementation of Quadrature DDS, Circuits and Systems, 2002: 369~372
26 Aakko Kairus, Juha Forsten, Matti Tommiska, Jorma Skytta, Bridging the Gap between Future Software and Hardware Engineers: A Case Study Using the Nios Soft-core Processor. 33rd ASEE/IEEE Frontiers in Education Conference, 2003:546~548
27 Gai, P., Lipari, G., Di Natale, M. Support for multiprocessor synchronization and resourcesharing in system-on-programmabl chips with softcores SOC Conference .2005. Proceedings. IEEE International. 2005,:109~110
28 Jeff Garrison, IP Enabling SOPC-Technology Information, Electronic News. 2001:28~31
29 Yan Yong-ming, Zeng Yun. USB dual-mode function IP core development. Journal of Electronic Science and Technology of China, 2006, (1):59-62.
30 Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne. Customizing 16-bit floating point instructions on a NIOSII processor for FPGA image and mediaprocessing .IEEE, 2005, :61~66 .
31邵舒渊,卢选民. SOPC系统设计入门教程.西北工业大学出版社. 2006:1~21
32 P. Moore, M. McLoone, S.Sezer. Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera NiosⅡProcessor. IEEE, 2005:95~98 .
33张欣.扩频通信数字基带信号处理算法及其VLSI实现.科学出版社2004:76~92
34 Mitola J. The Software Radio Architecture. IEEE Communication Magazine, 1995, (5) :26-38
35郭南,洪福明,李乐民.软限幅效应、量化阶数及取样间隔对直扩数字匹配滤波性能的影响.通信学报. 1996,17(1):12~17
36 Myung-SoonKing, Jin-GyunChung. Look-up-table based pulse-shaping Filter. Electronics Letters. 2000, 36(17):1505~1507
37杨贞斌,乌江兴.一种数字化基带成形实现新方法:基于码元间隔的定长滑动窗算法.通信学报. 1999, 2(6): 40~44
38王建新,蒋立平,吉训生,陈小梅.基带成形滤波器的FPGA实现.电讯技术. 2001,(5):43~45
39刘进.高动态下码元快速同步在北斗用户机中的应用研究.武汉理工大学学位论文. 2007:21~32
40 Vails.J, Peiro M.M, Sansaloni T. Design and FPGA implementation of digit-serial FIR filters. Electronics,Circuits and Systems, 2005 IEEE international Conference on. Volume 2 :7-10 .
41 Huang W, Krishnan.V, Allred.D, Heejong Yoo.“Design analysis of a distributed Arithmetic adaptive FIR Filter on a FPGA”.Signals, Systems and Computers. 2003, Volume1: 9-12
42 Esmael H Dinan, Bijan Jabbari.Spreading Codes for Direct Sequence CDMA and Wide Band CDMA Cellular Networks. IEEE Communications Magazine. 1998,36(9):48-53.
43宫剑,毕红军,贾怀义. Kasami扩频序列的研究.北方交通大学学报. 2001, 6(3). 103-106
44罗常青,安建平,沈业兵.采用(2,1,7)卷积码+QPSK的中频调制解调系统的FPGA实现.电子技术应用. 2005(10):78-80
45 Page K, Chau P M. Improved architectures for the add-compare-select Operation in long constraint length Viterbi Decoding. IEEE Journal of Solid-State Circuits, 1998, 33(1) :151-155
46宣建华,姚庆栋.高速Viterbi处理器——流水式处理并行结构.通信学报. 1995,16(1):94-100
47管立新.基于IP Core的Viterbi高速译码器测试.电子质量. 2006(1). 21-23
48 K. Ramamritham, K. Arya, G. Fohler. System Software for Embedded Applications. VLSI Design. 2004:12~14
49 Yang Yang, Yan Wenjun. Software Design of an intelligent Car System Based onμC/OS-Ⅱ. Proceeedings of the 25th Chinese Control Conference. Harbin, Heilongjiang. August 2006:7-11
50张宣.嵌入式实时操作系统μC/OS-Ⅱ在北斗导航接收机中的应用.合肥工业大学硕士论文. 2007:47~56
51 P. Moore, M. McLoone, S.Sezer. Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera NiosⅡProcessor. IEEE, 2005,8(13):95~98
2 Emil Dziadczyk, Wojciech Zabierowski, Andrzej Napieralski. The Future of the Global Positioning System. Published by Defence Science Board Task force. 2005(11):117~119
3 H Sairo, D Akopian, J Takala. Weighted dilution of precision asquality measure in satellite positioning. IEEE Radar, Sonarand Navigation. 2003, 150 (6):430-436
4 Alison Brown, Marvin May, Barry Tanju. Benefits of Software GPS Receivers for Enhanced Signal Processing. GPS Solutions, 2000,4(1) :56~66.
5 D.M.Akos, T.B.James. Design and Implementation of a Direct Digitization GPS Receiver Front End. IEEE Trans on Microwave Theory and Techniques. 1996,(12): 2334~2339
6丁宏才.全球卫星导航系统的选择不应过分依赖GPS.青岛远洋船员学院学报. 1998,19(2): 70-73
7 P.K.Enge, R.M.Kalafus, M.F.Ruane. Differential Operation of the Global Positioning System. Communications Magazine. 1988,(7):48~60
8 Arjun Singh. Interoperability between GAGAN and other Satellite Based Augmentation Systems. India-United States Conference, on Space Science, Applications and Commerce. Bangalore,India. 2004(7): 21~25
9窦长江.中国的北斗中国的骄傲.中国航天. 2007,(1):9~13
10 John J.etal. GPS Modeling for Designing Aerospace Vehicle Navigation Systems. IEEE Transactions on Aerospace and Electronic System, 1995, (2):695~704
11潘松,黄继业,曾毓. SOPC技术实用教程.清华大学出版社. 2005:1~11
12 X.Meng, G. W.Roberts, A. H.Dodson, E.Cosser, J.Barnes, C.Rizos. Impact of GPS satellite and pseudolite geometry on structural deformation monitoring: analytical and empirical studies. Journal of Geodesy. 2004,77(12):809~822
13林雪原,刘建业.北斗双星定位系统改进及其算法的研究.空间科学学报. 2003,(3):149~154
14吕伟,朱建军.北斗卫星导航系统发展综述.地矿测绘. 2007,23(3):29~32
15李俊锋.“北斗”卫星导航定位系统与全球定位系统之比较分析.北京测绘. 2007,(1):51~53
16杨军,曹冲.我国北斗卫星导航系统应用需求及效益分析.武汉大学学报.2004,(9):775-778
17 S.Miao,S.Wang ec al. The Design and Implementation of the GPS based Real-time Monitoring System for the State of Power Network.International Journals of Power & Energy Systems. 2001,12(3):159-163 .
18 Delahaye Jean-Philippe, Gogniat Guy, Roland Christian, Bomel Pierre. Software Radio and Dynamic Reconfiguration on a DSP/FPGA Platform. Frequenz, 2004, 58(5-6) :152-159
19 Zhuan Ye, Grosspietsch J, Memik G, An FPGA Based All-Digital Transmitter with RadioFrequency Output for Software Defined Radio, Design, Automation&Test in Europe Conference & Exhibition, 2007: 1-6.
20孙国良,丁子明.双星系统工作方式改进的探讨.电子学报. 2001, 29(9):1217-1220
21 Michael Keating, Pierre Bricaud. Reuse methodology Manual for System on a Chip Designs. 3rd ed. USA:Kluwer academic publishers. 2002:217-219
22 Eeckhaut Hendrik, Christiaens Mark, Faes Philipe, Stroobandt Dirk. Improving External Memory Access for Avalon Systems on Programmable Chips. Field Programmable Logic and Application. 2006:27~29
23 Suwartadi Eka, Gunawan Candra, Steijadi P.Ary, et al. First Step toward Internet Based Embedded Control System. 20045th Asian Control Conference. 2004: 1226~1231 .
24李兰英. NiosⅡ嵌入式软核SOPC设计原理及应用.北京航空航天大学出版社. 2006:15~26
25 Cardells-Tormo F, Valls-Coquillat A. Optimized FPGA-Implementation of Quadrature DDS, Circuits and Systems, 2002: 369~372
26 Aakko Kairus, Juha Forsten, Matti Tommiska, Jorma Skytta, Bridging the Gap between Future Software and Hardware Engineers: A Case Study Using the Nios Soft-core Processor. 33rd ASEE/IEEE Frontiers in Education Conference, 2003:546~548
27 Gai, P., Lipari, G., Di Natale, M. Support for multiprocessor synchronization and resourcesharing in system-on-programmabl chips with softcores SOC Conference .2005. Proceedings. IEEE International. 2005,:109~110
28 Jeff Garrison, IP Enabling SOPC-Technology Information, Electronic News. 2001:28~31
29 Yan Yong-ming, Zeng Yun. USB dual-mode function IP core development. Journal of Electronic Science and Technology of China, 2006, (1):59-62.
30 Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne. Customizing 16-bit floating point instructions on a NIOSII processor for FPGA image and mediaprocessing .IEEE, 2005, :61~66 .
31邵舒渊,卢选民. SOPC系统设计入门教程.西北工业大学出版社. 2006:1~21
32 P. Moore, M. McLoone, S.Sezer. Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera NiosⅡProcessor. IEEE, 2005:95~98 .
33张欣.扩频通信数字基带信号处理算法及其VLSI实现.科学出版社2004:76~92
34 Mitola J. The Software Radio Architecture. IEEE Communication Magazine, 1995, (5) :26-38
35郭南,洪福明,李乐民.软限幅效应、量化阶数及取样间隔对直扩数字匹配滤波性能的影响.通信学报. 1996,17(1):12~17
36 Myung-SoonKing, Jin-GyunChung. Look-up-table based pulse-shaping Filter. Electronics Letters. 2000, 36(17):1505~1507
37杨贞斌,乌江兴.一种数字化基带成形实现新方法:基于码元间隔的定长滑动窗算法.通信学报. 1999, 2(6): 40~44
38王建新,蒋立平,吉训生,陈小梅.基带成形滤波器的FPGA实现.电讯技术. 2001,(5):43~45
39刘进.高动态下码元快速同步在北斗用户机中的应用研究.武汉理工大学学位论文. 2007:21~32
40 Vails.J, Peiro M.M, Sansaloni T. Design and FPGA implementation of digit-serial FIR filters. Electronics,Circuits and Systems, 2005 IEEE international Conference on. Volume 2 :7-10 .
41 Huang W, Krishnan.V, Allred.D, Heejong Yoo.“Design analysis of a distributed Arithmetic adaptive FIR Filter on a FPGA”.Signals, Systems and Computers. 2003, Volume1: 9-12
42 Esmael H Dinan, Bijan Jabbari.Spreading Codes for Direct Sequence CDMA and Wide Band CDMA Cellular Networks. IEEE Communications Magazine. 1998,36(9):48-53.
43宫剑,毕红军,贾怀义. Kasami扩频序列的研究.北方交通大学学报. 2001, 6(3). 103-106
44罗常青,安建平,沈业兵.采用(2,1,7)卷积码+QPSK的中频调制解调系统的FPGA实现.电子技术应用. 2005(10):78-80
45 Page K, Chau P M. Improved architectures for the add-compare-select Operation in long constraint length Viterbi Decoding. IEEE Journal of Solid-State Circuits, 1998, 33(1) :151-155
46宣建华,姚庆栋.高速Viterbi处理器——流水式处理并行结构.通信学报. 1995,16(1):94-100
47管立新.基于IP Core的Viterbi高速译码器测试.电子质量. 2006(1). 21-23
48 K. Ramamritham, K. Arya, G. Fohler. System Software for Embedded Applications. VLSI Design. 2004:12~14
49 Yang Yang, Yan Wenjun. Software Design of an intelligent Car System Based onμC/OS-Ⅱ. Proceeedings of the 25th Chinese Control Conference. Harbin, Heilongjiang. August 2006:7-11
50张宣.嵌入式实时操作系统μC/OS-Ⅱ在北斗导航接收机中的应用.合肥工业大学硕士论文. 2007:47~56
51 P. Moore, M. McLoone, S.Sezer. Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera NiosⅡProcessor. IEEE, 2005,8(13):95~98