无线传感器网络节点基带处理器关键电路的低功耗设计
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摘要
能量受限，如何降低节点功耗，是无线传感器网络需要解决的首要问题。论文主要研究了节点无线通信模块中基带处理器的典型单元Viterbi译码器和DS／BPSK扩频电路的低功耗设计：
对(3，1，9)Viterbi译码器各子单元分别提出了具有针对性的低功耗设计方法：在设计BMU时，提出根据各分支预编码的对称性，可以节约大概80％的硬件开销；在设计ACSU时，提出采用预计算方法，可以将输入对电路开关活动性的影响降低12.5％以上；在设计PMU时，针对混合结构的原位更新方式，提出采用状态映射地址SMA，来实现新状态在下一轮加比选运算中和存储单元物理地址PA的对应，并通过标识最高位的方法，来减少SMA更新引起的功耗，相比于乒乓方式，功耗可节约46％左右；在设计SMU时，提出通过引入指针，标识最高位以及设置终止信号的方式，可以有效阻止无用寄存器的更新，和传统RE结构相比，可降低约30％的电路功耗。
由于现有扩频芯片并不适合无线传感器网络工作的特点，而前几代节点端机分别采用DSP或FPGA来实现DS／BPSK技术，这势必会引起较大的功耗，未来节点发展的趋势是SoC，基于此，我们拟研制系列专用于传感器节点的协议芯片，论文中设计实现的国内首颗传感器节点DS／BPSK扩频芯片就是其中之一，该芯片采用TSMC 0.25μm CMOS工艺，芯片面积约2×2.2 mm~2，在3.3V电源电压，输入时钟58.5MHz条件下，工作电流约6mA，和原来的DSP及FPGA实现方式相比，功耗得到明显降低。
针对测得DS／BPSK芯片毛刺功耗较高的情况，论文对电路毛刺产生和传播的原因进行了分析，对抑制RTL级电路控制信号和数据信号毛刺的技术，以及寄存器门控时钟的方法进行了研究，提出采用基于静态CMOS逻辑的栅控方式，来对DS／BPSK扩频芯片非关键路径上频繁出现毛刺的单元进行改进。
论文工作源自中科院知识创新项目CDMA无线传感器网络，相应成果有助于促进节点向微型化、低功耗方向发展，在实用性方面，具有一定的参考价值。
Since energy efficiency is a key concern in the research work of WSN, it is important to design a low power node. So the dissertation puts the emphasis on the low power design of the Viterbi decoder (VD) and the BPSK direct sequence spread spectrum (DSSS) which both belong to the baseband processing.
In the dissertation, first, we presented a low power implementation of a VD (rate 1/3 and constraint length 9), which was achieved by applying some algorithmic modification on the conventional structure, and then employing several low power design techniques; according to the symmetric characteristics of the generator polynomials, the complexity of branch metric unit (BMU) could be simplified about 80%; based on the pre-computation technique, the transition activity of the components in add-compare- select (ACS) could be reduced more than 12.5%; during the in-place path metric update, a state mapping address (SMA) was proposed to make the newly computed path metric write into the correct physical address (PA), and comparing with the ping-pong structure, approximately 46% power dissipation of SMA update could be reduced by the MSB flag; also with the MSB flag and the assigned pointer, the update operations of survivor memory unit (SMU) could be minimized; in addition, with a termination signal to prevent the useless activities in SMU, the power dissipation could be decreased around 30%.
As current spread spectrum chips were not completely fit for the characteristics of WSN, the former series node devices had to realize the DS/BPSK technique with DSP or FPGA, which led to high power consumption for the inefficiencies; since SoC was the trend of node progressing, therefore, we hoped to develop a series of chips that were special for sensor node, and the first DS/BPSK chip interiorly was one of them, which was fabricated in TSMC 0.25μm CMOS process technology with the area 2×2 mm~2; and the active current in chip was about 6mA at 3.3V and 58.5MHz which was obviously less than the one with DSP or FPGA.
Due to the high glitch power dissipation in chip test, we analyzed the reason for glitch generation and propagation, and studied the techniques that attempt to reduce glitches in control or data signals, as well as methods that could decrease register power consumption by gated clock; by comparing various gate triggerings with MOS transistor, we modified the design of some modules in DS/BPSK chip, which belonged to the non-critical path and appeared glitches frequently.
Finally, the motivation of the dissertation originated from "CDMA wireless sensor network" which belonged to Intellectual Innovation Project of Chinese Academy of Sciences; some work of the dissertation could be help to accelerate the development of WSN node towards miniaturization and low power way.
对(3，1，9)Viterbi译码器各子单元分别提出了具有针对性的低功耗设计方法：在设计BMU时，提出根据各分支预编码的对称性，可以节约大概80％的硬件开销；在设计ACSU时，提出采用预计算方法，可以将输入对电路开关活动性的影响降低12.5％以上；在设计PMU时，针对混合结构的原位更新方式，提出采用状态映射地址SMA，来实现新状态在下一轮加比选运算中和存储单元物理地址PA的对应，并通过标识最高位的方法，来减少SMA更新引起的功耗，相比于乒乓方式，功耗可节约46％左右；在设计SMU时，提出通过引入指针，标识最高位以及设置终止信号的方式，可以有效阻止无用寄存器的更新，和传统RE结构相比，可降低约30％的电路功耗。
由于现有扩频芯片并不适合无线传感器网络工作的特点，而前几代节点端机分别采用DSP或FPGA来实现DS／BPSK技术，这势必会引起较大的功耗，未来节点发展的趋势是SoC，基于此，我们拟研制系列专用于传感器节点的协议芯片，论文中设计实现的国内首颗传感器节点DS／BPSK扩频芯片就是其中之一，该芯片采用TSMC 0.25μm CMOS工艺，芯片面积约2×2.2 mm~2，在3.3V电源电压，输入时钟58.5MHz条件下，工作电流约6mA，和原来的DSP及FPGA实现方式相比，功耗得到明显降低。
针对测得DS／BPSK芯片毛刺功耗较高的情况，论文对电路毛刺产生和传播的原因进行了分析，对抑制RTL级电路控制信号和数据信号毛刺的技术，以及寄存器门控时钟的方法进行了研究，提出采用基于静态CMOS逻辑的栅控方式，来对DS／BPSK扩频芯片非关键路径上频繁出现毛刺的单元进行改进。
论文工作源自中科院知识创新项目CDMA无线传感器网络，相应成果有助于促进节点向微型化、低功耗方向发展，在实用性方面，具有一定的参考价值。
Since energy efficiency is a key concern in the research work of WSN, it is important to design a low power node. So the dissertation puts the emphasis on the low power design of the Viterbi decoder (VD) and the BPSK direct sequence spread spectrum (DSSS) which both belong to the baseband processing.
In the dissertation, first, we presented a low power implementation of a VD (rate 1/3 and constraint length 9), which was achieved by applying some algorithmic modification on the conventional structure, and then employing several low power design techniques; according to the symmetric characteristics of the generator polynomials, the complexity of branch metric unit (BMU) could be simplified about 80%; based on the pre-computation technique, the transition activity of the components in add-compare- select (ACS) could be reduced more than 12.5%; during the in-place path metric update, a state mapping address (SMA) was proposed to make the newly computed path metric write into the correct physical address (PA), and comparing with the ping-pong structure, approximately 46% power dissipation of SMA update could be reduced by the MSB flag; also with the MSB flag and the assigned pointer, the update operations of survivor memory unit (SMU) could be minimized; in addition, with a termination signal to prevent the useless activities in SMU, the power dissipation could be decreased around 30%.
As current spread spectrum chips were not completely fit for the characteristics of WSN, the former series node devices had to realize the DS/BPSK technique with DSP or FPGA, which led to high power consumption for the inefficiencies; since SoC was the trend of node progressing, therefore, we hoped to develop a series of chips that were special for sensor node, and the first DS/BPSK chip interiorly was one of them, which was fabricated in TSMC 0.25μm CMOS process technology with the area 2×2 mm~2; and the active current in chip was about 6mA at 3.3V and 58.5MHz which was obviously less than the one with DSP or FPGA.
Due to the high glitch power dissipation in chip test, we analyzed the reason for glitch generation and propagation, and studied the techniques that attempt to reduce glitches in control or data signals, as well as methods that could decrease register power consumption by gated clock; by comparing various gate triggerings with MOS transistor, we modified the design of some modules in DS/BPSK chip, which belonged to the non-critical path and appeared glitches frequently.
Finally, the motivation of the dissertation originated from "CDMA wireless sensor network" which belonged to Intellectual Innovation Project of Chinese Academy of Sciences; some work of the dissertation could be help to accelerate the development of WSN node towards miniaturization and low power way.
引文
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