音频低电压连续时间Sigma-Delta模数转换器研究与实现
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摘要
本文针对助听器的应用,依托国家863计划重点项目,设计了一款1-V、16-bit、20-KHz信号带宽的连续时间Sigma-Delta ADC。和采用开关电容的离散时间Sigma-Delta ADC相比,连续时间方案有着明显的低功耗优势,并且还有固有的抗混叠特性。本设计的调制器采用单比特量化,128倍过采样,四阶前馈结构,用有源RC积分器来实现,设计了在低电压下工作的两级class A/AB型运放,引入了一个固定延时吸收量化器信号相关延时。数字降采样滤波器采用梳状滤波器级联两级半带滤波器的结构,其中梳状滤波器采用8-4级联方式实现32倍降采样,所有子滤波器都为FIR滤波器,采用了采样转置和多相采样技术,以降低了功耗。
本文设计的Sigma-Delta调制器采用SMIC的0.13-μm Mixed Signal CMOS工艺实现,芯片的核心面积为0.64×0.361mm2,功耗约为110μW。后仿真结果表明,芯片在1-V电源电压下,5.12 MHz采用时钟下,20 KHz带宽范围内,SNDR可以达到最高108 dB, SFDR最高可以达到110.5 dB。
Basing on the National 863's Plan, this paper presents aⅠ-Ⅴ,16-bit,20-KHz bandwidth continuous-time Sigma-Delta modulator for hearing-aid applications. Compared with discrete-time sigma-delta modulatours implemented with switch-capacity technology, continuous-time sigma-delta modulators have the advantage of a lower power consumption and inherent anti-alias filtering. The presented modulator utilizes an 1-bit quantization 4th order feed-forward loop with a OSR of 128. It is implemented in active-RC integrators. A 2-stage class A/AB amplifier is designed to meet the low voltage supply requirement. A constant delay is introduced to solve the signal-dependent delay. The digital decimation filter is realized with a cascade combination of a comb filter and two half-band filter. The comb filter is implemented as a 8-4 cascade structure to realize a down sampling rate of 32. All the filter is FIR filter with utilizing sampling transposing and poly phase sampling technologies, so that the power consumption can be reduced.
The modulator is realized by SMIC0.13-μm Mixed Signal CMOS process, the core chip size is about 0.64x0.36 mm2 and the power consumption is about 110μW. The chip can work underl V, clocking at 5.12 MHz with a bandwidth of 20KHz. The modulator can achieves a peek SNDR of 108 dB and a peek SFDR of 110.5 dB.
本文设计的Sigma-Delta调制器采用SMIC的0.13-μm Mixed Signal CMOS工艺实现,芯片的核心面积为0.64×0.361mm2,功耗约为110μW。后仿真结果表明,芯片在1-V电源电压下,5.12 MHz采用时钟下,20 KHz带宽范围内,SNDR可以达到最高108 dB, SFDR最高可以达到110.5 dB。
Basing on the National 863's Plan, this paper presents aⅠ-Ⅴ,16-bit,20-KHz bandwidth continuous-time Sigma-Delta modulator for hearing-aid applications. Compared with discrete-time sigma-delta modulatours implemented with switch-capacity technology, continuous-time sigma-delta modulators have the advantage of a lower power consumption and inherent anti-alias filtering. The presented modulator utilizes an 1-bit quantization 4th order feed-forward loop with a OSR of 128. It is implemented in active-RC integrators. A 2-stage class A/AB amplifier is designed to meet the low voltage supply requirement. A constant delay is introduced to solve the signal-dependent delay. The digital decimation filter is realized with a cascade combination of a comb filter and two half-band filter. The comb filter is implemented as a 8-4 cascade structure to realize a down sampling rate of 32. All the filter is FIR filter with utilizing sampling transposing and poly phase sampling technologies, so that the power consumption can be reduced.
The modulator is realized by SMIC0.13-μm Mixed Signal CMOS process, the core chip size is about 0.64x0.36 mm2 and the power consumption is about 110μW. The chip can work underl V, clocking at 5.12 MHz with a bandwidth of 20KHz. The modulator can achieves a peek SNDR of 108 dB and a peek SFDR of 110.5 dB.
引文
[1]M. Dessouky and A. Kaiser, "very low-voltage digital-audio AE modulator with 88-dB dynamic range using local switch bootstrapping" IEEE Journal of Solid-State Circuits, vol.36, no.3, pp.349-355, Mar.2001.
[2]J.Sauerbrey, T.Tille, D.Schmitt-Landsiedel and R.Thewes, "A 0.7-V MOSFET-only switched-opamp Σ△. modulator in standard digital CMOS technology," IEEE Journal of Solid-State Circuits, vol.37, no.12, pp.1662-1669, Dec.2002.
[3]K. P. Pun, S. Chatterjee, and P. Kinget, "0.5-V analog circuit techniques and their application in OTA and filter design," IEEE J. Solid-State Circuits, vol.40, no.12, pp.2373-2387, Dec.2005.
[4]K. P. Pun, S. Chatterjee, and P. R. Kinget, "A 0.5-V 74-dB SNDR 25-kHz continuous-time delta-sigma modulator with a return-to-open DAC," IEEE Journal of Solid-State Circuits, vol.42, no.3, pp.496-507, Mar.2007.
[5]F. Gerfers, M. Ortmanns, and Y. Manoli, "A 1.5-V 12-bit power-efficient continuous-time third-order modulator," IEEE Journal of Solid-State Circuits, vol.38, no.8, pp.1343-1352, Aug.2003.
[6]S. Pavan, N. Krishnapura, R. Pandarinathan, and P. sankar, "A power optimized continuous-time △Σ ADC for audio applications," IEEE Journal of Solid-State Circuits, vol.43, no.2, pp.351-360, Feb.2008.
[7]E. van der Zwan and E. Dijkmans, "A 0.2-mW CMOS Σ△ modulator for speech coding with 80 dB dynamic range," IEEE Journal of Solid-State Circuits, vol.31, no.12, pp.1873-1880, Dec.1996.
[8]D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc.,1997.
[9]T. B. Cho and P. R. Gray, "A 10-b 20-Msample/s 35-mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp.166-172, Mar. 1995.
[10]M. Ortmanns, F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion Fundamentals, Performance Limits and Robust Implementations [M]. Springer Series in advanced microelectronics.
[11]S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters:Theory, Design, and Simulation. New York:IEEE Press,1996.
[12]Maurits Ortmanns and Friedel Gerfers, Continuous-Time Sigma-delta A/D conversion, Fundamentals, Performance Limits and Robust Implementations, Springer,2005.
[13]Willy Sansen, Analog Design Essentials, Springer,2006
[14]A.M. Durham, J.B.Hughes, and W.Redman-White. "Circuit architectures for high linearity monolithic continuous-time filtering," IEEE Trans. Circuits and Systems-Ⅱ, vol.39, no.39, pp.651-657, Sept.1992
[15]J.M.Khoury and Y.P.Tsividis, "Analysis and compensation of high-frequency effects in integrated MOSFET-C continuous-time filters" IEEE Trans. Circuits and Systems, vol.CAS-34, no.8, pp.862-875. Aug.1987
[16]J.I.Osa, A.Carlosena, and A.J.Lopez-Martin, " MOSFET-C filter with on-chip tuning and wide programming range" IEEE Trans. Circuits and Systems-Ⅱ, vol.48, no.10, pp.944-951, Oct.2001
[17]B.Nauta, "A CMOS transconductance-C filter technique for very high frequencies" IEEE Journal of Solid-State Circuits,Vol.27, No.2, pp.142-153, Feb.1992
[18]Z. Czarnul, S. C. Fang, and Y. Tsividis, "Improving linearity in MOS fully-integrated continuous-time filters," IEEE ISCAS.1986, pp.1169-1172
[19]J.Silva-Martinez, M. S. J. Steyaert, and W. M. C, Sansen, "A large-signal very low-distortion transconductor for high-frequency continuous-time filters" IEEE Journal of Solid-State Circuits, Vol.26, No.7, pp.946-955, July 1991.
[20]B.lazavi, Design Of Analog Cmos Integrated Circuits, McGraw-Hill Education, Europe
[21]P. Gray and R. Mayer, Analysis and Design of Analog Integrated Circuits. New York:Wiley,1993.
[22]F.Medeiro, B.Perez-Verdu, and A.Rodriguez-Vazquez, Top-Down Design of High Performance Sigma-Delta Modulators. Norwell, MA:Kluwer,1999.
[23]S. Pavan and Y. Tsividis, High Frequency Continuous-Time Filters in Digital CMOS Process. Norwell, MA:Kluwer,2000.
[24]J. A. Cherry and W. M. Snelgrove,.Excess Loop Delay in Continuous-Time Delta-Sigma Modulator, IEEE Trans. Circuits & System Ⅱ, vol.46, pp.376-389, Apr.1999.
[25]Zhimin Li, Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator with 2.5MHz Signal Bandwidth, PhD Thesis, Oregon State University (2006)
[26]Shouli yan, Baseband Continuous-Time Sigma-Delta Analog-to-Digital Conversion for ADSL Applications, PhD thesis, Texas A&M University,2002.
[27]James A. Cherry and W. Martin Snelgrove, CONTINUOUS-TIME DELTA-SIGMA MODULATORS FOR HIGH-SPEED A/D CONVERSION, Theory, Practice and FundamentalPerformance Limits, Kluwer academic publishers,2002
[28]李怡然CMOS宽带连续时间Sigma-Delta调制器,复旦大学硕士论文,2008年5月
[29]D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, "A self-calibration technique for monolithic high-resolution D/A converters," IEEE Journal of Solid-State Circuits, vol.24, no.6, pp.1517-1522, Dec.1989.
[30]R. Schreier, GC. Temes Delta-Sigma data converters[M]北京：科学出版社,2007.
[31]T. B. Cho and P. R. Gray, "A 10-b 20-Msample/s 35-mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp.166-172, Mar. 1995.
[32]Yao L B, Steyaert M S J, Sansen W. "A 1-V 140-uW 88-dB audio sigma-delta modulator in 90-nm CMOS" [J], IEEE JSSC,2004,39(11):1809-1818.
[33]S. Rabii and B.Wooley, "A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS," IEEE J. Solid-State Circuits, vol.32, no.6, pp.783-796, Jun.1997.
[34]H Aboushady, Y Dumonteix "Efficient Polyphase Decomposition of Comb Decimation Filters in Analog-to-Digital Converters", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Ⅱ:ANALOG AND DIGITAL SIGNAL PROCESSING VOL.48, NO.10, OCTOBER 2001
[35]J.C.Candy, "Decimation for Sigma Delta Modulation," IEEE Transactions on Communication, January 1986
[36]A.V.Oppenheim, "Discrete-Time Signal Processing," Prentice-Hall Inc.,1999
[37]S. Pavan,N. Krishnapura,R. Pandarinathan, et al. A power optimized continuous-time AE ADC for audio applications [J]. IEEE JSSC,2008,43(2): 351-360.
[38]J. Roh,S. Byun,Y. Choi, et al. A 0.9-V 60-μW 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range [J]. IEEE JSSC,2008,43(3):361-370.
[2]J.Sauerbrey, T.Tille, D.Schmitt-Landsiedel and R.Thewes, "A 0.7-V MOSFET-only switched-opamp Σ△. modulator in standard digital CMOS technology," IEEE Journal of Solid-State Circuits, vol.37, no.12, pp.1662-1669, Dec.2002.
[3]K. P. Pun, S. Chatterjee, and P. Kinget, "0.5-V analog circuit techniques and their application in OTA and filter design," IEEE J. Solid-State Circuits, vol.40, no.12, pp.2373-2387, Dec.2005.
[4]K. P. Pun, S. Chatterjee, and P. R. Kinget, "A 0.5-V 74-dB SNDR 25-kHz continuous-time delta-sigma modulator with a return-to-open DAC," IEEE Journal of Solid-State Circuits, vol.42, no.3, pp.496-507, Mar.2007.
[5]F. Gerfers, M. Ortmanns, and Y. Manoli, "A 1.5-V 12-bit power-efficient continuous-time third-order modulator," IEEE Journal of Solid-State Circuits, vol.38, no.8, pp.1343-1352, Aug.2003.
[6]S. Pavan, N. Krishnapura, R. Pandarinathan, and P. sankar, "A power optimized continuous-time △Σ ADC for audio applications," IEEE Journal of Solid-State Circuits, vol.43, no.2, pp.351-360, Feb.2008.
[7]E. van der Zwan and E. Dijkmans, "A 0.2-mW CMOS Σ△ modulator for speech coding with 80 dB dynamic range," IEEE Journal of Solid-State Circuits, vol.31, no.12, pp.1873-1880, Dec.1996.
[8]D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc.,1997.
[9]T. B. Cho and P. R. Gray, "A 10-b 20-Msample/s 35-mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp.166-172, Mar. 1995.
[10]M. Ortmanns, F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion Fundamentals, Performance Limits and Robust Implementations [M]. Springer Series in advanced microelectronics.
[11]S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters:Theory, Design, and Simulation. New York:IEEE Press,1996.
[12]Maurits Ortmanns and Friedel Gerfers, Continuous-Time Sigma-delta A/D conversion, Fundamentals, Performance Limits and Robust Implementations, Springer,2005.
[13]Willy Sansen, Analog Design Essentials, Springer,2006
[14]A.M. Durham, J.B.Hughes, and W.Redman-White. "Circuit architectures for high linearity monolithic continuous-time filtering," IEEE Trans. Circuits and Systems-Ⅱ, vol.39, no.39, pp.651-657, Sept.1992
[15]J.M.Khoury and Y.P.Tsividis, "Analysis and compensation of high-frequency effects in integrated MOSFET-C continuous-time filters" IEEE Trans. Circuits and Systems, vol.CAS-34, no.8, pp.862-875. Aug.1987
[16]J.I.Osa, A.Carlosena, and A.J.Lopez-Martin, " MOSFET-C filter with on-chip tuning and wide programming range" IEEE Trans. Circuits and Systems-Ⅱ, vol.48, no.10, pp.944-951, Oct.2001
[17]B.Nauta, "A CMOS transconductance-C filter technique for very high frequencies" IEEE Journal of Solid-State Circuits,Vol.27, No.2, pp.142-153, Feb.1992
[18]Z. Czarnul, S. C. Fang, and Y. Tsividis, "Improving linearity in MOS fully-integrated continuous-time filters," IEEE ISCAS.1986, pp.1169-1172
[19]J.Silva-Martinez, M. S. J. Steyaert, and W. M. C, Sansen, "A large-signal very low-distortion transconductor for high-frequency continuous-time filters" IEEE Journal of Solid-State Circuits, Vol.26, No.7, pp.946-955, July 1991.
[20]B.lazavi, Design Of Analog Cmos Integrated Circuits, McGraw-Hill Education, Europe
[21]P. Gray and R. Mayer, Analysis and Design of Analog Integrated Circuits. New York:Wiley,1993.
[22]F.Medeiro, B.Perez-Verdu, and A.Rodriguez-Vazquez, Top-Down Design of High Performance Sigma-Delta Modulators. Norwell, MA:Kluwer,1999.
[23]S. Pavan and Y. Tsividis, High Frequency Continuous-Time Filters in Digital CMOS Process. Norwell, MA:Kluwer,2000.
[24]J. A. Cherry and W. M. Snelgrove,.Excess Loop Delay in Continuous-Time Delta-Sigma Modulator, IEEE Trans. Circuits & System Ⅱ, vol.46, pp.376-389, Apr.1999.
[25]Zhimin Li, Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator with 2.5MHz Signal Bandwidth, PhD Thesis, Oregon State University (2006)
[26]Shouli yan, Baseband Continuous-Time Sigma-Delta Analog-to-Digital Conversion for ADSL Applications, PhD thesis, Texas A&M University,2002.
[27]James A. Cherry and W. Martin Snelgrove, CONTINUOUS-TIME DELTA-SIGMA MODULATORS FOR HIGH-SPEED A/D CONVERSION, Theory, Practice and FundamentalPerformance Limits, Kluwer academic publishers,2002
[28]李怡然CMOS宽带连续时间Sigma-Delta调制器,复旦大学硕士论文,2008年5月
[29]D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, "A self-calibration technique for monolithic high-resolution D/A converters," IEEE Journal of Solid-State Circuits, vol.24, no.6, pp.1517-1522, Dec.1989.
[30]R. Schreier, GC. Temes Delta-Sigma data converters[M]北京：科学出版社,2007.
[31]T. B. Cho and P. R. Gray, "A 10-b 20-Msample/s 35-mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp.166-172, Mar. 1995.
[32]Yao L B, Steyaert M S J, Sansen W. "A 1-V 140-uW 88-dB audio sigma-delta modulator in 90-nm CMOS" [J], IEEE JSSC,2004,39(11):1809-1818.
[33]S. Rabii and B.Wooley, "A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS," IEEE J. Solid-State Circuits, vol.32, no.6, pp.783-796, Jun.1997.
[34]H Aboushady, Y Dumonteix "Efficient Polyphase Decomposition of Comb Decimation Filters in Analog-to-Digital Converters", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Ⅱ:ANALOG AND DIGITAL SIGNAL PROCESSING VOL.48, NO.10, OCTOBER 2001
[35]J.C.Candy, "Decimation for Sigma Delta Modulation," IEEE Transactions on Communication, January 1986
[36]A.V.Oppenheim, "Discrete-Time Signal Processing," Prentice-Hall Inc.,1999
[37]S. Pavan,N. Krishnapura,R. Pandarinathan, et al. A power optimized continuous-time AE ADC for audio applications [J]. IEEE JSSC,2008,43(2): 351-360.
[38]J. Roh,S. Byun,Y. Choi, et al. A 0.9-V 60-μW 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range [J]. IEEE JSSC,2008,43(3):361-370.