高阶连续时间型Sigma-Delta调制器的研究与设计
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摘要
近年来Sigma-Delta ADC由于高精度、高集成度、低功耗等优点受到越来越多的关注,而且随着级联结构、多位量化、动态校准等新技术的发展,信号带宽高、过采样率低的Sigma-Delta ADC也在性能方面有了较大提高,所以Sigma-Delta ADC在宽带领域的应用也越来越广泛。然而以往大多数带宽达到MHz的Sigma-Delta ADC都是离散时间型,主要是由于它具有成熟的设计体系和健全的系统结构。比较起来,连续时间Sigma-Delta ADC具有低功耗和固有的抗混叠优势,可以有效地增加电池寿命,降低系统的复杂程度,这对于便携式无线设备是非常重要的。而且在数字电视、通信系统中都需要带宽大、精度较高的AD模块,连续时间型Sigma-Delta模数转换器就可以很好的满足这些应用需求。
本文设计了一款应用于视频解码芯片的连续时间型Sigma-Delta调制器,信号带宽为4MHz。设计的难点之一就在于时钟频率受到系统时钟以及功耗的限制只有64MHz,即过采样率仅为8。因此在设计过程中选取了五阶前馈型结构与10-level量化器相结合的技术。为了缩短设计周期,首先利用Matlab对整体系统进行了建模,得到了SNDR为72.2dB的前馈型Sigma-Delta调制器。在设计模型的同时考虑了电路实现的具体问题,采用了求和提前技术省略求和模块,从而降低了调制器的功耗。同时对于各模块可能引进的非理想性,利用增加传递函数模块、插入查找表结构、叠加白噪声等方法进行了建模仿真,计算了各模块非理想对整体性能的影响,并确定了各电路模块的主要性能指标,以指导具体电路模块的设计。在电路设计的过程中针对主要噪声源的噪声进行了理论推导,并对关键模块如运放、反馈DAC等,进行了匹配、延迟、功耗等方面的分析和设计考虑。最终整体的调制器前仿真信噪比(SNDR)为68.9dB,并且在所有工艺角下的最差SNDR不低于65dB。由于整体调制器都采用了全差分结构,在版图设计中尤其注意了对称性的考虑,包括运放、RC网络、量化器、反馈DAC等模块都是轴对称的,并与整体调制器版图的对称轴重合。对于关键的DAC模块,采用了特殊的版图布局以减小梯度误差及边缘误差,并进行了单独的精度测试。在输入信号为3V,2MHz的正弦波,采样频率为64MHz的情况下,最终的整体调制器后仿真SNDR为60.9dB,满足了系统的性能要求。
In recent years, more attention are payed to Sigma-Delta Modulator, due to its advantages such as high-precision, high-integration and low-power. Besides, along with the development of novel techniques, such as cascaded structure, multi-bit quantizer and dynamic calibration, the performance of wide-band Sigma-Delta ADC has been improved a lot. Therefore, it is possible to apply Sigma-Delta ADC for wide-band applications. However most of Sigma-Delta ADCs with signal band up to MHz employ switched capacitors in the past. Because there are mature design methodologies and robust system structures. Compared to DT (Discrete Time) Sigma-Delta ADC, CT (Continuous Time) Sigma-Delta ADC has the advantages of low-power and inherent anti-aliasing characteristic. These features can probably increase the life of battery and reduce the system complexity, which are essential for portable wireless equipments. ADC modules are necessary for Digital TV, and communication systems. A CT Sigma-Delta ADC can satisfy these requirements well.
In this paper A CT Sigma-Delta Modulator is designed for the application of video decode chip, with 4MHz signal bandwidth. The sampling clock frequency is limited by the clock of the whole system, therefore the OSR (OverSampling Ratio) is equal to 8. It is difficult to obtain a high performance Sigma-Delta ADC with such a low OSR. As a result, fifth-order feedforward structure and 10-level quantizer are used in this modulator. To shorten the desigh circle, a Matlab module of the whole system is built and 72.2dB SNDR is obtained. The modulator employs summation ahead technology so that a summation circuit is omitted and the power consumption is reduced. Detail nonideal analysises are conducted and modeled. Additional transfer function, lool-up table structure, extra white noise are added to the whole module to get the detail design guideline. During the circuit design, noise analysis on the main noise part—front-end circuits are given. Design considerations of key circuits in terms of mismatch, delay, power and so on are analyzed. The SNDR of the whole system is 68.9dB in the typical corner and above 65dB in every corner. As the whole system employs fully differential structure, the symmetry of the layout is seriously considered, including RC net, operational amplifier, quantizer and feedback DAC. What's more, special layout method is used for DAC module, because its mismatch error is fatal to the performance of the whole system. The post-layout SNDR of the whole system is 60.9dB, under a 3V,2MHz sinoder input signal and 64MHz clock.
本文设计了一款应用于视频解码芯片的连续时间型Sigma-Delta调制器,信号带宽为4MHz。设计的难点之一就在于时钟频率受到系统时钟以及功耗的限制只有64MHz,即过采样率仅为8。因此在设计过程中选取了五阶前馈型结构与10-level量化器相结合的技术。为了缩短设计周期,首先利用Matlab对整体系统进行了建模,得到了SNDR为72.2dB的前馈型Sigma-Delta调制器。在设计模型的同时考虑了电路实现的具体问题,采用了求和提前技术省略求和模块,从而降低了调制器的功耗。同时对于各模块可能引进的非理想性,利用增加传递函数模块、插入查找表结构、叠加白噪声等方法进行了建模仿真,计算了各模块非理想对整体性能的影响,并确定了各电路模块的主要性能指标,以指导具体电路模块的设计。在电路设计的过程中针对主要噪声源的噪声进行了理论推导,并对关键模块如运放、反馈DAC等,进行了匹配、延迟、功耗等方面的分析和设计考虑。最终整体的调制器前仿真信噪比(SNDR)为68.9dB,并且在所有工艺角下的最差SNDR不低于65dB。由于整体调制器都采用了全差分结构,在版图设计中尤其注意了对称性的考虑,包括运放、RC网络、量化器、反馈DAC等模块都是轴对称的,并与整体调制器版图的对称轴重合。对于关键的DAC模块,采用了特殊的版图布局以减小梯度误差及边缘误差,并进行了单独的精度测试。在输入信号为3V,2MHz的正弦波,采样频率为64MHz的情况下,最终的整体调制器后仿真SNDR为60.9dB,满足了系统的性能要求。
In recent years, more attention are payed to Sigma-Delta Modulator, due to its advantages such as high-precision, high-integration and low-power. Besides, along with the development of novel techniques, such as cascaded structure, multi-bit quantizer and dynamic calibration, the performance of wide-band Sigma-Delta ADC has been improved a lot. Therefore, it is possible to apply Sigma-Delta ADC for wide-band applications. However most of Sigma-Delta ADCs with signal band up to MHz employ switched capacitors in the past. Because there are mature design methodologies and robust system structures. Compared to DT (Discrete Time) Sigma-Delta ADC, CT (Continuous Time) Sigma-Delta ADC has the advantages of low-power and inherent anti-aliasing characteristic. These features can probably increase the life of battery and reduce the system complexity, which are essential for portable wireless equipments. ADC modules are necessary for Digital TV, and communication systems. A CT Sigma-Delta ADC can satisfy these requirements well.
In this paper A CT Sigma-Delta Modulator is designed for the application of video decode chip, with 4MHz signal bandwidth. The sampling clock frequency is limited by the clock of the whole system, therefore the OSR (OverSampling Ratio) is equal to 8. It is difficult to obtain a high performance Sigma-Delta ADC with such a low OSR. As a result, fifth-order feedforward structure and 10-level quantizer are used in this modulator. To shorten the desigh circle, a Matlab module of the whole system is built and 72.2dB SNDR is obtained. The modulator employs summation ahead technology so that a summation circuit is omitted and the power consumption is reduced. Detail nonideal analysises are conducted and modeled. Additional transfer function, lool-up table structure, extra white noise are added to the whole module to get the detail design guideline. During the circuit design, noise analysis on the main noise part—front-end circuits are given. Design considerations of key circuits in terms of mismatch, delay, power and so on are analyzed. The SNDR of the whole system is 68.9dB in the typical corner and above 65dB in every corner. As the whole system employs fully differential structure, the symmetry of the layout is seriously considered, including RC net, operational amplifier, quantizer and feedback DAC. What's more, special layout method is used for DAC module, because its mismatch error is fatal to the performance of the whole system. The post-layout SNDR of the whole system is 60.9dB, under a 3V,2MHz sinoder input signal and 64MHz clock.
引文
[1]O. Oliaei, P. Clement, and P. Gorisse. A 5-mW Sigma.Delta Modulator with 84-dB Dynamic Range for GSM/EDGE[J]. IEEE J. Solid-State Circuits,2002, Jan, 37:2-10.
[2]A. Dezzani and E. Andre. A 1.2-V Dual-Mode WCDMA/GPRS ΣΔ Modulator [A]. In ISSCC Dig. Tech. Papers,2003, Feb:58-59.
[3]K. Philips. A 4.4mW 76dB ComplexΣΔ ADC for Bluetooth Receivers[A].In ISSCC Dig. Tech. Papers,2003 Feb:64-65
[4]T. Ueno and T. Itakura. A 0.9V 1.5mW Continuous-Time ΣΔ Modulator for WCDMA[A]. In ISSCC Dig. Tech. Papers,2004, Feb:78-79.
[5]M. Schimper, L. Dorm, E. Riccio, and G. Panov.A 3mW Continuous-Time ΣΔ Modulator for EDGE/GSM with High Adjacent Channel Tolerance[A]. In European Solid-State Circuits Conference,2004, Sep:183-186.
[6]Y. L. Guillou et al. Highly Integrated Direct Conversion Receiver for GSM/GPRS/EDGE with On-Chip 84-dB Dynamic Range Continuous-TimeΣΔ ADC [J]. IEEE J. Solid-State Circuits,2005, Feb,40:403-411.
[7]F. Esfahani, P. Basedau et al. A Fourth Order Continuous-Time Complex Sigma-Delta ADC for Low-IF GSM and EDGE Receivers[A]. In VLSI Dig. Tech. Papers,2003, Jun:75-78.
[8]K. Philips et al. A Continuous-Time ΣΔ ADC with Increased Immunity to Interferers[J]. IEEE J. Solid-State Circuits,2004, Dec,39:2170-2178.
[9]R. van Veldhoven. A Tri-Mode Continuous-Time ΣΔ Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver[A]. In ISSCC Dig. Tech. Papers,2003, Feb:60-61.
[10]L. Doerrer.10-Bit,3 mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.12μm CMOS process[A]. In European Solid-State Circuits Conference,2003, Sept:245-248.
[11]L. J. Breems. A Cascaded Continuous-Time ΣΔ Modulator with 67dB Dynamic Range in 10MHz Bandwidth[A]. In ISSCC Dig. Tech. Papers,2004, Feb:72-73.
[12]S.Abdennadher, S.Kiaer, G.Temes and R. Schreier. Adaptive Selfcalibrating Delta-Sigma Modulators[J]. Electronics Letters,1992, July
[13]Jose Silva, Un-Ku Moon, and Gabor C. Temes. Low-distortion Delta-Sigma Topologyies for MASH Architectures. [J]. Circuits and Systems,2004, May.
[14]P. Benabes, A. Gauthier and D. Billet. New Wideband Converter[M], Aug.1993
[15]A.I.Hussein and W.B.Kuhn. Bandpass Sigma-Delta Modulator Employing Undersampling and on-chip Q-enhanced LC filter[J]. Mixed-Signal Design,1999, April.
[16]Van Tam Nguyen, Patrick Loumeau and Jean-Francois Naviner. Analysis of Time-interleaved Delta-Sigma Analog to Digital Converter[J]. Vehicular Technology Conference,2002, May
[17]Aria Eshraghi and Terri S. Fiez. A Comparative Analysis of Parallel Delta-Sigma ADC Architectures [J]. Circuits and Systems,2004, March
[18]Tsung-Sum Lee, Wen-Bin Lin and Dung-Lin Lee.Design Techniques for Micopower Low-voltage CMOS Switched-Capacitor Delta-Sigma Modulator[J]. Circuits and Systems,2004, July.
[19]Schreier R, Temes G.C. Delta-Sigma数据转换器[M].科学出版社,2007
[20]Lucien Breems, Johan H. Huijsing. Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers[M]. The Netherlands:Kluwer Academic Publishers,2001:59-63.
[21]S.R. Norsworthy, R. Scherier, G.C. Temes.Delta-sigma data converters-Theory, design, and simulation[M]. U.S.A.:IEEE Press,1997.
[22]L.R.Carley. A noise-shaping coder topology for 15-bit converters, IEEE J. Solid-State Circuits,1989, April,24(2):267-273.
[23]J.F.Jensen, G.Taghavan, A.E.Consand and R.H.Walden. A 3.2-GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology [J]. IEEE J.Solid-State Circuits,1995, Oct,30(10):1119-1127.
[24]A.Baschirotto, R.Castello.1-V 1.8-MHz CMOS Switched-OpAmp SC Filter with Rail-to-Rail Output Swing[J]. IEEE J.Solid-State Circuits,1997, Dec,32(12): 1979-1986.
[25]R.Gregorian, G.C.Temes. Analog MOS Integrated Circuits for Signal Processing[M]. John Willey&Sons.1986.
[26]M. Ortmanns, F. Gerfers, and Y. Manoli.Influence of Finite Integrator Gain Bandwidth on Continuous-Time Sigma-Delta Modulators. In IEEE Proc. ISCAS, 2003, May,1:925-928.
[27]Y. P. Tsividis and J. O. Voorman. Integrated Continuous-Time Filters[M], U.S.A:IEEE Press,1993.
[28]F. Krummenacher and N. Joehl. A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning[J]. IEEE J. Solid-State Circuits,1998, June, 23(3):750-758.
[29]Z. Chang, D. Haspeslagh, and J. Verfaillie. A Highly Linear CMOS Gm-C Bandpass Filter with On-Chip Frequency Tuning[J]. IEEE J. Solid-State Circuits, 1997, March,32:388-397.
[30]M. Chen, J. S. Martinez, S. Rokhsaz, and M. Robinson. A 2V-Vpp 80-200-MHz Fourth-Order Continuous-Time Linear Phase Filter with Automatic Frequency Tuning[A], In European Solid-State Circuits Conference,2002, Sept:643-646.
[31]Jose Bastos, Augusto Marques, Michel Steyaert, and Willy Sansen. A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC[J]. IEEE J. Solid State Circuits,1998, Dec,33:1959-1969.
[32]Jose Bastos, Michel Steyaert, and Willy Sansen. A High Yield 12-bit 250-MS/s CMOS D/A Converter[J]. In CICC,1996:431-434.
[33]Xuefeng Chen. A Wideband Low-Power Continuous-Time Delta-Sigma Modulator for Next Generation Wireless Applications[D]. U.S.A.:Oregon State University,2007.
[34]L. Hernandez, et al. Modeling and Optimization of Low Pass Continuous-Time Sigma-Delta Modulators for Clock Jitter Noise Reduction[A], In IEEE Proc. ISCAS,2004, May,1:1072-1075.
[35]J. A. Cherry and W. M. Snelgrove. Excess Loop Delay in Continuous-Time Delta-Sigma Modulator, In IEEE Trans. Circuits & System II,1999, April,46: 376-389.
[2]A. Dezzani and E. Andre. A 1.2-V Dual-Mode WCDMA/GPRS ΣΔ Modulator [A]. In ISSCC Dig. Tech. Papers,2003, Feb:58-59.
[3]K. Philips. A 4.4mW 76dB ComplexΣΔ ADC for Bluetooth Receivers[A].In ISSCC Dig. Tech. Papers,2003 Feb:64-65
[4]T. Ueno and T. Itakura. A 0.9V 1.5mW Continuous-Time ΣΔ Modulator for WCDMA[A]. In ISSCC Dig. Tech. Papers,2004, Feb:78-79.
[5]M. Schimper, L. Dorm, E. Riccio, and G. Panov.A 3mW Continuous-Time ΣΔ Modulator for EDGE/GSM with High Adjacent Channel Tolerance[A]. In European Solid-State Circuits Conference,2004, Sep:183-186.
[6]Y. L. Guillou et al. Highly Integrated Direct Conversion Receiver for GSM/GPRS/EDGE with On-Chip 84-dB Dynamic Range Continuous-TimeΣΔ ADC [J]. IEEE J. Solid-State Circuits,2005, Feb,40:403-411.
[7]F. Esfahani, P. Basedau et al. A Fourth Order Continuous-Time Complex Sigma-Delta ADC for Low-IF GSM and EDGE Receivers[A]. In VLSI Dig. Tech. Papers,2003, Jun:75-78.
[8]K. Philips et al. A Continuous-Time ΣΔ ADC with Increased Immunity to Interferers[J]. IEEE J. Solid-State Circuits,2004, Dec,39:2170-2178.
[9]R. van Veldhoven. A Tri-Mode Continuous-Time ΣΔ Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver[A]. In ISSCC Dig. Tech. Papers,2003, Feb:60-61.
[10]L. Doerrer.10-Bit,3 mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.12μm CMOS process[A]. In European Solid-State Circuits Conference,2003, Sept:245-248.
[11]L. J. Breems. A Cascaded Continuous-Time ΣΔ Modulator with 67dB Dynamic Range in 10MHz Bandwidth[A]. In ISSCC Dig. Tech. Papers,2004, Feb:72-73.
[12]S.Abdennadher, S.Kiaer, G.Temes and R. Schreier. Adaptive Selfcalibrating Delta-Sigma Modulators[J]. Electronics Letters,1992, July
[13]Jose Silva, Un-Ku Moon, and Gabor C. Temes. Low-distortion Delta-Sigma Topologyies for MASH Architectures. [J]. Circuits and Systems,2004, May.
[14]P. Benabes, A. Gauthier and D. Billet. New Wideband Converter[M], Aug.1993
[15]A.I.Hussein and W.B.Kuhn. Bandpass Sigma-Delta Modulator Employing Undersampling and on-chip Q-enhanced LC filter[J]. Mixed-Signal Design,1999, April.
[16]Van Tam Nguyen, Patrick Loumeau and Jean-Francois Naviner. Analysis of Time-interleaved Delta-Sigma Analog to Digital Converter[J]. Vehicular Technology Conference,2002, May
[17]Aria Eshraghi and Terri S. Fiez. A Comparative Analysis of Parallel Delta-Sigma ADC Architectures [J]. Circuits and Systems,2004, March
[18]Tsung-Sum Lee, Wen-Bin Lin and Dung-Lin Lee.Design Techniques for Micopower Low-voltage CMOS Switched-Capacitor Delta-Sigma Modulator[J]. Circuits and Systems,2004, July.
[19]Schreier R, Temes G.C. Delta-Sigma数据转换器[M].科学出版社,2007
[20]Lucien Breems, Johan H. Huijsing. Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers[M]. The Netherlands:Kluwer Academic Publishers,2001:59-63.
[21]S.R. Norsworthy, R. Scherier, G.C. Temes.Delta-sigma data converters-Theory, design, and simulation[M]. U.S.A.:IEEE Press,1997.
[22]L.R.Carley. A noise-shaping coder topology for 15-bit converters, IEEE J. Solid-State Circuits,1989, April,24(2):267-273.
[23]J.F.Jensen, G.Taghavan, A.E.Consand and R.H.Walden. A 3.2-GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology [J]. IEEE J.Solid-State Circuits,1995, Oct,30(10):1119-1127.
[24]A.Baschirotto, R.Castello.1-V 1.8-MHz CMOS Switched-OpAmp SC Filter with Rail-to-Rail Output Swing[J]. IEEE J.Solid-State Circuits,1997, Dec,32(12): 1979-1986.
[25]R.Gregorian, G.C.Temes. Analog MOS Integrated Circuits for Signal Processing[M]. John Willey&Sons.1986.
[26]M. Ortmanns, F. Gerfers, and Y. Manoli.Influence of Finite Integrator Gain Bandwidth on Continuous-Time Sigma-Delta Modulators. In IEEE Proc. ISCAS, 2003, May,1:925-928.
[27]Y. P. Tsividis and J. O. Voorman. Integrated Continuous-Time Filters[M], U.S.A:IEEE Press,1993.
[28]F. Krummenacher and N. Joehl. A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning[J]. IEEE J. Solid-State Circuits,1998, June, 23(3):750-758.
[29]Z. Chang, D. Haspeslagh, and J. Verfaillie. A Highly Linear CMOS Gm-C Bandpass Filter with On-Chip Frequency Tuning[J]. IEEE J. Solid-State Circuits, 1997, March,32:388-397.
[30]M. Chen, J. S. Martinez, S. Rokhsaz, and M. Robinson. A 2V-Vpp 80-200-MHz Fourth-Order Continuous-Time Linear Phase Filter with Automatic Frequency Tuning[A], In European Solid-State Circuits Conference,2002, Sept:643-646.
[31]Jose Bastos, Augusto Marques, Michel Steyaert, and Willy Sansen. A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC[J]. IEEE J. Solid State Circuits,1998, Dec,33:1959-1969.
[32]Jose Bastos, Michel Steyaert, and Willy Sansen. A High Yield 12-bit 250-MS/s CMOS D/A Converter[J]. In CICC,1996:431-434.
[33]Xuefeng Chen. A Wideband Low-Power Continuous-Time Delta-Sigma Modulator for Next Generation Wireless Applications[D]. U.S.A.:Oregon State University,2007.
[34]L. Hernandez, et al. Modeling and Optimization of Low Pass Continuous-Time Sigma-Delta Modulators for Clock Jitter Noise Reduction[A], In IEEE Proc. ISCAS,2004, May,1:1072-1075.
[35]J. A. Cherry and W. M. Snelgrove. Excess Loop Delay in Continuous-Time Delta-Sigma Modulator, In IEEE Trans. Circuits & System II,1999, April,46: 376-389.