网络处理器MAC层协议的实现与研究
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摘要
随着宽带网提供的网络协议与服务业务种类的增加，网络处理器已经成为新一代网络交换机与路由器的核心设备。网络处理器一般采用多内核结构和专用指令集处理器技术，具有高性能和灵活性强的优点。MAC层处理单元是网络处理器重要的网络接口单元，负责网络处理器和外部物理层链路的交换，其性能直接影响着网络处理器的整体性能。本文结合网络处理器的研究项目，从实现具有通用总线接口的MAC层处理单元入手，完成了网络处理器以太网MAC层的RTL级硬件实现。
本文首先研究了IEEE 802.3标准规定的MAC子层协议，分析了以太网MAC帧格式，并且介绍了Wishbone片上总线的4种互连方式、总线周期和接口信号。本文着重研究了MAC层处理单元的体系结构，对MAC层处理单元进行了功能模块的划分。设计MAC层处理单元由接收模块、发送模块、MAC流控模块、寄存器模块、缓冲区模块、Wishbone总线接口和MII接口控制模块7部分组成。使用FIFO单元缓冲MAC与Wishbone总线之间的数据传输。对发送模块、接收模块、缓冲区模块和Wishbone总线接口进行了比较详细的结构设计和功能描述。通过建立测试平台和测试用例，完成了设计的功能仿真和验证，给出了仿真验证结果。验证结果表明，硬件实现符合网络处理器MAC层的要求。
本文的创新点在于：实现了具有Wishbone片上总线接口的MAC层处理单元，该MAC层处理单元适用于网络处理器，并具有一定的通用性；详细推导了以太网的并行CRC校验方法；对MAC层处理单元进行了自己的功能模块划分以及RTL级硬件设计。
With the increase of protocols and services for broadband networks, Network processor (NP) has become the core of switcher and router. The architecture of NP is generally composed of multicore. And NP commonly uses the ASIP technology. NP has the advantages of high performance and flexibility. The MAC element which exchanges the data between NP and physical layer is the important interface for NP. The performance of the MAC sublayer impacts the I/O performance of network processor greatly. This dissertation researches the design and implementation of Ethernet MAC sublayer, which is incorporated with the project of network processor. In this paper, a MAC element which has standard bus interface and 10Mpbs/100Mbps data transfer rate has been designed on RTL level.
This dissertation studies the protocol of the MAC sublayer for IEEE 802.3 standard and then describes different MAC frames' structures. To introduce four components of the Wishbone interconnection architecture, classic bus cycles and interface signals.
This dissertation detailedly studies the architectures of the MAC element. its architecture is composed of receiver module, transmit module, MAC control module, register module, buffer module, Wishbone interface and MII interface module. The MAC element can transmits data with Wishbone interface through FIFO. It detailedly describes the designs and functions of the receiver module, transmit module, buffer module and Wishbone interface. It has completed the function simulation and verification of this design. The verification results show that the design meets the requirement of the MAC sublayer.
The contributions of this dissertation are as follows. A MAC element with Wishbone interface which has generality is proposed. The way for parallel CRC algorithm is detailedly presented. The architectures of the MAC element are detailedly designed on RTL level and implemented by Verilog codes.
本文首先研究了IEEE 802.3标准规定的MAC子层协议，分析了以太网MAC帧格式，并且介绍了Wishbone片上总线的4种互连方式、总线周期和接口信号。本文着重研究了MAC层处理单元的体系结构，对MAC层处理单元进行了功能模块的划分。设计MAC层处理单元由接收模块、发送模块、MAC流控模块、寄存器模块、缓冲区模块、Wishbone总线接口和MII接口控制模块7部分组成。使用FIFO单元缓冲MAC与Wishbone总线之间的数据传输。对发送模块、接收模块、缓冲区模块和Wishbone总线接口进行了比较详细的结构设计和功能描述。通过建立测试平台和测试用例，完成了设计的功能仿真和验证，给出了仿真验证结果。验证结果表明，硬件实现符合网络处理器MAC层的要求。
本文的创新点在于：实现了具有Wishbone片上总线接口的MAC层处理单元，该MAC层处理单元适用于网络处理器，并具有一定的通用性；详细推导了以太网的并行CRC校验方法；对MAC层处理单元进行了自己的功能模块划分以及RTL级硬件设计。
With the increase of protocols and services for broadband networks, Network processor (NP) has become the core of switcher and router. The architecture of NP is generally composed of multicore. And NP commonly uses the ASIP technology. NP has the advantages of high performance and flexibility. The MAC element which exchanges the data between NP and physical layer is the important interface for NP. The performance of the MAC sublayer impacts the I/O performance of network processor greatly. This dissertation researches the design and implementation of Ethernet MAC sublayer, which is incorporated with the project of network processor. In this paper, a MAC element which has standard bus interface and 10Mpbs/100Mbps data transfer rate has been designed on RTL level.
This dissertation studies the protocol of the MAC sublayer for IEEE 802.3 standard and then describes different MAC frames' structures. To introduce four components of the Wishbone interconnection architecture, classic bus cycles and interface signals.
This dissertation detailedly studies the architectures of the MAC element. its architecture is composed of receiver module, transmit module, MAC control module, register module, buffer module, Wishbone interface and MII interface module. The MAC element can transmits data with Wishbone interface through FIFO. It detailedly describes the designs and functions of the receiver module, transmit module, buffer module and Wishbone interface. It has completed the function simulation and verification of this design. The verification results show that the design meets the requirement of the MAC sublayer.
The contributions of this dissertation are as follows. A MAC element with Wishbone interface which has generality is proposed. The way for parallel CRC algorithm is detailedly presented. The architectures of the MAC element are detailedly designed on RTL level and implemented by Verilog codes.
引文
[1] 王诚，薛小刚，钟信潮．FPGA/CPLD设计工具Xilinx ISE使用详解[M]．北京：人民邮电出版社，2005．
[2] 田泽，张怡浩，于敦山等．Wishbone IP核互联总线[J]．半导体技术，2005，30(1)：28—31．
[3] 石晶林，程胜，孙江明．网络处理器原理、设计与应用．北京：清华大学出版社，2003．
[4] 宋廷强，刘川来，周艳．SOC中Wishbone片上总线的设计与开发[J]．青岛科技大学学报，2003，24(5)：439—442．
[5] 陈奇，沈力为，杨莲兴等．802．11b MAC子层控制器的设计与验证[J]．复旦大学学报(自然科学版)，2005，44(1)：192—195．
[6] 陆建松，李明，李纪军等．EPON中CRC校验码的并行算法实现[J]．无线通信技术，2006，(1)：37—39．
[7] 杨宗凯，黄建，杜旭．数字专用集成电路的设计与验证[M]．北京：电子工业出版社，2004．
[8] 张磊，吴晖．Wishbone总线协议下DDR存储控制器设计[J]．微电子学与计算机，2004，21(9)：170—176．
[9] 郎波，黄冬泉，张辉等译．千兆以太网技术与应用[M]．北京：机械工业出版社，2000．
[10] 周彩宝．网络处理器简介及其微引擎设计[J]．计算机工程，2006，32(14)：98—100．
[11] 徐欣，于红旗，易凡．基于FPGA的嵌入式系统设计[M]．北京：机械工业出版社，2004．
[12] 夏泽中，柴庆芬．循环冗余校验码算法的分析及VHDL语言实现[J]．计算机与数字工程，2005，33(7)：104—106．
[13] 徐洪波，俞承芳．基于FPGA的以太网MAC子层协议设计实现[J]．复旦大学学报(自然科学版)，2004，43(1)：50—53．
[14] 高继业，戎蒙恬，邹定楷．千兆以太网CRC的算法与VLSI设计与实现[J]．计算机工程，2005，31(3)：215—217．
[15] 夏琦，戎蒙恬，诸悦．千兆以太网1000BASE-T收发器物理编码子层系统及芯片设计[J]．上海交通大学学报(自然科学版)，2006，40(3)：528—531．
[16] 曹志刚，钱亚生．现代通信原理[M]．北京：清华大学出版社，2003．
[17] 谢希仁．计算机网络(第4版)[M]．北京：电子工业出版社，2003．
[18] 蔡宇，张浩，罗飞等．无线局域网卡MAC控制器设计[J]．半导体技术，2005， 3U(3)：50—53．
[19] 谭章熹，林闯，任丰源等．网络处理器的分析与研究[J]．软件学报，2003，14(2)：253—267．
[20] 戴艺，张晓明，孙志刚等．ATM网络中高速计算CRC-32算法及其并行实现[J]．计算机工程，2005，31(22)：116—118．
[21] 魏芳，刘志军，马克杰等．基于Vcrilog HDL的异步FIFO设计与实现[J]．电子技术应用，2006，(7)：97—99．
[22] Andrew S．Tanenbaum．计算机网络(第3版)[M]．北京：清华大学出版社，1998年．
[23] Blake S, Black D, Carlson M, Davies E, Wang Z, Weiss W. An architecture for differentiated services. RFC 2475, Internet Engineering Task Force, 1998.
[24] Ciletti M D. Advanced digital design with the Verilog HDL [M]. 北京：电子工业出版社，2004.
[25] Ethernet Media Access Controller Core, CAST Inc. October, 2003.
[26] F. Khunjush, M.W. E1-Kharashi, K.E Li, N.J. Dimopoulos. Network processor design: issues and challenges. Processing 2003 of IEEE Pacific Rim Conference on Communications, Computers and signal, 2003, Vol.1, pp.164-168.
[27] George C. clark, J. Bibb Cain. Erro-Correction Coding for Digital Communications[M]. New York: Plenum Press, 1981.
[28] IBM Corp. IBM Network Processor Hardware Reference Manual. http://www-3.ibm.corn/chips/techlib/techlib.nsf/products/PowerNP NP4GS3, January 2003.
[29] IEEE 802.3-2005: IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements, Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications, 2005[S].
[30] Intel Corp. Intel(R) IXP1200 Family Hardware Reference Manual. http://www.intel.com/design/network/manuals/278303.htm, 2006.
[31] Jan M. Rabaey, Anantha Chandrakasan, Borivoge Nikolie. Digital Integrated Circuits-A Design Perspective(second edition) [M].北京：清华大学出版社，2004.
[32] J.Bhasker. Verilog HDL 硬件描述语言[M].北京：机械工业出版社，2000.
[33] J.Bhasker. Verilog HDL Sythesis-A Pratical Primer[M]. 北京：清华大学出版社，2004.
[34] Peterson W. W, Weldon E J. Error-Correcting Codes (2nd ed.). Cambridge, MA: MIT Press, 1972.
[35] Shah N. Understanding network processors [MS. Thesis]. Berkeley: Department of Electrical Engineering and Computer Sciences, University of California, 2001.
[36] T.Wolf, J.S.Turner. Design issues for high-performance active routers. IEEE Journal on Selected Areas in Communications, 2001, Vol.19, No.3, pp.404-4091
[37] Wishbone System-on-Chip(SOC) Interconnection Architecture for Portable IP Cores(Reision B.3), Silicore Corporation, September 7,2001[S].
[38] W.Richard Stevens. TCP/IP Illustracted Volume l:The Protocols[M]. 北京：机械工业出版社，2000.
[2] 田泽，张怡浩，于敦山等．Wishbone IP核互联总线[J]．半导体技术，2005，30(1)：28—31．
[3] 石晶林，程胜，孙江明．网络处理器原理、设计与应用．北京：清华大学出版社，2003．
[4] 宋廷强，刘川来，周艳．SOC中Wishbone片上总线的设计与开发[J]．青岛科技大学学报，2003，24(5)：439—442．
[5] 陈奇，沈力为，杨莲兴等．802．11b MAC子层控制器的设计与验证[J]．复旦大学学报(自然科学版)，2005，44(1)：192—195．
[6] 陆建松，李明，李纪军等．EPON中CRC校验码的并行算法实现[J]．无线通信技术，2006，(1)：37—39．
[7] 杨宗凯，黄建，杜旭．数字专用集成电路的设计与验证[M]．北京：电子工业出版社，2004．
[8] 张磊，吴晖．Wishbone总线协议下DDR存储控制器设计[J]．微电子学与计算机，2004，21(9)：170—176．
[9] 郎波，黄冬泉，张辉等译．千兆以太网技术与应用[M]．北京：机械工业出版社，2000．
[10] 周彩宝．网络处理器简介及其微引擎设计[J]．计算机工程，2006，32(14)：98—100．
[11] 徐欣，于红旗，易凡．基于FPGA的嵌入式系统设计[M]．北京：机械工业出版社，2004．
[12] 夏泽中，柴庆芬．循环冗余校验码算法的分析及VHDL语言实现[J]．计算机与数字工程，2005，33(7)：104—106．
[13] 徐洪波，俞承芳．基于FPGA的以太网MAC子层协议设计实现[J]．复旦大学学报(自然科学版)，2004，43(1)：50—53．
[14] 高继业，戎蒙恬，邹定楷．千兆以太网CRC的算法与VLSI设计与实现[J]．计算机工程，2005，31(3)：215—217．
[15] 夏琦，戎蒙恬，诸悦．千兆以太网1000BASE-T收发器物理编码子层系统及芯片设计[J]．上海交通大学学报(自然科学版)，2006，40(3)：528—531．
[16] 曹志刚，钱亚生．现代通信原理[M]．北京：清华大学出版社，2003．
[17] 谢希仁．计算机网络(第4版)[M]．北京：电子工业出版社，2003．
[18] 蔡宇，张浩，罗飞等．无线局域网卡MAC控制器设计[J]．半导体技术，2005， 3U(3)：50—53．
[19] 谭章熹，林闯，任丰源等．网络处理器的分析与研究[J]．软件学报，2003，14(2)：253—267．
[20] 戴艺，张晓明，孙志刚等．ATM网络中高速计算CRC-32算法及其并行实现[J]．计算机工程，2005，31(22)：116—118．
[21] 魏芳，刘志军，马克杰等．基于Vcrilog HDL的异步FIFO设计与实现[J]．电子技术应用，2006，(7)：97—99．
[22] Andrew S．Tanenbaum．计算机网络(第3版)[M]．北京：清华大学出版社，1998年．
[23] Blake S, Black D, Carlson M, Davies E, Wang Z, Weiss W. An architecture for differentiated services. RFC 2475, Internet Engineering Task Force, 1998.
[24] Ciletti M D. Advanced digital design with the Verilog HDL [M]. 北京：电子工业出版社，2004.
[25] Ethernet Media Access Controller Core, CAST Inc. October, 2003.
[26] F. Khunjush, M.W. E1-Kharashi, K.E Li, N.J. Dimopoulos. Network processor design: issues and challenges. Processing 2003 of IEEE Pacific Rim Conference on Communications, Computers and signal, 2003, Vol.1, pp.164-168.
[27] George C. clark, J. Bibb Cain. Erro-Correction Coding for Digital Communications[M]. New York: Plenum Press, 1981.
[28] IBM Corp. IBM Network Processor Hardware Reference Manual. http://www-3.ibm.corn/chips/techlib/techlib.nsf/products/PowerNP NP4GS3, January 2003.
[29] IEEE 802.3-2005: IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements, Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications, 2005[S].
[30] Intel Corp. Intel(R) IXP1200 Family Hardware Reference Manual. http://www.intel.com/design/network/manuals/278303.htm, 2006.
[31] Jan M. Rabaey, Anantha Chandrakasan, Borivoge Nikolie. Digital Integrated Circuits-A Design Perspective(second edition) [M].北京：清华大学出版社，2004.
[32] J.Bhasker. Verilog HDL 硬件描述语言[M].北京：机械工业出版社，2000.
[33] J.Bhasker. Verilog HDL Sythesis-A Pratical Primer[M]. 北京：清华大学出版社，2004.
[34] Peterson W. W, Weldon E J. Error-Correcting Codes (2nd ed.). Cambridge, MA: MIT Press, 1972.
[35] Shah N. Understanding network processors [MS. Thesis]. Berkeley: Department of Electrical Engineering and Computer Sciences, University of California, 2001.
[36] T.Wolf, J.S.Turner. Design issues for high-performance active routers. IEEE Journal on Selected Areas in Communications, 2001, Vol.19, No.3, pp.404-4091
[37] Wishbone System-on-Chip(SOC) Interconnection Architecture for Portable IP Cores(Reision B.3), Silicore Corporation, September 7,2001[S].
[38] W.Richard Stevens. TCP/IP Illustracted Volume l:The Protocols[M]. 北京：机械工业出版社，2000.