JTAG的设计与研究
|
摘要
边界扫描技术是符合IEEE规范的一种测试方法，JTAG设计的实现降低了测试的复杂度、提高了质量及缩短面市时间。适合进行超大规模集成电路的测试。同时，JTAG以采用更小的体积而提供更强的功能的优势，主要应用到集成电路设计和测试验证的开发研究方面，但实现边界扫描技术需要超出7％的附加芯片面积，同时增加了连线数目，且工作速度有所下降，这些问题有待解决。
本文通过对JTAG标准和技术内容的研究，对JTAG在SoC器件中的应用结构进行了分析，提出了相应的简化措施，以此为据，设计了可用于芯片测试的嵌入式JTAG模块(IP软核)，所设计的JTAG模块具有结构简单、技术齐全、支持广泛、测试设计灵活、高精度故障定位等特征，可广泛用于SoC器件的设计。
本文通过一定的理论研究，给出了一种实现JTAG结构的具体方法，首次分析了如何选择扫描链的数量与长度的方法与原则，并对测试功耗进行了分析。本文的特点是紧扣IEEE1149.1标准，并对JTAG进行RTL级建模和仿真以及首次对JTAG指令进行了分析，得出JTAG软核的基础测试满足设计要求，并将边界扫描测试设计应用到实际电路当中，实现对边界扫描测试理论的验证。经过仿真验证，证明其设计可靠、方案可行，具有很好的实用价值。
Boundary-scan technique is a testing method of IEEE. Realization of JTAG reduces the complexity of testing, and increases time to market, thus it is suitable for testing of VLSI. Meanwhile, due to stronger function with smaller volume, mainly used in research on IC design and verification, but to realise bounsary-scan will requires7% extra area, increase the number of lines, and decrease the operating speed. All these problems are to be solved.
According to research on JTAG standard and technology conception, the JTAG application architecture in SoC device is analyzed, a simplyfied measure is proposed. Based on this, embeded JTAG IP core which is applicable in chip testing is designed. The JTAG IP core has the following features: simple structure, mature in technique, widely supportive, variable testing method design, high precision error location, and it is widely used in SoC design.
Through academic research, detailed method of JTAG realization is presented, and for the first time, how to select the number and length of scan chain and testing dissipation are analyzed. The paper is closely attached to IEEE1149.1 standard, and the novel idea lies in the fact that after analysis on JTAG instruction and RTL level modeling and simulation of JTAG, the fundamental part in JTAG testing follows the specification, boundary-scan testing is applied to actual circuits, and finally the theory of boundary-scan is verified. Through simulation and verification, the reliability and feasibility are satisfactory, and it is of good value.
本文通过对JTAG标准和技术内容的研究，对JTAG在SoC器件中的应用结构进行了分析，提出了相应的简化措施，以此为据，设计了可用于芯片测试的嵌入式JTAG模块(IP软核)，所设计的JTAG模块具有结构简单、技术齐全、支持广泛、测试设计灵活、高精度故障定位等特征，可广泛用于SoC器件的设计。
本文通过一定的理论研究，给出了一种实现JTAG结构的具体方法，首次分析了如何选择扫描链的数量与长度的方法与原则，并对测试功耗进行了分析。本文的特点是紧扣IEEE1149.1标准，并对JTAG进行RTL级建模和仿真以及首次对JTAG指令进行了分析，得出JTAG软核的基础测试满足设计要求，并将边界扫描测试设计应用到实际电路当中，实现对边界扫描测试理论的验证。经过仿真验证，证明其设计可靠、方案可行，具有很好的实用价值。
Boundary-scan technique is a testing method of IEEE. Realization of JTAG reduces the complexity of testing, and increases time to market, thus it is suitable for testing of VLSI. Meanwhile, due to stronger function with smaller volume, mainly used in research on IC design and verification, but to realise bounsary-scan will requires7% extra area, increase the number of lines, and decrease the operating speed. All these problems are to be solved.
According to research on JTAG standard and technology conception, the JTAG application architecture in SoC device is analyzed, a simplyfied measure is proposed. Based on this, embeded JTAG IP core which is applicable in chip testing is designed. The JTAG IP core has the following features: simple structure, mature in technique, widely supportive, variable testing method design, high precision error location, and it is widely used in SoC design.
Through academic research, detailed method of JTAG realization is presented, and for the first time, how to select the number and length of scan chain and testing dissipation are analyzed. The paper is closely attached to IEEE1149.1 standard, and the novel idea lies in the fact that after analysis on JTAG instruction and RTL level modeling and simulation of JTAG, the fundamental part in JTAG testing follows the specification, boundary-scan testing is applied to actual circuits, and finally the theory of boundary-scan is verified. Through simulation and verification, the reliability and feasibility are satisfactory, and it is of good value.
引文
[1] IEEE. IEEE Standard Test Access Port And Boundary Scan Archiecture. Institute of Electrical and Electronice Engineers, Inc, 1993
[2] 杨士元。 《数字系统的故障诊断与可靠性设计》。清华大学出版社。2000，149-214．
[3] 王彬，任颜颖。《数字IC系统设计》。西安电予科技大学出版社 2005，162-175．
[4] 胡学良，张春，王志华。JTAG技术的发展和应用综述。北京，微电：子学。2005年第6期，Vol．35，№6．pp．624-630．
[5] 何波，冯健。基于PC的JTAG测试环境的实现。现在电子技术。2004年第10期．pp．79-80．
[6] 鲁巍，杨修涛，李晓堆。基于JTAG标准的边界扫描在通用CPU中的设计。计算机工程。2004年10月第30卷第19期．pp．79-84．
[7] 马少霞，孟晓风，钟波。基于边界扫描技术的测试系统设计。自动控制与测试测量。2005．68-75．
[8] 薛军，潘高峰，朱莉。基于USB总线的边界扫描测试主控系统的设计。计算机测量与控制。2006．14(2)。
[9] Design for at-speed test, diagnosis and measurements by B.Nadeau-Dostie, Kluwer Academic Pub, USA, 2000.pp.56-61.
[10] Chakraborty TJ: A novel fault injection method for system verification based on FPGA boundary scan architecture.Proc.of ITC,2002.pp. 135-137.
[11] J.Nejedlo, " IBIST Architecture and Methodology for PCI-Express ", Proc.IEEE International Test Conference, 2003.pp.46-50.
[12] S.Chung and S.Baeg, "AC-JTAG:Empowering JTAG beyond Testing DC Nets", Proc.IEEE International Test Conference, 2001.pp.668-671.
[13] IEEE Standard 1149.6, "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks", IEEE Standards Board, New York, April 2003.pp.412-422.
[14] M.Hayashi and. Tsukiyama, "A hybrid hierarchical global router for multi-layer VLIS's, " IEICETrans.Fundamentals, vol.E78-A, no.3, 1995.pp.320-327.
[15] J.Cong, A.Kahng, and K.Leung, "Efficient algorithms for the minimum shortest path steiner arborescence problem with application to VLSI physical design," IEEE Trans. Computer-Aided Design, 1998. pp. 121-127.
[16] Eklow, Barnhard, Parker, IEEE P1149.6: A Boundary Scan Standard for Advanced Digital Network, Paper 37.1 2002 IEEE International Test Conference..pp. 76-82.
[17] Adding TAP, Boundary and ASI Test, Logic Vision Reference Manual, Nov, 2002.pp.66-73.
[18] IEEE computer society: "IEEE standard for a mixed signal test bus", —IEEE Std 1149.4,2000. pp.204-214.
[19] 夏宇闻 《从算法发涉及到硬件逻辑的实现——复杂数字逻辑系统的 Veriog HDL 设计技术和方法》高等教育出版社，2001．
[20] Roth JP. "Diagnosis of Automatic Failures: A Calculus and a Method." IBM Journal of Research and Development, 10, pp.278-281.
[21] Dave Stang R.Dandapani An lmplemention of IEEE1149.1 To Aoid Timing Violations and Other Practical In-compliance Improvements. ITC INTERNATIONAL TEST CONFERENCE. Paper 27. 2002. pp. 746-753.
[22] N.Ahmed, M.Tehranipour, M.Nourani, Extending JTAG for Testing Signal Integrity in SoCs. Proceedings of the Design,Automation and Test in Europe Conference and Exhibition. 2003. 03. 456-468.
[23] Lee Whetsel. Adapting JTAG for AC Interconnect Testing. ITC INTERNATIONAL TEST CONFERENCE. Paper 25.3. 2003. pp.96-105.
[24] Leon van de Logt, Frank van der Heyden, Tom Waayers.An extension to JTAG for at-speed debug on a system. ITC INTERNATIONAL TEST CONFERENCE. Paper 31.3.2003. pp.123-130.
[25] Mohammad H.Tehranipour, Nisar Ahmed, and Mehrdad Nourani. Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004. pp800-811.
[26] Hong-Shin Jun, Sung S. Chung and Sang H.Baeg. Removing JTAG Bottlenecks in System Interconnect Test. ITC INTERNATIONAL TEST CONFERENCE. Paper 7.3.2004. pp. 173-180.
[27] Michael L. Bushnell vishwani D.Agrawal，蒋安平，冯建华，王新安译。《Essentials of Electronic Testing for Digital,Memory & Mixed-Signal VLSI Circuits》，北京，电子工业出版社，2005．8，pp．412-430．
[28] Michael D．Ciletti，张雅绮，李锵等译，Advanced Digital Design with the Verilog HDL， 北京，电子工业出版社，2005．1，pp．603-644．
[2] 杨士元。 《数字系统的故障诊断与可靠性设计》。清华大学出版社。2000，149-214．
[3] 王彬，任颜颖。《数字IC系统设计》。西安电予科技大学出版社 2005，162-175．
[4] 胡学良，张春，王志华。JTAG技术的发展和应用综述。北京，微电：子学。2005年第6期，Vol．35，№6．pp．624-630．
[5] 何波，冯健。基于PC的JTAG测试环境的实现。现在电子技术。2004年第10期．pp．79-80．
[6] 鲁巍，杨修涛，李晓堆。基于JTAG标准的边界扫描在通用CPU中的设计。计算机工程。2004年10月第30卷第19期．pp．79-84．
[7] 马少霞，孟晓风，钟波。基于边界扫描技术的测试系统设计。自动控制与测试测量。2005．68-75．
[8] 薛军，潘高峰，朱莉。基于USB总线的边界扫描测试主控系统的设计。计算机测量与控制。2006．14(2)。
[9] Design for at-speed test, diagnosis and measurements by B.Nadeau-Dostie, Kluwer Academic Pub, USA, 2000.pp.56-61.
[10] Chakraborty TJ: A novel fault injection method for system verification based on FPGA boundary scan architecture.Proc.of ITC,2002.pp. 135-137.
[11] J.Nejedlo, " IBIST Architecture and Methodology for PCI-Express ", Proc.IEEE International Test Conference, 2003.pp.46-50.
[12] S.Chung and S.Baeg, "AC-JTAG:Empowering JTAG beyond Testing DC Nets", Proc.IEEE International Test Conference, 2001.pp.668-671.
[13] IEEE Standard 1149.6, "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks", IEEE Standards Board, New York, April 2003.pp.412-422.
[14] M.Hayashi and. Tsukiyama, "A hybrid hierarchical global router for multi-layer VLIS's, " IEICETrans.Fundamentals, vol.E78-A, no.3, 1995.pp.320-327.
[15] J.Cong, A.Kahng, and K.Leung, "Efficient algorithms for the minimum shortest path steiner arborescence problem with application to VLSI physical design," IEEE Trans. Computer-Aided Design, 1998. pp. 121-127.
[16] Eklow, Barnhard, Parker, IEEE P1149.6: A Boundary Scan Standard for Advanced Digital Network, Paper 37.1 2002 IEEE International Test Conference..pp. 76-82.
[17] Adding TAP, Boundary and ASI Test, Logic Vision Reference Manual, Nov, 2002.pp.66-73.
[18] IEEE computer society: "IEEE standard for a mixed signal test bus", —IEEE Std 1149.4,2000. pp.204-214.
[19] 夏宇闻 《从算法发涉及到硬件逻辑的实现——复杂数字逻辑系统的 Veriog HDL 设计技术和方法》高等教育出版社，2001．
[20] Roth JP. "Diagnosis of Automatic Failures: A Calculus and a Method." IBM Journal of Research and Development, 10, pp.278-281.
[21] Dave Stang R.Dandapani An lmplemention of IEEE1149.1 To Aoid Timing Violations and Other Practical In-compliance Improvements. ITC INTERNATIONAL TEST CONFERENCE. Paper 27. 2002. pp. 746-753.
[22] N.Ahmed, M.Tehranipour, M.Nourani, Extending JTAG for Testing Signal Integrity in SoCs. Proceedings of the Design,Automation and Test in Europe Conference and Exhibition. 2003. 03. 456-468.
[23] Lee Whetsel. Adapting JTAG for AC Interconnect Testing. ITC INTERNATIONAL TEST CONFERENCE. Paper 25.3. 2003. pp.96-105.
[24] Leon van de Logt, Frank van der Heyden, Tom Waayers.An extension to JTAG for at-speed debug on a system. ITC INTERNATIONAL TEST CONFERENCE. Paper 31.3.2003. pp.123-130.
[25] Mohammad H.Tehranipour, Nisar Ahmed, and Mehrdad Nourani. Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004. pp800-811.
[26] Hong-Shin Jun, Sung S. Chung and Sang H.Baeg. Removing JTAG Bottlenecks in System Interconnect Test. ITC INTERNATIONAL TEST CONFERENCE. Paper 7.3.2004. pp. 173-180.
[27] Michael L. Bushnell vishwani D.Agrawal，蒋安平，冯建华，王新安译。《Essentials of Electronic Testing for Digital,Memory & Mixed-Signal VLSI Circuits》，北京，电子工业出版社，2005．8，pp．412-430．
[28] Michael D．Ciletti，张雅绮，李锵等译，Advanced Digital Design with the Verilog HDL， 北京，电子工业出版社，2005．1，pp．603-644．