极低电压应用的低功耗低相噪压控振荡器的研究与实现
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摘要
随着近几年无线通讯系统的蓬勃发展,推动了低成本、低功耗CMOS无线收发机的研究与开发,而压控振荡器(VCO,Voltage Controlled Oscillator)是无线收发机的关键模块。作为收发机中的本地振荡源进行频率转换和信道选择,需要压控振荡器具有低功耗和低相位噪声的特点。
CMOS工艺尺寸的进一步缩小,增加了芯片的功能模块密度、器件的速度以及电路处理信号的能力。然而,为了满足可靠性,避免器件栅氧化层击穿、热载流子效应以及功耗密度过大等问题,其电源电压也在等比例地缩小。另一方面,虽然电源电压减小了,但器件的阈值电压却没有相应减小,这导致了可获得的电压摆幅变小。传统的模拟电路结构在电源电压降低到1V以下时由于没有足够的电压净空间,使得模拟电路的设计遇到了挑战。
本论文的目的是设计一个工作在极低电压(0.5V)环境下的低功耗和低相位噪声射频压控振荡器集成电路芯片。目前国际上对于极低电压环境下的VCO也只处于研究阶段,相应的产品问世尚需要一定的时间。国内对VCO的研究近几年也呈现繁荣之势,但关注的往往是正常电源电压环境下的研究,只是在追随国外已有产品的脚步前进。在国内CMOS工艺技术已经可以接近国际先进水平的情况下,有必要进行跨越式发展,研究国际上的前沿课题。这样,对快速提高我国集成电路产业的整体竞争力具有重要的意义。
本文主要工作和创新点包括:
1.探讨了片上电感的物理结构及电学模型的物理意义,研究了电感的几何尺寸参数对片上电感性能的影响,总结得到了优化电感的一系列指导原则,并根据CMOS工艺的发展,改进了文献中有关电感设计的经验报导。
2.探讨了变容管的物理结构及电学模型的物理意义,分析了不同结构变容管的优缺点及相应的应用领域,研究了偏置电压、变容管几何尺寸参数以及工作频率等对变容管性能的影响,得到了优化设计变容管的一系列指导原则。
3.深入分析总结了四种电感电容式压控振荡器的相位噪声模型:线性时不变(Lesson's)模型,线性时变(Hajimiri's)模型,非线性扰动(Demir's)模型以及类谐波平衡分析(Rael's)模型。详细分析了振荡器的内在振荡机制,总结了振荡器设计和优化的一般步骤,提出了振荡器设计中针对低相位噪声和低功耗设计的设计原则,归纳了几种相位噪声降低技术。综合应用多种技术,实现了低至0.5 V电源电压下的低功耗、低相位噪声的LC VCO的设计。
4.研究了极低电压应用的射频锁相环(PLL,Phase-Locked Loop)的设计,分别构建了鉴频鉴相器(PFD,Phase-Frequency Detector)、电荷泵(CP,Charge-Pump)以及分频器。其中鉴频鉴相器采用改进型预充电鉴频鉴相器结构,其特点是工作频率范围大,功耗低,且死区极小;电荷泵模块采用负反馈电路结构,在极低电压下能够提高充放电电流匹配度;分频器采用扩展的单相时钟动态逻辑结构,在极低电压下能够工作在3 GHz以上,且功耗很小,同时考虑了动态逻辑中动态结点漏电流的影响,给出了相应的辅助电路,弥补了这个缺点。
5.采用中芯国际0.13μm 1P8M CMOS工艺实现了工作于0.5 V电源电压下的低功耗、低相位噪声的LC VCO芯片,测试得到LC VCO能正常工作在0.5 V电压下,输出频率范围为2.1～2.3 GHz,输出相位噪声在-119.8～-121.5 dBc/Hz@1 MHz,功耗仅为685μW,计算得到综合性能指标FOM为-188.7～-190.3 dB,达到国内领先水平。以此VCO为核心,完成了相应的极低电压下低功耗、低相位噪声的PLL芯片设计,目前正在流片中。
The explosive growth in wireless communications has driven universities and companies to produce wireless transceivers at low-cost, low-power, and compact size, while the VCO is a critical device of wireless transceivers. It works as a local oscillator for frequency translation and channel selection in the transceivers but suffers phase noise.
The line-width of CMOS technologies is projected to keep scaling deeper into nanoscale dimensions for the next two decades. This will increase the functionality density, the intrinsic speed of the devices and thus the signal processing capability of the circuits. However, in order to maintain reliability, to avoid breakdown, to avoid thermal problems and to reduce power density, the maximum supply voltage has to be scaled down appropriately. But the transistor's threshold voltage is not reduced as aggressively. The low power supply voltages and the relatively large device threshold voltages are an obstacle to high performance analog circuit design. At supply voltages below 1 V, the design of analog circuits becomes very challenging since the traditional circuit techniques do not have sufficient voltage headroom.
This thesis aims at realizing a chip design of low phase noise, low power voltage-controlled oscillator integrated circuit for ultra low voltage (0.5V) application. At present, the VCO for ultra low voltage application on the international is still in its infancy. The corresponding products come out still need certain time. Research on the VCO in our country is prosperity over the past few years, but they often pay attentions on the normal supply voltage environment research, just following the footsteps of the oversea existed products. In the case that the CMOS process technology in our country can already come up to an international advanced level, so we can carry out great-leap-forward development through researching the topics at the international level. Thus, these is important significance to improving the overall competitiveness of integrated circuit industry of our country.
The main contents and innovative points of this dissertation are list below.
Firstly, it covers some general considerations like the physical analysis of the integrated inductor, the existing electrical models to model them, and some methods to improve the quality factor of an integrated inductor. And it also analyses the influence of the geometrical parameters in the inductor's performance and will establish the design guidelines for the definition of the elements geometrical characteristics. It also introduces some new techniques to improve the quality factor.
Secondly, it describes the physical phenomena that takes place in the different types of variable capacitor structures currently available in standard integrated circuits fabrication processes. And it also introduces the electric and magnetic field distributions in the varactors. Based on physical dimensions and on the properties of the fabrication processes, the electrical models of varactors are derived. Some important design rules to consider when dealing with the optimization of the performance of an integrated varactor are summarized. It also analyses the influence of the geometrical parameters in the different types of varactors' performance.
Thirdly, we have studied four analysis methods of phase noise: linear time invariant (Lesson's), linear time varying (Hajimiri's), nonlinear perturbation analysis (Demir's) and mechanistic physical model (Rael's). The underlying physics of LC oscillators is analyzed in detail. The general process of LC VCOs' design and optimization is summarized. Energy conservation and VCO phase noise theory applied to the tank design leads to the concept of systematic high inductance LC tank VCO design for low power low phase noise oscillator designs. We summarize many techniques of lowering phase noise. Using these techniques, the low phase noise low power consumption VCO can operate from a 0.5 V supply.
Fourthly, for ultra low voltage applications, in aspect of circuit implementation, various structures of PFD, CP, divider are discussed respectively. In order to overcome dead zone of PFD and improve operating frequency of circuit, a modified precharge PFD (MPTPFD) is used and optimized. With the reduced supply voltage, a novel structure for a CP circuit, which a negative feedback is employed, is proposed to achieve perfect current matching in a large range of the output voltage. The Extended True Single-Phase-Clock (ETSPC), an extension of the TSPC CMOS circuit technique, is proposed and analyzed. A complete dual-modulus prescaler is implemented, and a 3 GHz rate is achieved with low power consumption.
Finally, 3-T LC VCO is implemented in SMIC 0.13μm 1P8M CMOS process, and the CP PLL has already been taped out. Measurement results have shown that the 3-T LC VCO provide the phase noise of -119.8～-121.5 dBc/Hz at 1-MHz offset, and the range of the output frequency is about 2.1～2.3 GHz while dissipating 685μW from a 0.5 V supply. The FOM of the VCO is -188.7～-190.3 dB. This design has reached the leading level in China. Using the VCO as the key componet, an ultra low voltage, low power, low phase noise PLL is presented in this thesis and the chip is being taped out in SMIC.
CMOS工艺尺寸的进一步缩小,增加了芯片的功能模块密度、器件的速度以及电路处理信号的能力。然而,为了满足可靠性,避免器件栅氧化层击穿、热载流子效应以及功耗密度过大等问题,其电源电压也在等比例地缩小。另一方面,虽然电源电压减小了,但器件的阈值电压却没有相应减小,这导致了可获得的电压摆幅变小。传统的模拟电路结构在电源电压降低到1V以下时由于没有足够的电压净空间,使得模拟电路的设计遇到了挑战。
本论文的目的是设计一个工作在极低电压(0.5V)环境下的低功耗和低相位噪声射频压控振荡器集成电路芯片。目前国际上对于极低电压环境下的VCO也只处于研究阶段,相应的产品问世尚需要一定的时间。国内对VCO的研究近几年也呈现繁荣之势,但关注的往往是正常电源电压环境下的研究,只是在追随国外已有产品的脚步前进。在国内CMOS工艺技术已经可以接近国际先进水平的情况下,有必要进行跨越式发展,研究国际上的前沿课题。这样,对快速提高我国集成电路产业的整体竞争力具有重要的意义。
本文主要工作和创新点包括:
1.探讨了片上电感的物理结构及电学模型的物理意义,研究了电感的几何尺寸参数对片上电感性能的影响,总结得到了优化电感的一系列指导原则,并根据CMOS工艺的发展,改进了文献中有关电感设计的经验报导。
2.探讨了变容管的物理结构及电学模型的物理意义,分析了不同结构变容管的优缺点及相应的应用领域,研究了偏置电压、变容管几何尺寸参数以及工作频率等对变容管性能的影响,得到了优化设计变容管的一系列指导原则。
3.深入分析总结了四种电感电容式压控振荡器的相位噪声模型:线性时不变(Lesson's)模型,线性时变(Hajimiri's)模型,非线性扰动(Demir's)模型以及类谐波平衡分析(Rael's)模型。详细分析了振荡器的内在振荡机制,总结了振荡器设计和优化的一般步骤,提出了振荡器设计中针对低相位噪声和低功耗设计的设计原则,归纳了几种相位噪声降低技术。综合应用多种技术,实现了低至0.5 V电源电压下的低功耗、低相位噪声的LC VCO的设计。
4.研究了极低电压应用的射频锁相环(PLL,Phase-Locked Loop)的设计,分别构建了鉴频鉴相器(PFD,Phase-Frequency Detector)、电荷泵(CP,Charge-Pump)以及分频器。其中鉴频鉴相器采用改进型预充电鉴频鉴相器结构,其特点是工作频率范围大,功耗低,且死区极小;电荷泵模块采用负反馈电路结构,在极低电压下能够提高充放电电流匹配度;分频器采用扩展的单相时钟动态逻辑结构,在极低电压下能够工作在3 GHz以上,且功耗很小,同时考虑了动态逻辑中动态结点漏电流的影响,给出了相应的辅助电路,弥补了这个缺点。
5.采用中芯国际0.13μm 1P8M CMOS工艺实现了工作于0.5 V电源电压下的低功耗、低相位噪声的LC VCO芯片,测试得到LC VCO能正常工作在0.5 V电压下,输出频率范围为2.1～2.3 GHz,输出相位噪声在-119.8～-121.5 dBc/Hz@1 MHz,功耗仅为685μW,计算得到综合性能指标FOM为-188.7～-190.3 dB,达到国内领先水平。以此VCO为核心,完成了相应的极低电压下低功耗、低相位噪声的PLL芯片设计,目前正在流片中。
The explosive growth in wireless communications has driven universities and companies to produce wireless transceivers at low-cost, low-power, and compact size, while the VCO is a critical device of wireless transceivers. It works as a local oscillator for frequency translation and channel selection in the transceivers but suffers phase noise.
The line-width of CMOS technologies is projected to keep scaling deeper into nanoscale dimensions for the next two decades. This will increase the functionality density, the intrinsic speed of the devices and thus the signal processing capability of the circuits. However, in order to maintain reliability, to avoid breakdown, to avoid thermal problems and to reduce power density, the maximum supply voltage has to be scaled down appropriately. But the transistor's threshold voltage is not reduced as aggressively. The low power supply voltages and the relatively large device threshold voltages are an obstacle to high performance analog circuit design. At supply voltages below 1 V, the design of analog circuits becomes very challenging since the traditional circuit techniques do not have sufficient voltage headroom.
This thesis aims at realizing a chip design of low phase noise, low power voltage-controlled oscillator integrated circuit for ultra low voltage (0.5V) application. At present, the VCO for ultra low voltage application on the international is still in its infancy. The corresponding products come out still need certain time. Research on the VCO in our country is prosperity over the past few years, but they often pay attentions on the normal supply voltage environment research, just following the footsteps of the oversea existed products. In the case that the CMOS process technology in our country can already come up to an international advanced level, so we can carry out great-leap-forward development through researching the topics at the international level. Thus, these is important significance to improving the overall competitiveness of integrated circuit industry of our country.
The main contents and innovative points of this dissertation are list below.
Firstly, it covers some general considerations like the physical analysis of the integrated inductor, the existing electrical models to model them, and some methods to improve the quality factor of an integrated inductor. And it also analyses the influence of the geometrical parameters in the inductor's performance and will establish the design guidelines for the definition of the elements geometrical characteristics. It also introduces some new techniques to improve the quality factor.
Secondly, it describes the physical phenomena that takes place in the different types of variable capacitor structures currently available in standard integrated circuits fabrication processes. And it also introduces the electric and magnetic field distributions in the varactors. Based on physical dimensions and on the properties of the fabrication processes, the electrical models of varactors are derived. Some important design rules to consider when dealing with the optimization of the performance of an integrated varactor are summarized. It also analyses the influence of the geometrical parameters in the different types of varactors' performance.
Thirdly, we have studied four analysis methods of phase noise: linear time invariant (Lesson's), linear time varying (Hajimiri's), nonlinear perturbation analysis (Demir's) and mechanistic physical model (Rael's). The underlying physics of LC oscillators is analyzed in detail. The general process of LC VCOs' design and optimization is summarized. Energy conservation and VCO phase noise theory applied to the tank design leads to the concept of systematic high inductance LC tank VCO design for low power low phase noise oscillator designs. We summarize many techniques of lowering phase noise. Using these techniques, the low phase noise low power consumption VCO can operate from a 0.5 V supply.
Fourthly, for ultra low voltage applications, in aspect of circuit implementation, various structures of PFD, CP, divider are discussed respectively. In order to overcome dead zone of PFD and improve operating frequency of circuit, a modified precharge PFD (MPTPFD) is used and optimized. With the reduced supply voltage, a novel structure for a CP circuit, which a negative feedback is employed, is proposed to achieve perfect current matching in a large range of the output voltage. The Extended True Single-Phase-Clock (ETSPC), an extension of the TSPC CMOS circuit technique, is proposed and analyzed. A complete dual-modulus prescaler is implemented, and a 3 GHz rate is achieved with low power consumption.
Finally, 3-T LC VCO is implemented in SMIC 0.13μm 1P8M CMOS process, and the CP PLL has already been taped out. Measurement results have shown that the 3-T LC VCO provide the phase noise of -119.8～-121.5 dBc/Hz at 1-MHz offset, and the range of the output frequency is about 2.1～2.3 GHz while dissipating 685μW from a 0.5 V supply. The FOM of the VCO is -188.7～-190.3 dB. This design has reached the leading level in China. Using the VCO as the key componet, an ultra low voltage, low power, low phase noise PLL is presented in this thesis and the chip is being taped out in SMIC.
引文
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