深亚微米工艺下的Memory建库技术研究
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摘要
随着超大规模集成电路技术的飞速发展，集成电路技术更新换代的周期越来越短，设计工具的自动化称度也越来越高，而建库技术即成为设计自动化的基础。存储器的高速发展使得其在集成电路设计中举足轻重，其逻辑参数库的提取亦不可或缺，这就使得建库工作者快速提取存储器的逻辑参数成为必要。为了精确而快速地提取存储器逻辑参数，我们迫切需要自动化的软件，尽量减少建库过程中人为的影响因素，从而能够自动而快速地完成存储器的逻辑参数提取和建库工作。
然而，由于存储器单元密集和电路庞大的特点，并且存储器的增大极为迅速，使得用仿真工具直接提取逻辑参数并不现实，存储器的简化迫在眉睫。目前的参数提取测试电路由于和实际电路差别较大，也不能够精确地提取参数。而同时，目前逻辑参数库的更新工作大都是半自动的，需要人为地设计用于提取各种逻辑参数的单元电路的仿真激励波形，不但需要大量的人力物力，耗费大量的时间，而且容易引入人为的误差或错误，从而影响了逻辑参数库的质量。
针对以上问题，本文在研究已有建库技术的基础上，针对存储器的逻辑参数提取提出新的解决方案。参数提取前，在库参数精度受影响可忽略的前提下，对存储器先进行电路简化，使得存储器的提取自动化得以实现。同时，本文提出电压控制电压源的输入信号控制法，精确地反映了实际工作的情况。本文自动生成正确而又简练完备的激励波形，加快了参数提取的速度。
With fast developing of ultra-large-scale-integrated-circuits technology, it's update cycle is shorter and shorter. The library building technology has became the basic of design automation since the automation of design tools is more and more advanced. The fast growing of memory make it quite important for IC design. So quick parameter extraction is indispensable for memory. In order to extract the logic parameter of memory quickly and accurately, we need automatic tools to go on the parameter extraction and library building so as to reduce the man-made influence during the library building process.
However, since memory circuit is very large and dense and the growing of its size is amazing, it is unpractical to extract the logic parameter directly with simulation tools. So it's necessary for us to reduce the memory circuits. The current circuit under test for parameter extraction is different from the actual one, so the parameter extraction is far from accurate enough. Nowadays, most of the work of library building is semi-automatic and so much manual work is got in producing stimuli, the parameter extraction is time-consuming, and it will also introduce error or mistake frequently.
Faced with these problems, this paper presents new methods for parameter extraction of memory on the base of current research about library building technology. On the precondition that the error is acceptable, we reduce the memory circuit before we do the logic parameter extraction so as to realize extraction automation. At the same time, VCVS(Voltage-Controlled-Voltage-Source) is presented in this paper to reflect the actual situation exactly. The input stimuli is produced accurately, completely and automatically, so that the parameter extraction is more fast.
然而，由于存储器单元密集和电路庞大的特点，并且存储器的增大极为迅速，使得用仿真工具直接提取逻辑参数并不现实，存储器的简化迫在眉睫。目前的参数提取测试电路由于和实际电路差别较大，也不能够精确地提取参数。而同时，目前逻辑参数库的更新工作大都是半自动的，需要人为地设计用于提取各种逻辑参数的单元电路的仿真激励波形，不但需要大量的人力物力，耗费大量的时间，而且容易引入人为的误差或错误，从而影响了逻辑参数库的质量。
针对以上问题，本文在研究已有建库技术的基础上，针对存储器的逻辑参数提取提出新的解决方案。参数提取前，在库参数精度受影响可忽略的前提下，对存储器先进行电路简化，使得存储器的提取自动化得以实现。同时，本文提出电压控制电压源的输入信号控制法，精确地反映了实际工作的情况。本文自动生成正确而又简练完备的激励波形，加快了参数提取的速度。
With fast developing of ultra-large-scale-integrated-circuits technology, it's update cycle is shorter and shorter. The library building technology has became the basic of design automation since the automation of design tools is more and more advanced. The fast growing of memory make it quite important for IC design. So quick parameter extraction is indispensable for memory. In order to extract the logic parameter of memory quickly and accurately, we need automatic tools to go on the parameter extraction and library building so as to reduce the man-made influence during the library building process.
However, since memory circuit is very large and dense and the growing of its size is amazing, it is unpractical to extract the logic parameter directly with simulation tools. So it's necessary for us to reduce the memory circuits. The current circuit under test for parameter extraction is different from the actual one, so the parameter extraction is far from accurate enough. Nowadays, most of the work of library building is semi-automatic and so much manual work is got in producing stimuli, the parameter extraction is time-consuming, and it will also introduce error or mistake frequently.
Faced with these problems, this paper presents new methods for parameter extraction of memory on the base of current research about library building technology. On the precondition that the error is acceptable, we reduce the memory circuit before we do the logic parameter extraction so as to realize extraction automation. At the same time, VCVS(Voltage-Controlled-Voltage-Source) is presented in this paper to reflect the actual situation exactly. The input stimuli is produced accurately, completely and automatically, so that the parameter extraction is more fast.
引文
[1] Allan A. Edenfeld, D. Joyner, W. H., et al. 2001 technology roadmap for semiconductors. Computer pp.42-53.2002
[2] Henry Chang, Larry Cooke, Merrill Hunt, et al. Surviving the SOC Revolution: a guide to platform-based design. USA: KLUWER Academic Publishers. 1999
[3] Cadence, The IP Reuse Evolution, Cadence design system white paper, 1999
[4] Zeizoff P M. Circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below technology generations: an International Technology Roadmap for Semiconductors perspective. Proceedings. 16th International Conference on Solid-State and Integrated-Circuit Technology. Pp.23-28. vol.1.2001.
[5] Joz Wiak L, "Quality-driven System on a Chip Design", IEEE 2000 First International Symposium on Quality Electronic Design,pp:93-102,2000
[6] Binary Ackalloor,Dinesh Gaitonde."An Overview of Library Characterization in Semi-Cumstom Design",IEEE 1998 CUSTOM INTEGRATED CIRCUITDS CONFERENCE, pp.305-312
[7] COMPASS AutoSPICE Orline Document, USA: VLSI Technology, Inc., Version 8r4.6,1996.
[8] 陈水珑、贺祥庆、刘卫东，“COMPASS的库开发工具Mercury建立逻辑参数库应用”，电子科技导报，1997年第7期，24—26页
[9] Jan M.Rabaey,“数字集成电路设计透视”，清华大学出版社，Prentice Hall
[10] Synopsys, DesignWare, Synopsys Online Documentation,1998
[11] 李伟良，葛海通等，单元特性提取中采样点偏离现象的研究
[12] N.H.E, Weste and K.Eshraghian, Principle of CMOS VLSI Design: A System Perspective, 2nd ed., Addison-Wesley, 1993
[13] Synopsys Inc Library Compiler Reference Manual Volume 1, V 3.4, USA: Synopsys Ine
[14] J.R.Burns, "Swiching response of complementary-symmetry MOS transistor logic circuits," RCA Rev., vol.25, pp.627-61, Dec. 1964.
[15] A. I. Kayssi, K. A. Sakallah, and T. M. Burks, "Analytical Transient Response of CMOS Inverters," IEEE Tram. Circuits and Syst. Vol.39,pp.42-45, Jan. 1992.
[16] 陈永刚，张彩珍，“组合电路的故障测试生成D算法研究”，兰州铁道学院学报(自然科学版)，2002年12月第21卷第6期
[17] 余党军，郑茂生等，“基于D算法的组合电路单故障检测的代数方法”，杭州电子工业学院学报，2000年12月第20卷第6期
[18] 陈水珑、贺祥庆，“一类时序逻辑电路的逻辑参数提取激励波形自动生成”，半导体学报，2001年2月，第22卷第2期，214—218页
[19] CHEN Shuilong, HE Xiangqing, SHEN Ming et al., A Method for Auto Stimulus Waveform Generation in Auto Logic Parameter Extraction, Microelectronics and Computer, Supplement, 1998, 13(6): 142-144.
[20] L.Bisdounism,S.Nikolaidis and O.Koufopavlou, "Propagation delay and short-circuit power dissipation modeling of the CMOS inverters," IEEE Trans. Circuits Syst. Vol.45,pp.259-270,Mar.1998.
[21] K. O. Jeppson, "Modeling the Influence of the Transistor Gain Ratio and the Input-to-Output Coupling Capacitance on the CMOS Inverter Delay," IEEE J.Solid-State Circuits, vol.29, pp.646-654, June 1994.
[22] 陈水珑、贺祥庆，“逻辑参数自动提取工具的设计及实现”，清华大学学报(自然科学版)，1999年第39卷第S1期，5—8页
[23] L.Bisdounism, S.Nikolaidis, and O.Koufopavlou, "Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices," IEEE J.Solid-State Circuits, vol.33, pp.302-306, Feb. 1998.
[24] D. A. Hodges and H.G.Jackson. Analysis and Design of Digital Integrated Circuit. McGraw Hill. 1983.
[25] C.T.Sah, "Characteristics of the Metal-Oxide-Semiconductor Transistor," IEEE. Trans. Electron.Devices, vol.ED-11,pp.324-345,July 1964.
[26] T.Sakurai and A.R.Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Trans. Electron Devices,vol.38,pp.887-894, Apr. 1991.
[27] T. Sakurai, A.R. Newton. "A simple MOSFET model for circuit analysis" IEEE Trans. On electron devices, vol.38, no.4, pp.887-894, April 1991.
[28] W.H.Kao, R,Hamazaki and H.Kikuchi, A modeling and Circuit Reduction Methodology for Circuit Simulation of DRAM Circuit. IEEE International Workshop on Memory Technology, Design and Testing, pp15-20, Aug. 1995.
[29] Santanu Dutta, Shivaling S. Mahant Shetti, and Stephen L. Lusky, "A Comprehensive Delay Model for CMOS Inverters" J. of Solid State Circuits.vol.30. no.8. pp. 864-871.1995.
[30] T.Sakurai and A.R.Newton, "Delay Analysis of Series-Connected MOSFET Circuits," IEEE J.Solid-State Circuits,vol.26,pp. 122-131 ,Feb. 1991.
[31] Synopsys Inc. Primetime User's Manual. USA: Synopsys Inc.2001.
[32] N.Hedenstierna and K.O.Jeppson, CMOS circuit speed and buffer optimization,IEEE Trans.Computer-Aided Design,6(2),270-281 ,Mar. 1987.
[33] T. Sakurai and A.R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE J. Solid-State Circuits, 25(2), 584-594, April 1990.
[34] A.I. Kayssi, K.A. Sakallah, and T.M. Burks, Analytical transient response of CMOS inverters, IEEE Trans. Circuits. Syst., 39(1), 42-45, Jan. 1992.
[35] Synopsys, LIBRARY TOOLS, Synopsys Online Documentation,1998.
[36] Sente, Inc. Sente2.2 Library Development Guide, Dec.2,1996.
[37] 1-Micron Portable Library(VGT350),USA:VLSI Technology, Inc., November 1991.
[38] N. H. Weste and K. Eshraghian, Principles of CMOS VLSI Design. New York: Addson Wesley,2nd ed., 1993.
[39] 于宗光、邵锦荣、何晓娃，“ASIC单元库建库方法的研究”，半导体情报，2000年8月，第37卷第4期，1—5页．
[40] 薛庆华、张玥 刘伟，“0.25微米宏单元库的验证”，中国集成电路，2002年1月，总第44期，66—70页．
[2] Henry Chang, Larry Cooke, Merrill Hunt, et al. Surviving the SOC Revolution: a guide to platform-based design. USA: KLUWER Academic Publishers. 1999
[3] Cadence, The IP Reuse Evolution, Cadence design system white paper, 1999
[4] Zeizoff P M. Circuit, MOSFET, and front end process integration trends and challenges for the 180 nm and below technology generations: an International Technology Roadmap for Semiconductors perspective. Proceedings. 16th International Conference on Solid-State and Integrated-Circuit Technology. Pp.23-28. vol.1.2001.
[5] Joz Wiak L, "Quality-driven System on a Chip Design", IEEE 2000 First International Symposium on Quality Electronic Design,pp:93-102,2000
[6] Binary Ackalloor,Dinesh Gaitonde."An Overview of Library Characterization in Semi-Cumstom Design",IEEE 1998 CUSTOM INTEGRATED CIRCUITDS CONFERENCE, pp.305-312
[7] COMPASS AutoSPICE Orline Document, USA: VLSI Technology, Inc., Version 8r4.6,1996.
[8] 陈水珑、贺祥庆、刘卫东，“COMPASS的库开发工具Mercury建立逻辑参数库应用”，电子科技导报，1997年第7期，24—26页
[9] Jan M.Rabaey,“数字集成电路设计透视”，清华大学出版社，Prentice Hall
[10] Synopsys, DesignWare, Synopsys Online Documentation,1998
[11] 李伟良，葛海通等，单元特性提取中采样点偏离现象的研究
[12] N.H.E, Weste and K.Eshraghian, Principle of CMOS VLSI Design: A System Perspective, 2nd ed., Addison-Wesley, 1993
[13] Synopsys Inc Library Compiler Reference Manual Volume 1, V 3.4, USA: Synopsys Ine
[14] J.R.Burns, "Swiching response of complementary-symmetry MOS transistor logic circuits," RCA Rev., vol.25, pp.627-61, Dec. 1964.
[15] A. I. Kayssi, K. A. Sakallah, and T. M. Burks, "Analytical Transient Response of CMOS Inverters," IEEE Tram. Circuits and Syst. Vol.39,pp.42-45, Jan. 1992.
[16] 陈永刚，张彩珍，“组合电路的故障测试生成D算法研究”，兰州铁道学院学报(自然科学版)，2002年12月第21卷第6期
[17] 余党军，郑茂生等，“基于D算法的组合电路单故障检测的代数方法”，杭州电子工业学院学报，2000年12月第20卷第6期
[18] 陈水珑、贺祥庆，“一类时序逻辑电路的逻辑参数提取激励波形自动生成”，半导体学报，2001年2月，第22卷第2期，214—218页
[19] CHEN Shuilong, HE Xiangqing, SHEN Ming et al., A Method for Auto Stimulus Waveform Generation in Auto Logic Parameter Extraction, Microelectronics and Computer, Supplement, 1998, 13(6): 142-144.
[20] L.Bisdounism,S.Nikolaidis and O.Koufopavlou, "Propagation delay and short-circuit power dissipation modeling of the CMOS inverters," IEEE Trans. Circuits Syst. Vol.45,pp.259-270,Mar.1998.
[21] K. O. Jeppson, "Modeling the Influence of the Transistor Gain Ratio and the Input-to-Output Coupling Capacitance on the CMOS Inverter Delay," IEEE J.Solid-State Circuits, vol.29, pp.646-654, June 1994.
[22] 陈水珑、贺祥庆，“逻辑参数自动提取工具的设计及实现”，清华大学学报(自然科学版)，1999年第39卷第S1期，5—8页
[23] L.Bisdounism, S.Nikolaidis, and O.Koufopavlou, "Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices," IEEE J.Solid-State Circuits, vol.33, pp.302-306, Feb. 1998.
[24] D. A. Hodges and H.G.Jackson. Analysis and Design of Digital Integrated Circuit. McGraw Hill. 1983.
[25] C.T.Sah, "Characteristics of the Metal-Oxide-Semiconductor Transistor," IEEE. Trans. Electron.Devices, vol.ED-11,pp.324-345,July 1964.
[26] T.Sakurai and A.R.Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Trans. Electron Devices,vol.38,pp.887-894, Apr. 1991.
[27] T. Sakurai, A.R. Newton. "A simple MOSFET model for circuit analysis" IEEE Trans. On electron devices, vol.38, no.4, pp.887-894, April 1991.
[28] W.H.Kao, R,Hamazaki and H.Kikuchi, A modeling and Circuit Reduction Methodology for Circuit Simulation of DRAM Circuit. IEEE International Workshop on Memory Technology, Design and Testing, pp15-20, Aug. 1995.
[29] Santanu Dutta, Shivaling S. Mahant Shetti, and Stephen L. Lusky, "A Comprehensive Delay Model for CMOS Inverters" J. of Solid State Circuits.vol.30. no.8. pp. 864-871.1995.
[30] T.Sakurai and A.R.Newton, "Delay Analysis of Series-Connected MOSFET Circuits," IEEE J.Solid-State Circuits,vol.26,pp. 122-131 ,Feb. 1991.
[31] Synopsys Inc. Primetime User's Manual. USA: Synopsys Inc.2001.
[32] N.Hedenstierna and K.O.Jeppson, CMOS circuit speed and buffer optimization,IEEE Trans.Computer-Aided Design,6(2),270-281 ,Mar. 1987.
[33] T. Sakurai and A.R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE J. Solid-State Circuits, 25(2), 584-594, April 1990.
[34] A.I. Kayssi, K.A. Sakallah, and T.M. Burks, Analytical transient response of CMOS inverters, IEEE Trans. Circuits. Syst., 39(1), 42-45, Jan. 1992.
[35] Synopsys, LIBRARY TOOLS, Synopsys Online Documentation,1998.
[36] Sente, Inc. Sente2.2 Library Development Guide, Dec.2,1996.
[37] 1-Micron Portable Library(VGT350),USA:VLSI Technology, Inc., November 1991.
[38] N. H. Weste and K. Eshraghian, Principles of CMOS VLSI Design. New York: Addson Wesley,2nd ed., 1993.
[39] 于宗光、邵锦荣、何晓娃，“ASIC单元库建库方法的研究”，半导体情报，2000年8月，第37卷第4期，1—5页．
[40] 薛庆华、张玥 刘伟，“0.25微米宏单元库的验证”，中国集成电路，2002年1月，总第44期，66—70页．