SOI的电学性能测试以及低功耗SOI DRAM的设计研究
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摘要
与传统的体硅电路比较起来，SOI电路具有高速、低压、低功耗、抗辐照、耐高温等优点。但是由于SOI材料的制作成本比较高，所以原来它的应用主要局限在军工，航空航天等领域来制作耐高温和抗辐照电路，随着SOI衬底技术的发展，SOI园片的成本不断降低，使得SOI进入民用成为可能。随着移动通信、手提电脑等便携式电子产品的发展，集成电路在功耗和体积方面的要求越来越高，SOI将成为实现低压、低功耗的主流技术。所以，对于SOI材料，器件，电路测试，模拟仿真，设计，工艺方面的研究就显得非常的重要
本论文的主要工作分为三个部分。
第一个部分总结了SOI技术的发展历程，发展趋势及其所面临的巨大挑战。在这一部分中，重点总结了SOI技术相对于传统的体硅技术来说的优越性，SOI材料制备的方法流程，SOI新型器件的特性和工艺，以及SOI技术在抗辐照、耐高温、高速、低功耗、低压等领域内的应用及进展。
第二部分我们对高性能低功耗SOI DRAM结构的设计进行了研究，设计了一个低压低功耗SOI DRAM阵列模型，介绍了我们的DRAM的逻辑结构设计，存储单元设计，存储器阵列的设计，及读／写电路等外围电路的设计。完成了存储阵列，控制电路，外围电路的时序设计，原理图设计，版图设计，并且通过了DRC，LVS检查。同时我们针对我们的电路和特定的器件进行了模拟仿真。我们分析了SOI技术应用到我们的SOI DRAM电路上所能获得的优点，并且把我们针对设计的电路和传统的体硅电路进行了对比。
第三部分，我们对SOI材料器件的电学性能测试进行了深入的研究。针对SOI材料与传统的体硅材料在结构上的不同，我们分别用三种不同的电学性能测试模型来进行SOI材料的电学表征。这三种模型分别是：第一，将传统的MOS电容结构应用到SOI材料上来进行C-V，I-V测试，分析计算SOI材料的重要电学性能参数；第二种，针对SOI材料的特殊结构，为了适应生产线上对无损SOI园片进行电学性能测试的要求，应用MOSOS结构来对SOI材料进行电学性能表征。第三种，为了简化SOI材料的电学性能测试结构，使它的测试，分析，计算
摘要
与传统的MOS模型相兼容，我们通过引入一个耦合因子，将传统的MOS模型
的测试方法，公式引入SOI材料的C－V，I刁测试过程。应用SIS模型来进行SOI
材料的电学表征。
本课题由中科院知识创新工程项目《SOI材料和器件》，上海市集成电路设计
中心与美国AM公司的AM基金资助。
Silicon on Insulator (SOI) Technology was originally invented for the niche of radiation-hard circuits. High speed, low voltage and radiation-hardness are mam three advantages presented by SOI over bulk. Since the cost to produce SOI materials was high in the past, the application of SOI materials was limited in military industry and aerospace. More recently, the advent of new SOI wafer fabrication techniques and the explosive growth of portable microelectronic devices have attracted considerable attention on SOI for the fabrication of low-power (LP), low-voltage (LV), and high-frequency (HF) CMOS circuits.
In this thesis, we study the electrical characterization on SOI wafers and design a low-power SOI CMOS DRAM structure.
The electrical parameters of buried oxide and interface state in SOI structures influence the performance, reliability and the radiation hardness of devices fabricated in the superficial silicon film. Based on the experimental results and theory analysis, the characteristics of SOI wafers were discussed through using three different electrical characterization models: MOS, SIS, and MOSOS. SIMOX SOI wafers produced by ion implant processes were used in this experiment. The results for SIMOX SOI samples we got here revealed that all the three structures are valuable for SOI electrical characterization and SIS structure has irrefragable advantage over the other two structures.
The SOI transistors have been the key devices for achieving the low voltage operation and low power consumption, because of the small junction capacitance, the small S-factor, and the small substrate bias effect. In our work, the stressless DRAM array has been newly developed for the lower voltage operation. In addition to the DRAM array, the logic circuitry with the body-bias-controlled SOI transistors has been developed for high-speed operation. Combine some new techniques for power reduction and our DRAM array, we design a new low-power SOI CMOS DRAM structure and study the performance of our circuits. The results we got in the simulation and test are valuable.
m
Abstract
Our Thesis was supported by Project of Knowledge Innovation Program of the Chinese Academy of Sciences and AM fund of Shanghai 1C Design Center and AM Inc. USA.
本论文的主要工作分为三个部分。
第一个部分总结了SOI技术的发展历程，发展趋势及其所面临的巨大挑战。在这一部分中，重点总结了SOI技术相对于传统的体硅技术来说的优越性，SOI材料制备的方法流程，SOI新型器件的特性和工艺，以及SOI技术在抗辐照、耐高温、高速、低功耗、低压等领域内的应用及进展。
第二部分我们对高性能低功耗SOI DRAM结构的设计进行了研究，设计了一个低压低功耗SOI DRAM阵列模型，介绍了我们的DRAM的逻辑结构设计，存储单元设计，存储器阵列的设计，及读／写电路等外围电路的设计。完成了存储阵列，控制电路，外围电路的时序设计，原理图设计，版图设计，并且通过了DRC，LVS检查。同时我们针对我们的电路和特定的器件进行了模拟仿真。我们分析了SOI技术应用到我们的SOI DRAM电路上所能获得的优点，并且把我们针对设计的电路和传统的体硅电路进行了对比。
第三部分，我们对SOI材料器件的电学性能测试进行了深入的研究。针对SOI材料与传统的体硅材料在结构上的不同，我们分别用三种不同的电学性能测试模型来进行SOI材料的电学表征。这三种模型分别是：第一，将传统的MOS电容结构应用到SOI材料上来进行C-V，I-V测试，分析计算SOI材料的重要电学性能参数；第二种，针对SOI材料的特殊结构，为了适应生产线上对无损SOI园片进行电学性能测试的要求，应用MOSOS结构来对SOI材料进行电学性能表征。第三种，为了简化SOI材料的电学性能测试结构，使它的测试，分析，计算
摘要
与传统的MOS模型相兼容，我们通过引入一个耦合因子，将传统的MOS模型
的测试方法，公式引入SOI材料的C－V，I刁测试过程。应用SIS模型来进行SOI
材料的电学表征。
本课题由中科院知识创新工程项目《SOI材料和器件》，上海市集成电路设计
中心与美国AM公司的AM基金资助。
Silicon on Insulator (SOI) Technology was originally invented for the niche of radiation-hard circuits. High speed, low voltage and radiation-hardness are mam three advantages presented by SOI over bulk. Since the cost to produce SOI materials was high in the past, the application of SOI materials was limited in military industry and aerospace. More recently, the advent of new SOI wafer fabrication techniques and the explosive growth of portable microelectronic devices have attracted considerable attention on SOI for the fabrication of low-power (LP), low-voltage (LV), and high-frequency (HF) CMOS circuits.
In this thesis, we study the electrical characterization on SOI wafers and design a low-power SOI CMOS DRAM structure.
The electrical parameters of buried oxide and interface state in SOI structures influence the performance, reliability and the radiation hardness of devices fabricated in the superficial silicon film. Based on the experimental results and theory analysis, the characteristics of SOI wafers were discussed through using three different electrical characterization models: MOS, SIS, and MOSOS. SIMOX SOI wafers produced by ion implant processes were used in this experiment. The results for SIMOX SOI samples we got here revealed that all the three structures are valuable for SOI electrical characterization and SIS structure has irrefragable advantage over the other two structures.
The SOI transistors have been the key devices for achieving the low voltage operation and low power consumption, because of the small junction capacitance, the small S-factor, and the small substrate bias effect. In our work, the stressless DRAM array has been newly developed for the lower voltage operation. In addition to the DRAM array, the logic circuitry with the body-bias-controlled SOI transistors has been developed for high-speed operation. Combine some new techniques for power reduction and our DRAM array, we design a new low-power SOI CMOS DRAM structure and study the performance of our circuits. The results we got in the simulation and test are valuable.
m
Abstract
Our Thesis was supported by Project of Knowledge Innovation Program of the Chinese Academy of Sciences and AM fund of Shanghai 1C Design Center and AM Inc. USA.
引文
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[2]. Manners, D., "Portables Prompt Low-Power Chips," Electronics Weekly, no. 1574, p. 22, Nov. 13, 1991.
[3]. Stephany, R. et al., "A 200MHz 32b 0.5W CMOS RISC Microprocessor," in ISSCC Digest of Technical Papers, pp. 15.5-1 to 15.5-2, Feb. 1998.
[4]. Igura, H. et al., "An 800MOPS 100mW 1.5V Parallel DSP for Mobile Multimedia Processing," in ISSCC Digest of Technical Papers, pp. 18.3-1 to 18.3-2, Feb., 1998.
[5]. Sharma, A. K., Semiconductor Memories -- Technology, Testing and Reliability, IEEE Press, 1997.
[6]. Margala, M. and Durdle, N. G., "Noncomplementary BiCMOS Logic and CMOS Logic Styles for Low-Voltage Low-Power Operation -- A Comparative Study," IEEE Journal of Solid-State Circuits, vol. 33, no. 10, pp. 1580-1585, Oct. 1998.
[7]. Margala, M. and Durdle, N. G., "1.2 V Full-Swing BiNMOS Logic Gate," Microelectronics Journal, vol. 29, no. 7, pp. 421-429, Jul. 1998.
[8]. Fujisawa, H. et al., "The Charge-Share Modified (CSM) Precharge-Level Architecture for High-Speed and Low-Power Ferroelectric Memory," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 655-661, May 1997.
[9]. Womack, R. et al., "A 16-kb ferroelectric nonvolatile memory with a bit parallel architecture," in ISSCC Digest of Technical Papers, pp. 242-243, Feb. 1989.
[10]33. Bellaouar, A. and Elmasry, M. I., Low-Power Digital VLSI Design, Circuits and Systems, Kluwer Academic Publishers, 1996.
[11]. Itoh, K. et al., "Trends in Low-Power RAM Circuit Technologies," Proceedings of the IEEE, pp. 524-543, Apr. 1995.
[12]. Amrutur, B. S. and Horowitz, M. A., "Techniques to Reduce Power in Fast Wide Memories," in Proceedings of SLPE'94, pp. 92-93, 1994.
[13]. Aoki, M. and Itoh, K., "Low-Voltage and Low-Power ULSI Circuit Techniques," IEICE Transactions on Electronics, vol. E77-C, no. 8, pp. 1351-1360, Aug. 1994.
[14]. Suzuki, T. et al., "High-Speed Circuit Techniques for Battery-Operated 16 MBit CMOS DRAM," IEICE Transactions on Electronics, vol. E77-C, no. 8, pp. 1334-1342, Aug. 1994.
[15]. Lee, K. et al., "Low-Voltage, High-Speed Circuit Designs for Gigabit DRAM's," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 642-648, May 1997.
[16]. Itoh, K. et al., "Limitations and Challenges of Multigigabit DRAM Chip Design," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 624-634, May 1997.
[17]. Lee, K.-C. et al., "A 1GBit SDRAM with an Independent Sub-Array Controlled Scheme and a Hierarchical Decoding Scheme," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 103-104, Jun. 1997.
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[19]. Tsuruda, T. et al., "High-Speed/High-Bandwidth Design Methodologies for On-Chip DRAM Core Multimedia System LSI's," IEEE Journal of Solid-State Circuits, vol. 32, no. 3, pp. 477-482, Mar. 1997.
[20]. Joo, J.-H. et al., "A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte/s Bandwidth," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1635-11644, Nov. 1996.
[21]. Eto, S. et al., "A 1-Gb SDRAM with Ground-Level Precharged Bit Line and Nonboosted 2.1-V Word Line," IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp. 1697-1702, Nov. 1998.
[22]. Kato, Y. et al., "Non-Precharged Bit-Line Sensing Scheme for High-Speed Low-Power DRAMs," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 16-17, Jun. 1998.
[23]. Tsikikawa, Y. et al., "An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5V DRAMs," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 85-86, May 1993.
[24]. Tanaka, H. et al., "A Precise On-Chip Voltage Generator for a Giga-Scale DRAM with a Negative Word-Line Scheme," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 94-95, Jun. 1998.
[25]. Seta, K. et al., "50% Active Power Saving Without Speed Degradation Using Standby Power Reduction (SPA) Circuit," in ISSCC Digest of Technical Papers, pp. 318-319, Feb. 1995.
[26]. Song, H. J., "A Self-Off-Time Detector for Reducing Standby Current of DRAM," IEEE Journal of Solid-State Circuits, vol. 32, no. 10, pp. 1535-1542, Oct. 1997.
[27]. Tsukude, M. et al., "A 1.2- to 3.3-V Wide Voltage-Range/Low-Power DRAM with a Charge-Transfer Presensing Scheme," IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1721-1727, Nov. 1997.
[28]. Shimomura, K. et al., "A 1-V 46-ns 16-Mb SOI-DRAM with Body Control Technique," IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1712-1720, Nov. 1997.
[29]. Okudi, T. and Murotani, T., "A Four-Level Storage 4-Gb DRAM," IEEE Journal of Solid- State Circuits, vol. 32, no. 11, pp. 1743-1747, Nov. 1997.
[30]. Idei, Y. et al., "Dual-Period Self-Refresh Scheme for Low-Power DRAM's with On-Chip PROM Mode Register," IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 253-259, Feb. 1998.
[31]. Cristoloveanu, S. and Li, S. S., Electrical Characterization of SOI Materials and Devices, Kluwer, Norwell, 1995.
[32]. Cristoloveanu, S., "A review of the electrical properties of SIMOX substrates and their impact on device performance," J. Electrochem. Soc., 138, 3131, 1991.
[33]. Sato, N., Ishii, S., Matsumura, S., Ito, M., Nakayama, J., and Yonehara, T., "Reduction of crystalline defects to 50/cm 2 in epitaxial layers over porous silicon for Eltran," IEEE Int. SOI Conf., Stuart, FL, 1998.
[34]. Tsuchiya, T., Ohno, T. , and Kado, Y., "Present status and potential of subquarter-micron ultra-thin-film CMOS/SIMOX technology," SOI Technology and Devices, Electrochem. Soc., Pennington, 401, 1994.
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[38]. Ohmura, Y., Ishiyama, T., Shoji, M., and Izumi, K., "Quantum mechanical transport characteristics in ultimately miniaturized MOSFETs/SIMOX," SOI Technology and Devices, Electrochem. Soc., Pennington, 199, 1996.
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[43]. Murotani, T. et al., "A 4-Level Storage 4Gb DRAM," ISSCC Dig. Tech. Papers, pp. 74-75, Feb. 1997.
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[47] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETss", International Electron Device Meeting, pp.719-722, 2000.
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[2]. Manners, D., "Portables Prompt Low-Power Chips," Electronics Weekly, no. 1574, p. 22, Nov. 13, 1991.
[3]. Stephany, R. et al., "A 200MHz 32b 0.5W CMOS RISC Microprocessor," in ISSCC Digest of Technical Papers, pp. 15.5-1 to 15.5-2, Feb. 1998.
[4]. Igura, H. et al., "An 800MOPS 100mW 1.5V Parallel DSP for Mobile Multimedia Processing," in ISSCC Digest of Technical Papers, pp. 18.3-1 to 18.3-2, Feb., 1998.
[5]. Sharma, A. K., Semiconductor Memories -- Technology, Testing and Reliability, IEEE Press, 1997.
[6]. Margala, M. and Durdle, N. G., "Noncomplementary BiCMOS Logic and CMOS Logic Styles for Low-Voltage Low-Power Operation -- A Comparative Study," IEEE Journal of Solid-State Circuits, vol. 33, no. 10, pp. 1580-1585, Oct. 1998.
[7]. Margala, M. and Durdle, N. G., "1.2 V Full-Swing BiNMOS Logic Gate," Microelectronics Journal, vol. 29, no. 7, pp. 421-429, Jul. 1998.
[8]. Fujisawa, H. et al., "The Charge-Share Modified (CSM) Precharge-Level Architecture for High-Speed and Low-Power Ferroelectric Memory," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 655-661, May 1997.
[9]. Womack, R. et al., "A 16-kb ferroelectric nonvolatile memory with a bit parallel architecture," in ISSCC Digest of Technical Papers, pp. 242-243, Feb. 1989.
[10]33. Bellaouar, A. and Elmasry, M. I., Low-Power Digital VLSI Design, Circuits and Systems, Kluwer Academic Publishers, 1996.
[11]. Itoh, K. et al., "Trends in Low-Power RAM Circuit Technologies," Proceedings of the IEEE, pp. 524-543, Apr. 1995.
[12]. Amrutur, B. S. and Horowitz, M. A., "Techniques to Reduce Power in Fast Wide Memories," in Proceedings of SLPE'94, pp. 92-93, 1994.
[13]. Aoki, M. and Itoh, K., "Low-Voltage and Low-Power ULSI Circuit Techniques," IEICE Transactions on Electronics, vol. E77-C, no. 8, pp. 1351-1360, Aug. 1994.
[14]. Suzuki, T. et al., "High-Speed Circuit Techniques for Battery-Operated 16 MBit CMOS DRAM," IEICE Transactions on Electronics, vol. E77-C, no. 8, pp. 1334-1342, Aug. 1994.
[15]. Lee, K. et al., "Low-Voltage, High-Speed Circuit Designs for Gigabit DRAM's," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 642-648, May 1997.
[16]. Itoh, K. et al., "Limitations and Challenges of Multigigabit DRAM Chip Design," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 624-634, May 1997.
[17]. Lee, K.-C. et al., "A 1GBit SDRAM with an Independent Sub-Array Controlled Scheme and a Hierarchical Decoding Scheme," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 103-104, Jun. 1997.
[18]. Lee, K. et al., "A 1GBit SDRAM with an Independent Sub-Array Controlled Scheme and a Hier-archical Decoding Scheme," IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 779-786, May 1998.
[19]. Tsuruda, T. et al., "High-Speed/High-Bandwidth Design Methodologies for On-Chip DRAM Core Multimedia System LSI's," IEEE Journal of Solid-State Circuits, vol. 32, no. 3, pp. 477-482, Mar. 1997.
[20]. Joo, J.-H. et al., "A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte/s Bandwidth," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1635-11644, Nov. 1996.
[21]. Eto, S. et al., "A 1-Gb SDRAM with Ground-Level Precharged Bit Line and Nonboosted 2.1-V Word Line," IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp. 1697-1702, Nov. 1998.
[22]. Kato, Y. et al., "Non-Precharged Bit-Line Sensing Scheme for High-Speed Low-Power DRAMs," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 16-17, Jun. 1998.
[23]. Tsikikawa, Y. et al., "An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5V DRAMs," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 85-86, May 1993.
[24]. Tanaka, H. et al., "A Precise On-Chip Voltage Generator for a Giga-Scale DRAM with a Negative Word-Line Scheme," in Digest of Technical Papers of Symposium on VLSI Circuits, pp. 94-95, Jun. 1998.
[25]. Seta, K. et al., "50% Active Power Saving Without Speed Degradation Using Standby Power Reduction (SPA) Circuit," in ISSCC Digest of Technical Papers, pp. 318-319, Feb. 1995.
[26]. Song, H. J., "A Self-Off-Time Detector for Reducing Standby Current of DRAM," IEEE Journal of Solid-State Circuits, vol. 32, no. 10, pp. 1535-1542, Oct. 1997.
[27]. Tsukude, M. et al., "A 1.2- to 3.3-V Wide Voltage-Range/Low-Power DRAM with a Charge-Transfer Presensing Scheme," IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1721-1727, Nov. 1997.
[28]. Shimomura, K. et al., "A 1-V 46-ns 16-Mb SOI-DRAM with Body Control Technique," IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1712-1720, Nov. 1997.
[29]. Okudi, T. and Murotani, T., "A Four-Level Storage 4-Gb DRAM," IEEE Journal of Solid- State Circuits, vol. 32, no. 11, pp. 1743-1747, Nov. 1997.
[30]. Idei, Y. et al., "Dual-Period Self-Refresh Scheme for Low-Power DRAM's with On-Chip PROM Mode Register," IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 253-259, Feb. 1998.
[31]. Cristoloveanu, S. and Li, S. S., Electrical Characterization of SOI Materials and Devices, Kluwer, Norwell, 1995.
[32]. Cristoloveanu, S., "A review of the electrical properties of SIMOX substrates and their impact on device performance," J. Electrochem. Soc., 138, 3131, 1991.
[33]. Sato, N., Ishii, S., Matsumura, S., Ito, M., Nakayama, J., and Yonehara, T., "Reduction of crystalline defects to 50/cm 2 in epitaxial layers over porous silicon for Eltran," IEEE Int. SOI Conf., Stuart, FL, 1998.
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