深亚微米移动多媒体处理器的节电技术
摘要
如今,集成电路和计算机系统正变得越来越复杂。对于总体系统设计来说,功耗在设计中的地位已变得越来越重要,这是电子工业发展的必然趋势。电子工业发展总的趋势是提供更小、更轻和功能更强大的最终产品。目前许多产品领域中还出现了无线和便携式的要求,从功率观点看设计任务将变得更加艰巨。
便携式产品是IT技术融合、发展的必然产物,是一个全新的数字多媒体终端。便携式是我们消费电子娱乐产品的发展必然趋势,处于移动状态的终端会越来越多,在市场竞争非常激烈的同时,新的技术方案也不断涌现,引发新一轮个人便携多媒体终端及相关配套市场发展的浪潮,也迎来了前所未有的机遇和挑战,产品功能日趋完善的同时,电源的稳定性以及功耗问题也日显突出。
飞思卡尔iMX21深亚微米移动多媒体处理器的well bias节电结构可以对PMOS与NMOS的衬底偏置电压进行调节。从静态电流的模拟分析中我们能够看到没有well bias节电结构的芯片与带有well bias节电结构的芯片相比,漏电流提高了10倍。同时从这些实验数据中我们能够得出,P型阱的衬底偏置为-1V, N型阱的衬底偏置为Vdd+0.6V时。整个器件的漏电流最小。
在大多数情形下,对低功耗的要求必须同时满足对高芯片密度以及高吞吐量电路的同等迫切的要求。在前沿的技术中,降低功耗是一项关键人物,特别是随着晶体管尺寸的缩小而在硅片上增加晶体管密度的情况下。降低功耗也是数字电路设计的一项重要目标。本文讨论基于低功耗CMOS电路的各种设计技术。并重点阐明阱极偏置(well bias)节电技术在目前超深亚微米(0.13微米以下)工艺条件下对漏电功耗的控制。并已飞思卡尔iMX21深亚微米移动多媒体处理器为例。阐述阱极偏置(well bias)节电技术从设计到验证的整个环节。
With scaling of processes there is an increased need for decreasing the leakage current drawn by the digital logic of chips. The advantage of reducing the leakage current is increased battery life. This becomes especially important in the case of handheld devices, cellular phones etc. the most important features of mobile device design is low power consumption.
The wellbias circuit is designed to reduced the leakage current of the ARM926 platform (lo-vt transistors in Hip7A by increasing the threshold voltage during the standby mode. This in turn reduces the leakage current by 10x or more as shown in the simulations. This is achieved by increasing the p and n-well voltages. Silicon characteristics show that the optimum biasing voltage for the n-well is about 0.6v above vdd (1.5v), and for the p-well is about -1v below vss (0v).
Well biasing effectively raises the threshold of the devices thus lowering subthreshold leakage currents. It is estimated that an order of magnitude reduction in leakage currents can be acheived by back biasing the N-well by 500-600mV and the P-well by -1V. In order to back bias the wells, a charge pump is required and modifications to the current SoC methodology must be made. This document discusses some of the technical concepts regarding well biasing as well as the methodology improvements that must be made to incorporate well biasing into the SoC design flow.
便携式产品是IT技术融合、发展的必然产物,是一个全新的数字多媒体终端。便携式是我们消费电子娱乐产品的发展必然趋势,处于移动状态的终端会越来越多,在市场竞争非常激烈的同时,新的技术方案也不断涌现,引发新一轮个人便携多媒体终端及相关配套市场发展的浪潮,也迎来了前所未有的机遇和挑战,产品功能日趋完善的同时,电源的稳定性以及功耗问题也日显突出。
飞思卡尔iMX21深亚微米移动多媒体处理器的well bias节电结构可以对PMOS与NMOS的衬底偏置电压进行调节。从静态电流的模拟分析中我们能够看到没有well bias节电结构的芯片与带有well bias节电结构的芯片相比,漏电流提高了10倍。同时从这些实验数据中我们能够得出,P型阱的衬底偏置为-1V, N型阱的衬底偏置为Vdd+0.6V时。整个器件的漏电流最小。
在大多数情形下,对低功耗的要求必须同时满足对高芯片密度以及高吞吐量电路的同等迫切的要求。在前沿的技术中,降低功耗是一项关键人物,特别是随着晶体管尺寸的缩小而在硅片上增加晶体管密度的情况下。降低功耗也是数字电路设计的一项重要目标。本文讨论基于低功耗CMOS电路的各种设计技术。并重点阐明阱极偏置(well bias)节电技术在目前超深亚微米(0.13微米以下)工艺条件下对漏电功耗的控制。并已飞思卡尔iMX21深亚微米移动多媒体处理器为例。阐述阱极偏置(well bias)节电技术从设计到验证的整个环节。
With scaling of processes there is an increased need for decreasing the leakage current drawn by the digital logic of chips. The advantage of reducing the leakage current is increased battery life. This becomes especially important in the case of handheld devices, cellular phones etc. the most important features of mobile device design is low power consumption.
The wellbias circuit is designed to reduced the leakage current of the ARM926 platform (lo-vt transistors in Hip7A by increasing the threshold voltage during the standby mode. This in turn reduces the leakage current by 10x or more as shown in the simulations. This is achieved by increasing the p and n-well voltages. Silicon characteristics show that the optimum biasing voltage for the n-well is about 0.6v above vdd (1.5v), and for the p-well is about -1v below vss (0v).
Well biasing effectively raises the threshold of the devices thus lowering subthreshold leakage currents. It is estimated that an order of magnitude reduction in leakage currents can be acheived by back biasing the N-well by 500-600mV and the P-well by -1V. In order to back bias the wells, a charge pump is required and modifications to the current SoC methodology must be made. This document discusses some of the technical concepts regarding well biasing as well as the methodology improvements that must be made to incorporate well biasing into the SoC design flow.
引文
1。韦恩。沃尔夫著,现代VLSI设计------系统芯片设计(张欣,王占平,胡永大,韩磊译)。北京科学出版社
2。Kaushik Roy and Sharat C. Prasad. Low Power CMOS VLSI Circuit Design. New York: Wiley Interscience 2000.
3。T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, T. Sakurai, A0.9V, 150MHz, 10-mW, 4mm2, 2-D discrete cosine transform core processor with variable threshold-voltage scheme. IEEE Journal of Solid-State Circuits, 31(11), November 1996, pp 1770-1779.
4。H.Mizuno K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda, K. Uchiyama (from HITACHI), An 18-uA Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode, IEEE Journal of Solid-State Circuits, Vol. 34, No. 11, November 1999.
5。Fundamentals of Logic Design, C. Roth. PWS Publishing Company, Boston,1995.
6。R.C. Taft and P. Pelley, A Low Voltage, High Efficiency Charge Pump for On-Chip DC-to-DC Conversion. Motorola internal document, APRDL, Austin.
7。K Wang, K. Teng, M. Bader, R. Kung, A Low Standby Power, High Efficiency, Clamped P-well Bias Genberator for High Density Fast SRAMs, Motorola internal document, MOS Memory Product Division, Austin, 1988.
8。曾芷德。数字系统测试与可测性。长沙:国防科技大学出版社。1992
9。范鹏程等。用于IDDQ测试的片内电流传感器。微电子测试,1997(1):28～38。
10。Razavi B. Design of Analog CMOS Integrated Circuits[M]. New Yorks, McGraw-Hill, 2001
11。R.Jacob Baker, Harry W.Li, David E.Boyce. CMOS Circuit Design, Layout, and Simulation, John Wiley &Sons,Inc,1998
12。规划与布局—片上系统物理设计的核心问题探讨。计算机世界报2005年10月24日第41期B4、B5
13。毕查德。拉查维著,模拟CMOS集成电路设计(陈贵灿,程军,张瑞智译)。西安交通大学出版社。
14. R.S. Muller and T.I.Kamins. Device Electronics for Integrated Circuits. Second Ed., New York:Wiley, 1986.
15. Y.Tsividis. Operation and Modeling of the MOS Transistor. Second Ed. , Boston: McGraw-Hill, 1999.
16. Y.Taur and T.H.Ning. Fundamentals of Modern VLSI Devices. New York:Cambridge University Press, 1998.
17. Dwight Hill, Don Shugard, John Fishburn and Kurt Keutzer, Algorithms and Techniques for VLSI Layout Synthesis, Kluwer Academic Publisher, Norwell, MA, 1989.
18. Edward S. Yang, Fundamentals of Semiconductor Devices, McGraw-Hill, 1978.
19. L. W. Nagel,“SPICE 2: A Computer Program to Simulate Semiconductor Circuits,”UCB/ERL M520, University of California, May 1975.
20. Randall L. Geiger, Phillip E. Allen, Noel R. Strader, VLSI: Design Techniques for Analog and Digital Circuits, McGraw-Hill, 1990
2。Kaushik Roy and Sharat C. Prasad. Low Power CMOS VLSI Circuit Design. New York: Wiley Interscience 2000.
3。T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, T. Sakurai, A0.9V, 150MHz, 10-mW, 4mm2, 2-D discrete cosine transform core processor with variable threshold-voltage scheme. IEEE Journal of Solid-State Circuits, 31(11), November 1996, pp 1770-1779.
4。H.Mizuno K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda, K. Uchiyama (from HITACHI), An 18-uA Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode, IEEE Journal of Solid-State Circuits, Vol. 34, No. 11, November 1999.
5。Fundamentals of Logic Design, C. Roth. PWS Publishing Company, Boston,1995.
6。R.C. Taft and P. Pelley, A Low Voltage, High Efficiency Charge Pump for On-Chip DC-to-DC Conversion. Motorola internal document, APRDL, Austin.
7。K Wang, K. Teng, M. Bader, R. Kung, A Low Standby Power, High Efficiency, Clamped P-well Bias Genberator for High Density Fast SRAMs, Motorola internal document, MOS Memory Product Division, Austin, 1988.
8。曾芷德。数字系统测试与可测性。长沙:国防科技大学出版社。1992
9。范鹏程等。用于IDDQ测试的片内电流传感器。微电子测试,1997(1):28～38。
10。Razavi B. Design of Analog CMOS Integrated Circuits[M]. New Yorks, McGraw-Hill, 2001
11。R.Jacob Baker, Harry W.Li, David E.Boyce. CMOS Circuit Design, Layout, and Simulation, John Wiley &Sons,Inc,1998
12。规划与布局—片上系统物理设计的核心问题探讨。计算机世界报2005年10月24日第41期B4、B5
13。毕查德。拉查维著,模拟CMOS集成电路设计(陈贵灿,程军,张瑞智译)。西安交通大学出版社。
14. R.S. Muller and T.I.Kamins. Device Electronics for Integrated Circuits. Second Ed., New York:Wiley, 1986.
15. Y.Tsividis. Operation and Modeling of the MOS Transistor. Second Ed. , Boston: McGraw-Hill, 1999.
16. Y.Taur and T.H.Ning. Fundamentals of Modern VLSI Devices. New York:Cambridge University Press, 1998.
17. Dwight Hill, Don Shugard, John Fishburn and Kurt Keutzer, Algorithms and Techniques for VLSI Layout Synthesis, Kluwer Academic Publisher, Norwell, MA, 1989.
18. Edward S. Yang, Fundamentals of Semiconductor Devices, McGraw-Hill, 1978.
19. L. W. Nagel,“SPICE 2: A Computer Program to Simulate Semiconductor Circuits,”UCB/ERL M520, University of California, May 1975.
20. Randall L. Geiger, Phillip E. Allen, Noel R. Strader, VLSI: Design Techniques for Analog and Digital Circuits, McGraw-Hill, 1990