16bit音频过采样DAC的FPGA设计实现
|
摘要
基于∑-△噪声整形技术和过采样技术的数模转换器(DAC)可以可靠地把数字信号转换成为高精度的模拟信号。采用这一结构进行数模转换具有诸多优点,例如极低的失配噪声和高的可靠性,便于作为IP模块嵌入到其他芯片系统中等,更重要的是可以得到其他DAC结构所无法达到的精度和动态范围。在高精度测量、音频转换、汽车电子等领域有着广泛的应用价值。
由于非线性和不稳定性的存在,高阶∑-△调制器的设计与实现存在较大的难度。本设计综合大量文献中的经验原则和方法,首先阐述了∑-△调制器的一般原理,并讨论了一般结构调制器的设计过程,然后描述了稳定的高阶高精度调制器的设计流程。根据市场需求,设定了整个设计方案的性能指标,并据此设计了达到16bit精度和满量程输入范围的三阶128倍过采样调制器。
本设计采用∑-△结构,根据系统要求设计了量化器位数、调制器过采样比和阶数。在分析高阶单环路调制器稳定性的基础上,成功设计了六位量化三阶单环路调制器结构。在16比特的输入信号下,达到了90dB左右的信噪比。该设计已经在Cyclone系列FPGA器件下得到硬件实现和验证,并实现了实时音频验证。测试表明,该DAC模块输出信号的信噪比能满足16比特数据转换应用的分辨率要求,并具备良好的兼容性和通用性。
本设计可作为IP核广泛地在其他系统中进行复用,具有很强的应用性和一定的创新性。
Digital-to-analog Convertor (DAC), based on∑-△noise-shaping and over-sampling tech-niques, can convert digital signal to high resolution analog signal reliably. It has many advantages in converting, such as the ultimate low mismatch, high reliability and being able to embed to other SOC as an IP- core module. The more important is its high resolution and dynamic range compar-ing to other DAC structures. Therefore, it is widely used in high-resolution measurements, audio converting, car electronics, and other fields.
It is difficult to design and implement a high-order∑-△modulator due to the non-linearity and the non-stability. Based on a synthesis of many empirical principals and methods from refer-ences, the basic principles of∑-△modulator is described in this paper at first. And the design flow of modulator with common structure is discussed. Then, a design flow of stable, high-order and high-resolution modulator is proposed. The performance parameters of such modulator design scheme are specified according to the market requirement. Based on the scheme, a 16-bit resolu-tion, full-scale input range and three-order 128 over-sampling modulator design is accomplished in this paper.
∑-△structure is adopted in this paper, the quantization bit, oversampling ratio and order of the modulator are determined following the system requirement. Six bit quantization, three-order single-loop structure modulator is implemented after a deep stability analysis of high-order sin-gle-loop modulator. This design has been implemented and verified on the Cyclone FPGA plat-form, with the real-time audio signal verification. Testing results indicates that the SNR of the de-signed DAC module’s output signals meets the resolution requirement in 16-bit data-convention application, possessing favorable compatibility and universal ability also.
The DAC module developed in this paper could be reused as an IP core in other SOC systems, holding strong application performance and innovation.
由于非线性和不稳定性的存在,高阶∑-△调制器的设计与实现存在较大的难度。本设计综合大量文献中的经验原则和方法,首先阐述了∑-△调制器的一般原理,并讨论了一般结构调制器的设计过程,然后描述了稳定的高阶高精度调制器的设计流程。根据市场需求,设定了整个设计方案的性能指标,并据此设计了达到16bit精度和满量程输入范围的三阶128倍过采样调制器。
本设计采用∑-△结构,根据系统要求设计了量化器位数、调制器过采样比和阶数。在分析高阶单环路调制器稳定性的基础上,成功设计了六位量化三阶单环路调制器结构。在16比特的输入信号下,达到了90dB左右的信噪比。该设计已经在Cyclone系列FPGA器件下得到硬件实现和验证,并实现了实时音频验证。测试表明,该DAC模块输出信号的信噪比能满足16比特数据转换应用的分辨率要求,并具备良好的兼容性和通用性。
本设计可作为IP核广泛地在其他系统中进行复用,具有很强的应用性和一定的创新性。
Digital-to-analog Convertor (DAC), based on∑-△noise-shaping and over-sampling tech-niques, can convert digital signal to high resolution analog signal reliably. It has many advantages in converting, such as the ultimate low mismatch, high reliability and being able to embed to other SOC as an IP- core module. The more important is its high resolution and dynamic range compar-ing to other DAC structures. Therefore, it is widely used in high-resolution measurements, audio converting, car electronics, and other fields.
It is difficult to design and implement a high-order∑-△modulator due to the non-linearity and the non-stability. Based on a synthesis of many empirical principals and methods from refer-ences, the basic principles of∑-△modulator is described in this paper at first. And the design flow of modulator with common structure is discussed. Then, a design flow of stable, high-order and high-resolution modulator is proposed. The performance parameters of such modulator design scheme are specified according to the market requirement. Based on the scheme, a 16-bit resolu-tion, full-scale input range and three-order 128 over-sampling modulator design is accomplished in this paper.
∑-△structure is adopted in this paper, the quantization bit, oversampling ratio and order of the modulator are determined following the system requirement. Six bit quantization, three-order single-loop structure modulator is implemented after a deep stability analysis of high-order sin-gle-loop modulator. This design has been implemented and verified on the Cyclone FPGA plat-form, with the real-time audio signal verification. Testing results indicates that the SNR of the de-signed DAC module’s output signals meets the resolution requirement in 16-bit data-convention application, possessing favorable compatibility and universal ability also.
The DAC module developed in this paper could be reused as an IP core in other SOC systems, holding strong application performance and innovation.
引文
1 S.R. Norsworthy, R.Schreier, and G.C. Temes, Eds., Delta-Sigma Data Converters: Theory, Design and Simulation, Piscataway, NJ:IEEE Press, 1997.
2 S.Rabii and B.A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Boston: Kluwer AP, 1999.
3 P.P. Vaidyanathan, Multirate Systems and Filter banks, Prentice Hall, Englewood Cliffs NJ, 1993
4 R. Schreier, "An empirical study of high-order single-bit delta-sigma modulators," IEEE Transactions on Circuits and Systems, vol. 40, no.8, pp. 461-466, Aug. 1993.
5 W.L.Lee," A novel higher-order interpolative modulator topology for high resolution over-sampling A/D converters," Master's thesis, Massachusetts Institute of Technology, Cambridge, MA, Jun. 1987.
6 R.E. Crochiere, L. R. Rabiner, "Interplolation and decimation of digital signals ----a tutorial review," Proc.IEEE, vol.69, no.3, pp.300-331, Mar. 1981.
7 J.C. Candy, "A use of limit cycle oscillations to obtain robust analog-to-digital vonverters," IEEE Transactions on Communications, vol. com-22, no.3, pp. 298-305, Mar. 1974.
8 S.Hein and A.Zakhor, "On the stability of sigma delta modulators," IEEE Transacions on Signal Processing, vol. 41, no. 7, pp. 2322-2348, Jul. 1993.
9 F.Colodro, A. Torralba, and J.L. Mora, "Digital noise-shaping of residues in dual-quantization sigma-delta modulators," IEEE Transactions on Circuits and System, vol.51, no.2, pp.225-232, Feb.2004.
10 P.Kiss, J. Arias, D.Li, and V. Boccuzzi, "Stable high-order delta-sigma digital-to-analog con-verters," IEEE Transactions on Circuits and Systems, vol. 51, no.1, pp.200-205, Jan.2004.
11 R. Adams, “Design and implementation of an audio 18-bit analog-to-digital convert using oversampling techniques” J.Audio Eng.Soc.1986.
12 Schreier R.IEEE Trans Circuits and System-II,1993,40(8):461~466
13 Fernando Medeiro,Angel Perez-Verdu and Angel Rodriguez-Vazquez “Top-Down Design of High-Performance Sigma-Delta Modulators.” KLUWER ACADEMIC PUBLISHERS. 1999
14 Jurgen van Engelen and Rudy van de Plassche “Bandpass Sigma Delta Modulators Stability Analysis Performance and Design Aspects” KLUWER ACADEMIC PUBLISHERS 1999
15 H.Inose, Y.Yasuda and J.Marakami, “A telemetering system by code modulation, delta-sigma modulation,” IRE Trans.on Space, Electronics and Telemetry, SET-8,pp.204-209, Sept.1962
16 Opt Eynde. “A CMOS four-order 14b 500k samples/s sigma-delta ADC converter.” Proc IEEE ISSCC’91,1991.62~63
17 P.Naus, E.Dijkmans, E.Stikvoort, A McKnight, D.Holland and W.Bradinal, "A CMOS Stereo 16-bit D/A Converter for Digital Audio", IEEE Journal of Solid-State Circuits,vol.SC-22, pp.390-394,June 1987.
18 Ronald E.Crochiere and Lawrence R.Rabiner Multirate Digtal Signal Processing Pre-tice-Hall ,Inc 1983
19 S.Park, “A real-time implementation of half-band filters to obtain 18-20 bit resolution from the DSP56ADC16 Sigma-Delta A/D converter,” Proc. International Conference on Acoustics, Speech and Signal Processing, Vol.2. pp.989-992, Albuquerque, NM, April 3-6, 1990.
20 Mikael Gustavsson and Nianxiong Nick Tan “CMOS Data Converters for Communications” KLUWER ACADEMIC PUBLISHERS. 1999
21 Y.Matsuya, K.Uchimura, A.Iwata and T.Kaneo, "A 17-bit Oversampling D-to-A Conversion Technology Using Multistage Noise Shaping", IEEE Journal of Solid-State Cir-cuits,vol.SC-24,pp.969-975,Aug.1989.
22 Chao, K.C.-H.; Nadeem, S.; Lee, W.L.; Sodini, C.G.. “A higher order topology for interpola-tive modulators for oversampling A/D converters”. IEEE Circuits and Systems, 1990;37(3):309~318
23 B.Kup, E.Dijkmans, H.Naus and J.Sneep, "A Bitstream Digital-to-Analog Converter with l8b Resolution", in Proc.IEEE Int. Solid-State Circuits Conference,vol.34,pp.70-71,Feb.1991.
24 T.Saramaki, T.Karema, T.Ritoniemi and H.Tenhunen, " Multiplier-Free Decimator Algo-rithms for Superresolution Oversampled Converters", in Proc. IEEE Int. Symp.on Circuits and Systems, May 1990, pp.3275-3278.
25 T.Saramaki, T.Karema, T.Ritoniemi, J.Isoaho and H.Tenhunen, "VLSI-Realizable Multip-lier-Free Interpolators for Sigma-Delta D/A Converters", in Proc.Int.Conf.on Circuitsystems, July 1989,pp.60-63.
26 T.Saramaki, T.Karema, T.Ritoniemi and H.Tenhunen, "VLSI-Realizable Multiplier-Free In-terpolators for High-Order Sigma-Delta D/A Converters, in Proc.Mediterranean Electrotech-nical Conference, May 1991, pp.295-298.
27 T.Karema, T.Ritoniemi and H.Tenhunen, "An Oversampled Sigma-Delta A/D Converter Cir-cuit Using Two-Stage Fourth Order Modulator", in Proc.IEEE Int.Symp.on Circuits and Sys-tems, May 1990, pp.3279-3282.
28 T.Ritoniemi,T.Karema,and H.Tenhunen, "Design of Stable High Order 1-bit Sigma-Delta Modulators", in Proc.IEEE Int.Symp.on Circuits and Systems, May 1990, pp.3267-3270.
29 T.Karema, T.Ritoniemi and H.Tenhunen, "Intermodulation in Sigma-Delta D/AConverters", in Proc.IEEE Int.Symp.on Circuits and System, June 1990, pp. 1625-1628.
30 F.F.Tsui, “LSI/VLSI Testability Design”, McGraw-Hill Inc.,1988, ch.7.2.
31 F.Op't Eynde, "High-Performance Analog Interfaces for Digital Signal Processors",PhD. Dissertation,Catholic University of Leuven, Leuven, Nov.1990, pp.201-232.
32 S.Harris, "The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters,and on Oversampling Delta-Sigma ADCs",in Journal of the Audio Engineering Society,vol.38,pp.537-542,July/Aug.1990.
33 L.T.Bruton, "Network Transfer Functions Using the Concept of Frequency-Dependent Nega-tive Resistance", IEEE Trans. Circuit Theory, vol.CT-16, pp.406-408, 1969.
34 Y.Matsuya, et. al, “A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping,” IEEE J.of Solid-State Circuits, Vol. SC-22, No.6, pp.921-929, Dec.1987.
35 P.A. Francese, P.Ferrat, and Q.Huang, "A 13b 1.1Mhz over-sampled DAC with semidigital reconstruction filtering," IEEE Journal of Solid-State Circuits, vol. 39, pp. 2098-2106, Dec,2004.
36 J.W. Kim, B.M. Min, J.S. Yoo, S.W.Kim, "An area-efficient sigma-delta DAC with a cur-rent-mode semidigital IFIR reconstruction filter," Proc. ISCAS'98, vol. 1, pp. 344-347, Jun.1998.
37 Y.Gao and H. Tenhunen, "Implementation aspects of an oversampling D/A converter for DMT-ADSL systems," Preceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, vol.3, pp.1397-1400, Sep. 1999
38 V. Peluso, A. Marques, M.steyaert, and W. Sansen, "Optimal parameters for single loop Σ-Δ modulators," IEEE Transactions on Circuits and Systems II: Analog and Digital Processing, vol. 45, pp.1232-1241, Sep.1998.
39 M.J. Borkowski, T. A. D. Riley, J.Hakkinen, and J. Kostamovaara, "A practical Σ-Δ modula-tor design method based on periodical behavior analysis," IEEE Transactions on Circuits and Systems II: Analog and Digital Processing, vol.52, pp.626-630, Oct.2005.
40 E.Gaalaas, B.Y.Liu, N.Nishimura, R.Adams, and K.Sweetland, "Integrated stereo class D amplifier," IEEE Journal of Solid-State Circuits, vol.40, no.12, pp.2388-2397, Dec. 2005.
41 J.Zhang, P.V. Brennan, D.Jiang, E.Vinogradova, and P.D. Smith, "Stability analysis of a sig-ma delta modulator," Proc.ISCAS'03, vol.1, pp.I-961-I-964, May. 2003.
42 M.Neitola, A.Kivi, and T.Rahkonen, "Design of a wideband transmit delta-sigma DAC," Proc. ICECS 2001, vol.2, pp. 1053-1056, Sep.2001.
43 S.H. Yu and J.S. Hu, "Sigma-delta modulators operated in optimization mode," Proc. IS-CAS'04, vol.1, pp.I-1080-I-1083, May. 2004.
44 M.Yagyu and A. Nishihara, "Fast and efficient algorithm to design noise-shaping FIR filters for high-order overload-free stable sigma-delta modulators," Proc. ISCAS'04, vol.1,pp.I-469-I-472, May.2004.
45 R.C.C. Cheung, K. P.Pun, S.C.L. Yuen, K.H. Tsoi and P.H.W. Leong, "An FPGA-based re-configurable 24-bit 96kHZ sigma-delta audio DAC," Proc. IEEE International Conference on Field-Programmable Technology(FPT) 2003, pp. 110-117, Dec. 2003
46 T. H. Kuo, K.D. Chen, and J.R. Chen, "Automatic coefficients design of high-order sig-ma-delta modulators," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, no.1, pp.6-15,Jan. 1999.
47 Candy, J., "A Use of Double Integration in Sigma Delta Modulation", Communications, IEEE Transactions vol.33, Issue 3, pp.249 – 258, Mar 1985
48 A.V. Oppenheim, R.W. Schafer, J.R. BUck 著,刘树棠,黄建国译,离散时间信号处理(第二版),西安交通大学出版社,2001
49 S.K. Mitra 著,孙洪,余翔宇等译,数字信号处理-----基于计算机的方法(第二版),电子工业出版社,2005
50 U.M. Baese 著, 刘凌,胡永生译,数字信号处理的 FPGA 实现,清华大学出版社,2003
51 杨小牛,楼才义,徐建良,软件无线电原理与应用,电子工业出版社,2001
52 王正宏,凌燮亭,“多比特增量-综合调制器中的降噪环路”,中国第十六届电路与系统学术会议论文集, 2001: 9-13
53 唐长文,吴俊军,闵昊,“新型高速CSD编码滤波器及VLSI的实现”, 半导体技术, 2001, 26(11):22-25
54 赵建华,冯正和,“一种 Σ-Δ 音频 DAC 的设计”,电声技术,2004(11):29-32
55 刘晨,王森章,“应用于 ADSL 的多位 Σ-Δ 数/模转换器的设计”,微电子学,2004,8,34(4):476-478
56 刘洪江,高清运,秦世才,“Σ-ΔA/D 转换器中数字下变频解调器的设计与实现”,微电子学,2005,2,35(1):8-10
57 米佳,“16 位 Σ-ΔDAC 的 Σ-Δ 调制器的研究和设计”,硕士学位论文,电子科技大学,2002
58 闾晓晨,“音频过采样 D/A 转换器的理论与设计研究”,硕士学位论文,西安交通大学,2004
2 S.Rabii and B.A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Boston: Kluwer AP, 1999.
3 P.P. Vaidyanathan, Multirate Systems and Filter banks, Prentice Hall, Englewood Cliffs NJ, 1993
4 R. Schreier, "An empirical study of high-order single-bit delta-sigma modulators," IEEE Transactions on Circuits and Systems, vol. 40, no.8, pp. 461-466, Aug. 1993.
5 W.L.Lee," A novel higher-order interpolative modulator topology for high resolution over-sampling A/D converters," Master's thesis, Massachusetts Institute of Technology, Cambridge, MA, Jun. 1987.
6 R.E. Crochiere, L. R. Rabiner, "Interplolation and decimation of digital signals ----a tutorial review," Proc.IEEE, vol.69, no.3, pp.300-331, Mar. 1981.
7 J.C. Candy, "A use of limit cycle oscillations to obtain robust analog-to-digital vonverters," IEEE Transactions on Communications, vol. com-22, no.3, pp. 298-305, Mar. 1974.
8 S.Hein and A.Zakhor, "On the stability of sigma delta modulators," IEEE Transacions on Signal Processing, vol. 41, no. 7, pp. 2322-2348, Jul. 1993.
9 F.Colodro, A. Torralba, and J.L. Mora, "Digital noise-shaping of residues in dual-quantization sigma-delta modulators," IEEE Transactions on Circuits and System, vol.51, no.2, pp.225-232, Feb.2004.
10 P.Kiss, J. Arias, D.Li, and V. Boccuzzi, "Stable high-order delta-sigma digital-to-analog con-verters," IEEE Transactions on Circuits and Systems, vol. 51, no.1, pp.200-205, Jan.2004.
11 R. Adams, “Design and implementation of an audio 18-bit analog-to-digital convert using oversampling techniques” J.Audio Eng.Soc.1986.
12 Schreier R.IEEE Trans Circuits and System-II,1993,40(8):461~466
13 Fernando Medeiro,Angel Perez-Verdu and Angel Rodriguez-Vazquez “Top-Down Design of High-Performance Sigma-Delta Modulators.” KLUWER ACADEMIC PUBLISHERS. 1999
14 Jurgen van Engelen and Rudy van de Plassche “Bandpass Sigma Delta Modulators Stability Analysis Performance and Design Aspects” KLUWER ACADEMIC PUBLISHERS 1999
15 H.Inose, Y.Yasuda and J.Marakami, “A telemetering system by code modulation, delta-sigma modulation,” IRE Trans.on Space, Electronics and Telemetry, SET-8,pp.204-209, Sept.1962
16 Opt Eynde. “A CMOS four-order 14b 500k samples/s sigma-delta ADC converter.” Proc IEEE ISSCC’91,1991.62~63
17 P.Naus, E.Dijkmans, E.Stikvoort, A McKnight, D.Holland and W.Bradinal, "A CMOS Stereo 16-bit D/A Converter for Digital Audio", IEEE Journal of Solid-State Circuits,vol.SC-22, pp.390-394,June 1987.
18 Ronald E.Crochiere and Lawrence R.Rabiner Multirate Digtal Signal Processing Pre-tice-Hall ,Inc 1983
19 S.Park, “A real-time implementation of half-band filters to obtain 18-20 bit resolution from the DSP56ADC16 Sigma-Delta A/D converter,” Proc. International Conference on Acoustics, Speech and Signal Processing, Vol.2. pp.989-992, Albuquerque, NM, April 3-6, 1990.
20 Mikael Gustavsson and Nianxiong Nick Tan “CMOS Data Converters for Communications” KLUWER ACADEMIC PUBLISHERS. 1999
21 Y.Matsuya, K.Uchimura, A.Iwata and T.Kaneo, "A 17-bit Oversampling D-to-A Conversion Technology Using Multistage Noise Shaping", IEEE Journal of Solid-State Cir-cuits,vol.SC-24,pp.969-975,Aug.1989.
22 Chao, K.C.-H.; Nadeem, S.; Lee, W.L.; Sodini, C.G.. “A higher order topology for interpola-tive modulators for oversampling A/D converters”. IEEE Circuits and Systems, 1990;37(3):309~318
23 B.Kup, E.Dijkmans, H.Naus and J.Sneep, "A Bitstream Digital-to-Analog Converter with l8b Resolution", in Proc.IEEE Int. Solid-State Circuits Conference,vol.34,pp.70-71,Feb.1991.
24 T.Saramaki, T.Karema, T.Ritoniemi and H.Tenhunen, " Multiplier-Free Decimator Algo-rithms for Superresolution Oversampled Converters", in Proc. IEEE Int. Symp.on Circuits and Systems, May 1990, pp.3275-3278.
25 T.Saramaki, T.Karema, T.Ritoniemi, J.Isoaho and H.Tenhunen, "VLSI-Realizable Multip-lier-Free Interpolators for Sigma-Delta D/A Converters", in Proc.Int.Conf.on Circuitsystems, July 1989,pp.60-63.
26 T.Saramaki, T.Karema, T.Ritoniemi and H.Tenhunen, "VLSI-Realizable Multiplier-Free In-terpolators for High-Order Sigma-Delta D/A Converters, in Proc.Mediterranean Electrotech-nical Conference, May 1991, pp.295-298.
27 T.Karema, T.Ritoniemi and H.Tenhunen, "An Oversampled Sigma-Delta A/D Converter Cir-cuit Using Two-Stage Fourth Order Modulator", in Proc.IEEE Int.Symp.on Circuits and Sys-tems, May 1990, pp.3279-3282.
28 T.Ritoniemi,T.Karema,and H.Tenhunen, "Design of Stable High Order 1-bit Sigma-Delta Modulators", in Proc.IEEE Int.Symp.on Circuits and Systems, May 1990, pp.3267-3270.
29 T.Karema, T.Ritoniemi and H.Tenhunen, "Intermodulation in Sigma-Delta D/AConverters", in Proc.IEEE Int.Symp.on Circuits and System, June 1990, pp. 1625-1628.
30 F.F.Tsui, “LSI/VLSI Testability Design”, McGraw-Hill Inc.,1988, ch.7.2.
31 F.Op't Eynde, "High-Performance Analog Interfaces for Digital Signal Processors",PhD. Dissertation,Catholic University of Leuven, Leuven, Nov.1990, pp.201-232.
32 S.Harris, "The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters,and on Oversampling Delta-Sigma ADCs",in Journal of the Audio Engineering Society,vol.38,pp.537-542,July/Aug.1990.
33 L.T.Bruton, "Network Transfer Functions Using the Concept of Frequency-Dependent Nega-tive Resistance", IEEE Trans. Circuit Theory, vol.CT-16, pp.406-408, 1969.
34 Y.Matsuya, et. al, “A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping,” IEEE J.of Solid-State Circuits, Vol. SC-22, No.6, pp.921-929, Dec.1987.
35 P.A. Francese, P.Ferrat, and Q.Huang, "A 13b 1.1Mhz over-sampled DAC with semidigital reconstruction filtering," IEEE Journal of Solid-State Circuits, vol. 39, pp. 2098-2106, Dec,2004.
36 J.W. Kim, B.M. Min, J.S. Yoo, S.W.Kim, "An area-efficient sigma-delta DAC with a cur-rent-mode semidigital IFIR reconstruction filter," Proc. ISCAS'98, vol. 1, pp. 344-347, Jun.1998.
37 Y.Gao and H. Tenhunen, "Implementation aspects of an oversampling D/A converter for DMT-ADSL systems," Preceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, vol.3, pp.1397-1400, Sep. 1999
38 V. Peluso, A. Marques, M.steyaert, and W. Sansen, "Optimal parameters for single loop Σ-Δ modulators," IEEE Transactions on Circuits and Systems II: Analog and Digital Processing, vol. 45, pp.1232-1241, Sep.1998.
39 M.J. Borkowski, T. A. D. Riley, J.Hakkinen, and J. Kostamovaara, "A practical Σ-Δ modula-tor design method based on periodical behavior analysis," IEEE Transactions on Circuits and Systems II: Analog and Digital Processing, vol.52, pp.626-630, Oct.2005.
40 E.Gaalaas, B.Y.Liu, N.Nishimura, R.Adams, and K.Sweetland, "Integrated stereo class D amplifier," IEEE Journal of Solid-State Circuits, vol.40, no.12, pp.2388-2397, Dec. 2005.
41 J.Zhang, P.V. Brennan, D.Jiang, E.Vinogradova, and P.D. Smith, "Stability analysis of a sig-ma delta modulator," Proc.ISCAS'03, vol.1, pp.I-961-I-964, May. 2003.
42 M.Neitola, A.Kivi, and T.Rahkonen, "Design of a wideband transmit delta-sigma DAC," Proc. ICECS 2001, vol.2, pp. 1053-1056, Sep.2001.
43 S.H. Yu and J.S. Hu, "Sigma-delta modulators operated in optimization mode," Proc. IS-CAS'04, vol.1, pp.I-1080-I-1083, May. 2004.
44 M.Yagyu and A. Nishihara, "Fast and efficient algorithm to design noise-shaping FIR filters for high-order overload-free stable sigma-delta modulators," Proc. ISCAS'04, vol.1,pp.I-469-I-472, May.2004.
45 R.C.C. Cheung, K. P.Pun, S.C.L. Yuen, K.H. Tsoi and P.H.W. Leong, "An FPGA-based re-configurable 24-bit 96kHZ sigma-delta audio DAC," Proc. IEEE International Conference on Field-Programmable Technology(FPT) 2003, pp. 110-117, Dec. 2003
46 T. H. Kuo, K.D. Chen, and J.R. Chen, "Automatic coefficients design of high-order sig-ma-delta modulators," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, no.1, pp.6-15,Jan. 1999.
47 Candy, J., "A Use of Double Integration in Sigma Delta Modulation", Communications, IEEE Transactions vol.33, Issue 3, pp.249 – 258, Mar 1985
48 A.V. Oppenheim, R.W. Schafer, J.R. BUck 著,刘树棠,黄建国译,离散时间信号处理(第二版),西安交通大学出版社,2001
49 S.K. Mitra 著,孙洪,余翔宇等译,数字信号处理-----基于计算机的方法(第二版),电子工业出版社,2005
50 U.M. Baese 著, 刘凌,胡永生译,数字信号处理的 FPGA 实现,清华大学出版社,2003
51 杨小牛,楼才义,徐建良,软件无线电原理与应用,电子工业出版社,2001
52 王正宏,凌燮亭,“多比特增量-综合调制器中的降噪环路”,中国第十六届电路与系统学术会议论文集, 2001: 9-13
53 唐长文,吴俊军,闵昊,“新型高速CSD编码滤波器及VLSI的实现”, 半导体技术, 2001, 26(11):22-25
54 赵建华,冯正和,“一种 Σ-Δ 音频 DAC 的设计”,电声技术,2004(11):29-32
55 刘晨,王森章,“应用于 ADSL 的多位 Σ-Δ 数/模转换器的设计”,微电子学,2004,8,34(4):476-478
56 刘洪江,高清运,秦世才,“Σ-ΔA/D 转换器中数字下变频解调器的设计与实现”,微电子学,2005,2,35(1):8-10
57 米佳,“16 位 Σ-ΔDAC 的 Σ-Δ 调制器的研究和设计”,硕士学位论文,电子科技大学,2002
58 闾晓晨,“音频过采样 D/A 转换器的理论与设计研究”,硕士学位论文,西安交通大学,2004