高精度、低功耗流水线型模数转换器的研究与设计
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摘要
流水线型模数转换器被广泛地应用于图像处理、通信基站、数字视频和快速以太网等领域。而对于应用越来越广泛的手持移动终端而言,低功耗对于产品电池的使用寿命起着至关重要的作用。同时随着人们对音质、画质等感官体验的要求越来越高,以及更为细致的数据信息量要求,高精度也成了模数转换器系统设计中一个极为重要的方面。通常实现低功耗的方法往往会产生各种误差从而导致精度降低,同样实现高精度又往往需要以增加功耗为代价,因此如何同时实现高精度和低功耗成为了研究的热点和难点。
论文主要研究了应用于数字视频领域的流水线型模数转换器的低功耗及高精度实现方法。从采用级间运放共享技术来降低功耗为切入点,首先分析了传统运放共享结构中影响电路精度的因素。其次为了消除这些因素的影响,提出了新的电路结构和设计技术,从而达到了同时实现高精度和低功耗的目的。搭建了流水线模数转换器Matlab模型,引入了各种非理想因素参与行为级仿真,建立了系统级的设计框架。最后完成了整个流水线模数转换器的电路设计、版图布局和芯片测试等全部流程。
主要研究成果和工作有以下几个方面：
1)从降低运放功耗入手,选择功耗最低的单级套筒式运放,同时采用级间运放共享和逐级缩减等技术,实现低功耗设计。
2)详细分析了传统级间运放共享结构中存在的记忆效应、级间信号串扰以及共享开关引入的电荷注入和时钟馈通等各种影响电路精度的因素。为了消除这些因素的影响,提出了一种新的双输入开关内置运放共享结构的MDAC电路。
3)提出采用两组输入差分对管的结构,共享运放的两流水级各使用一组,每组差分对管在保持时段交替参与运放工作,而在采样时段则交替的连接到共模输入电压进行复位,从而完全消除记忆效应,并且不需要额外的复位时间。
4)提出将运放共享开关嵌入在运放内部,有效消除了级间信号串扰通路；因此,开关产生的电荷注入和时钟馈通效应也不会对信号建立精度造成影响；同时消除了传统结构中采用外置开关所引入的寄生电阻对运放失调的影响。内置的共享开关仅消耗约30mV的电压裕度,不会影响运放的输出摆幅。
5)提出采用双相交叠时钟来控制运放共享开关,解决了采用传统非交叠时钟导致的大信号建立恶化的问题。通过采用与被偏置电路一致的结构,改进了宽摆幅运放偏置电路,与系统中各运放都能获得更好的匹配。
6)从传递函数的角度建立了流水线型模数转换器的Matlab系统级模型,并引入了诸如电容失配、噪声、运放单位增益带宽、运放压摆率、时钟抖动以及比较器失调等非理想因素影响,从而指导电路设计。模型仿真结果与流片结果契合。
7)在SMIC 0.18-μm、1.8V电源电压、单层多晶硅六层金属的标准CMOS工艺下完成了一款10 bit 80 MSps的流水线型模数转换器的电路设计、版图布局、仿真验证以及芯片测试等工作。
采用这种新型双输入开关内置运放共享的MDAC结构可以在不增加额外时钟、功耗、面积的条件下,消除多种制约MDAC精度的误差来源,从而有效提高系统精度。
此外,基于双输入开关内置运放的良好隔离特性,对电路进行进一步的优化和改进,令采样保持电路与第一级MDAC共享运放,从而完全避免运放功耗的额外消耗,继续显著降低系统功耗。
流片测试结果显示,本论文设计的10-bit 80 MSps模数转换器有效位(ENOB)可以达到9.69 bit,无杂散动态范围(SFDR)可以达到76 dB,并且在整个奈奎斯特带宽内都保持着9.62bit以上的ENOB。当输入信号超过奈奎斯特频率,甚至接近采样频率时,ENOB仍可以达到超过9.47 bit的精度。此外,当采样频率提高到100MSps时,仍可以达到超过9.1 bit的有效位。芯片核心功耗为28mW,性能系数(FOM)为0.42pJ/step。其中ENOB和SFDR两项指标优于近几年收录在JSSC、ISSCC和CICC等国际项级期刊会议上相同分辨率流水线模数转换器的研究成果,FOM达到了这些研究成果中的较高水平,能够实现低功耗高精度的数字视频及SOC嵌入式应用。
Pipelined analog-to-digital converter (ADC) is widely used in the systems of image signal processing, base stations and digital video, fast Ethernet, ect. For hand-held mobile terminals, low power devices play a vital role for the life of the battery. At the same time, as people demanding of sensory experiences such as sound, picture quality have become increasingly and the requirement of more detailed information, design has become a very important aspect.Low power consump-tion usually tends to reduce the accuracy while high accuracy is often needed to increase the cost of power. Thus, how to achieve high accuracy and low power consumption simultaneously has become a hot research spot.
This work focuses on the high accuracy and low-power pipelined ADC for digital video system. The opamp-sharing technology is used to achieve low power consumption at the cost of the resolution reduction, since the conventional opamp-sharing ADC has some serious problems. To get rid of these problems, an new architechture of MDAC was proposed to improve the system accuracy. A Matlab model of pipelined ADC which guide the actual circuit design is structured, variety of non-ideal factors are involved in the behavioral simulation. By using this MDAC, this work presents the transistor level of pipelined ADC. Finally, layout and chip testing are described.
The specific research contributions of this work include:
1) Starting from reducing the power consumption of the opamp telescopic opamp was selected for its lowest power consumption. More methods such as opamp-sharing between successive stage and stage-scaling-down were adopted to achieve low-power design.
2) To get rid of the problems of memory effect, successive stage crosstalk, charge injection and clock feedthrough, a switch-embedded MDAC with dual NMOS differential input pairs current-reuse OTA is proposed.
3) The dual NMOS differential input pairs was proposed to eliminate the memory effect. Since both input pairs are reset to a common-mode input voltage alternately, the memory effect is completely eliminated without any additional clock phase.
4) By embedding the opamp-sharing switches into OTA, the effect of the inter-stage crosstalk path, charge injection, clock feedthrough and the offset introduced by parasitic resistance of opamp-sharing switches ware eliminated and does not affect the signal settling accuracy. The embedded switches only consumed about 30mV of votage margin, so not affect the opamp's output swing.
5) The two-phase non-overlapping clock is always used in a pipelined ADC but is not suitable for controlling the opamp-sharing switches in the proposed OTA. To achieving a well matching, a optimized stable high-swing bias circuit is employed for the OTA.
6) Based on the signal transfer function, A Matlab model of pipelined ADC is structured to guide the circuit design. By involved the effect of many non-ideal factors such as mismatch, noise, GBW, slew rate, jitter and offset, this model is reasonable according the silicon results.
7) In the SMIC 0.18-μm,1.8V supply voltage, single-poly six-metal standard CMOS process, the circuit and layout design, simulation and chip testing of a 10 bit 80MSps pipelined ADC are completed.
By using the proposed switch-embedded opamp-sharing MDAC based on a dual NMOS input pairs current-reuse opamp, an improved accuracy is achieved without any additional power and area consumption and clock phase.
Further more, built on the good isolation characteristic of the dual-input switch-emmbeded opamp, a new circuit structure of opamp-sharing between S/H circuit and the first MDAC stage was proposed to significantly reduce power consumption by avoiding the extra power consumption of opamp.
The ADC achieves a peak ENOB of 9.69 bit and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. When input frequency is close to sample rate, the ADC still maintains 9.47 ENOB. When sample rate rises to 100MHz, there is still 9.1 ENOB. The chip consumes 28mW an FOM achieves 0.42 pJ/step. The measured SNDR and SFDR are better than other recently published works of 10-bit pipelined ADCs on JSSC, ISSCC and CICC, and FOM has achieved a higher level. This work can be used in low power consumption and high accuracy digital video system an embedded in applications of SOC.
论文主要研究了应用于数字视频领域的流水线型模数转换器的低功耗及高精度实现方法。从采用级间运放共享技术来降低功耗为切入点,首先分析了传统运放共享结构中影响电路精度的因素。其次为了消除这些因素的影响,提出了新的电路结构和设计技术,从而达到了同时实现高精度和低功耗的目的。搭建了流水线模数转换器Matlab模型,引入了各种非理想因素参与行为级仿真,建立了系统级的设计框架。最后完成了整个流水线模数转换器的电路设计、版图布局和芯片测试等全部流程。
主要研究成果和工作有以下几个方面：
1)从降低运放功耗入手,选择功耗最低的单级套筒式运放,同时采用级间运放共享和逐级缩减等技术,实现低功耗设计。
2)详细分析了传统级间运放共享结构中存在的记忆效应、级间信号串扰以及共享开关引入的电荷注入和时钟馈通等各种影响电路精度的因素。为了消除这些因素的影响,提出了一种新的双输入开关内置运放共享结构的MDAC电路。
3)提出采用两组输入差分对管的结构,共享运放的两流水级各使用一组,每组差分对管在保持时段交替参与运放工作,而在采样时段则交替的连接到共模输入电压进行复位,从而完全消除记忆效应,并且不需要额外的复位时间。
4)提出将运放共享开关嵌入在运放内部,有效消除了级间信号串扰通路；因此,开关产生的电荷注入和时钟馈通效应也不会对信号建立精度造成影响；同时消除了传统结构中采用外置开关所引入的寄生电阻对运放失调的影响。内置的共享开关仅消耗约30mV的电压裕度,不会影响运放的输出摆幅。
5)提出采用双相交叠时钟来控制运放共享开关,解决了采用传统非交叠时钟导致的大信号建立恶化的问题。通过采用与被偏置电路一致的结构,改进了宽摆幅运放偏置电路,与系统中各运放都能获得更好的匹配。
6)从传递函数的角度建立了流水线型模数转换器的Matlab系统级模型,并引入了诸如电容失配、噪声、运放单位增益带宽、运放压摆率、时钟抖动以及比较器失调等非理想因素影响,从而指导电路设计。模型仿真结果与流片结果契合。
7)在SMIC 0.18-μm、1.8V电源电压、单层多晶硅六层金属的标准CMOS工艺下完成了一款10 bit 80 MSps的流水线型模数转换器的电路设计、版图布局、仿真验证以及芯片测试等工作。
采用这种新型双输入开关内置运放共享的MDAC结构可以在不增加额外时钟、功耗、面积的条件下,消除多种制约MDAC精度的误差来源,从而有效提高系统精度。
此外,基于双输入开关内置运放的良好隔离特性,对电路进行进一步的优化和改进,令采样保持电路与第一级MDAC共享运放,从而完全避免运放功耗的额外消耗,继续显著降低系统功耗。
流片测试结果显示,本论文设计的10-bit 80 MSps模数转换器有效位(ENOB)可以达到9.69 bit,无杂散动态范围(SFDR)可以达到76 dB,并且在整个奈奎斯特带宽内都保持着9.62bit以上的ENOB。当输入信号超过奈奎斯特频率,甚至接近采样频率时,ENOB仍可以达到超过9.47 bit的精度。此外,当采样频率提高到100MSps时,仍可以达到超过9.1 bit的有效位。芯片核心功耗为28mW,性能系数(FOM)为0.42pJ/step。其中ENOB和SFDR两项指标优于近几年收录在JSSC、ISSCC和CICC等国际项级期刊会议上相同分辨率流水线模数转换器的研究成果,FOM达到了这些研究成果中的较高水平,能够实现低功耗高精度的数字视频及SOC嵌入式应用。
Pipelined analog-to-digital converter (ADC) is widely used in the systems of image signal processing, base stations and digital video, fast Ethernet, ect. For hand-held mobile terminals, low power devices play a vital role for the life of the battery. At the same time, as people demanding of sensory experiences such as sound, picture quality have become increasingly and the requirement of more detailed information, design has become a very important aspect.Low power consump-tion usually tends to reduce the accuracy while high accuracy is often needed to increase the cost of power. Thus, how to achieve high accuracy and low power consumption simultaneously has become a hot research spot.
This work focuses on the high accuracy and low-power pipelined ADC for digital video system. The opamp-sharing technology is used to achieve low power consumption at the cost of the resolution reduction, since the conventional opamp-sharing ADC has some serious problems. To get rid of these problems, an new architechture of MDAC was proposed to improve the system accuracy. A Matlab model of pipelined ADC which guide the actual circuit design is structured, variety of non-ideal factors are involved in the behavioral simulation. By using this MDAC, this work presents the transistor level of pipelined ADC. Finally, layout and chip testing are described.
The specific research contributions of this work include:
1) Starting from reducing the power consumption of the opamp telescopic opamp was selected for its lowest power consumption. More methods such as opamp-sharing between successive stage and stage-scaling-down were adopted to achieve low-power design.
2) To get rid of the problems of memory effect, successive stage crosstalk, charge injection and clock feedthrough, a switch-embedded MDAC with dual NMOS differential input pairs current-reuse OTA is proposed.
3) The dual NMOS differential input pairs was proposed to eliminate the memory effect. Since both input pairs are reset to a common-mode input voltage alternately, the memory effect is completely eliminated without any additional clock phase.
4) By embedding the opamp-sharing switches into OTA, the effect of the inter-stage crosstalk path, charge injection, clock feedthrough and the offset introduced by parasitic resistance of opamp-sharing switches ware eliminated and does not affect the signal settling accuracy. The embedded switches only consumed about 30mV of votage margin, so not affect the opamp's output swing.
5) The two-phase non-overlapping clock is always used in a pipelined ADC but is not suitable for controlling the opamp-sharing switches in the proposed OTA. To achieving a well matching, a optimized stable high-swing bias circuit is employed for the OTA.
6) Based on the signal transfer function, A Matlab model of pipelined ADC is structured to guide the circuit design. By involved the effect of many non-ideal factors such as mismatch, noise, GBW, slew rate, jitter and offset, this model is reasonable according the silicon results.
7) In the SMIC 0.18-μm,1.8V supply voltage, single-poly six-metal standard CMOS process, the circuit and layout design, simulation and chip testing of a 10 bit 80MSps pipelined ADC are completed.
By using the proposed switch-embedded opamp-sharing MDAC based on a dual NMOS input pairs current-reuse opamp, an improved accuracy is achieved without any additional power and area consumption and clock phase.
Further more, built on the good isolation characteristic of the dual-input switch-emmbeded opamp, a new circuit structure of opamp-sharing between S/H circuit and the first MDAC stage was proposed to significantly reduce power consumption by avoiding the extra power consumption of opamp.
The ADC achieves a peak ENOB of 9.69 bit and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. When input frequency is close to sample rate, the ADC still maintains 9.47 ENOB. When sample rate rises to 100MHz, there is still 9.1 ENOB. The chip consumes 28mW an FOM achieves 0.42 pJ/step. The measured SNDR and SFDR are better than other recently published works of 10-bit pipelined ADCs on JSSC, ISSCC and CICC, and FOM has achieved a higher level. This work can be used in low power consumption and high accuracy digital video system an embedded in applications of SOC.
引文
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